Lines Matching refs:index
55 int arm_gic_get_active_irq(rt_uint32_t index) in arm_gic_get_active_irq() argument
59 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_active_irq()
63 irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; in arm_gic_get_active_irq()
67 void arm_gic_ack(rt_uint32_t index, int irq) in arm_gic_ack() argument
69 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_ack()
77 void arm_gic_mask(rt_uint32_t index, int irq) in arm_gic_mask() argument
81 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_mask()
83 irq = irq - _gic_table[index].offset; in arm_gic_mask()
90 GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; in arm_gic_mask()
94 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
98 void arm_gic_umask(rt_uint32_t index, int irq) in arm_gic_umask() argument
102 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_umask()
104 irq = irq - _gic_table[index].offset; in arm_gic_umask()
111 GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; in arm_gic_umask()
115 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_umask()
119 rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq) in arm_gic_get_pending_irq() argument
123 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_pending_irq()
125 irq = irq - _gic_table[index].offset; in arm_gic_get_pending_irq()
130 pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_pending_irq()
135 … pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_pending_irq()
150 void arm_gic_set_pending_irq(rt_uint32_t index, int irq) in arm_gic_set_pending_irq() argument
152 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_pending_irq()
154 irq = irq - _gic_table[index].offset; in arm_gic_set_pending_irq()
159 GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); in arm_gic_set_pending_irq()
165 GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); in arm_gic_set_pending_irq()
169 void arm_gic_clear_pending_irq(rt_uint32_t index, int irq) in arm_gic_clear_pending_irq() argument
173 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_pending_irq()
175 irq = irq - _gic_table[index].offset; in arm_gic_clear_pending_irq()
181 GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
186 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
190 void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config) in arm_gic_set_configuration() argument
195 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_configuration()
197 irq = irq - _gic_table[index].offset; in arm_gic_set_configuration()
200 icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); in arm_gic_set_configuration()
206 GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; in arm_gic_set_configuration()
209 rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq) in arm_gic_get_configuration() argument
211 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_configuration()
213 irq = irq - _gic_table[index].offset; in arm_gic_get_configuration()
216 return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); in arm_gic_get_configuration()
219 void arm_gic_clear_active(rt_uint32_t index, int irq) in arm_gic_clear_active() argument
223 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_active()
225 irq = irq - _gic_table[index].offset; in arm_gic_clear_active()
228 GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_active()
232 void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) in arm_gic_set_cpu() argument
236 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_cpu()
238 irq = irq - _gic_table[index].offset; in arm_gic_set_cpu()
241 old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); in arm_gic_set_cpu()
246 GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; in arm_gic_set_cpu()
249 rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq) in arm_gic_get_target_cpu() argument
251 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_target_cpu()
253 irq = irq - _gic_table[index].offset; in arm_gic_get_target_cpu()
256 return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_target_cpu()
259 void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) in arm_gic_set_priority() argument
263 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_priority()
265 irq = irq - _gic_table[index].offset; in arm_gic_set_priority()
273 mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); in arm_gic_set_priority()
276 GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; in arm_gic_set_priority()
280 mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); in arm_gic_set_priority()
283 GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_set_priority()
287 rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq) in arm_gic_get_priority() argument
289 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_priority()
291 irq = irq - _gic_table[index].offset; in arm_gic_get_priority()
299 …return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U… in arm_gic_get_priority()
303 return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_priority()
307 void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value) in arm_gic_set_system_register_enable_mask() argument
309 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_system_register_enable_mask()
318 rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index) in arm_gic_get_system_register_enable_mask() argument
320 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_system_register_enable_mask()
327 void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority) in arm_gic_set_interface_prior_mask() argument
329 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_interface_prior_mask()
336 rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index) in arm_gic_get_interface_prior_mask() argument
338 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_interface_prior_mask()
345 void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point) in arm_gic_set_binary_point() argument
347 index = index; in arm_gic_set_binary_point()
353 rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index) in arm_gic_get_binary_point() argument
357 index = index; in arm_gic_get_binary_point()
362 rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq) in arm_gic_get_irq_status() argument
367 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_irq_status()
369 irq = irq - _gic_table[index].offset; in arm_gic_get_irq_status()
372 active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_irq_status()
373 pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_irq_status()
378 void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routin… in arm_gic_send_affinity_sgi() argument
412 rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index) in arm_gic_get_high_pending_irq() argument
415 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_high_pending_irq()
417 index = index; in arm_gic_get_high_pending_irq()
422 rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index) in arm_gic_get_interface_id() argument
424 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_interface_id()
426 return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); in arm_gic_get_interface_id()
429 void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group) in arm_gic_set_group() argument
434 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_group()
437 irq = irq - _gic_table[index].offset; in arm_gic_set_group()
440 igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); in arm_gic_set_group()
445 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; in arm_gic_set_group()
448 rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq) in arm_gic_get_group() argument
450 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_group()
452 irq = irq - _gic_table[index].offset; in arm_gic_get_group()
455 return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_group()
458 static int arm_gicv3_wait_rwp(rt_uint32_t index, rt_uint32_t irq) in arm_gicv3_wait_rwp() argument
463 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gicv3_wait_rwp()
470 base = _gic_table[index].redist_hw_base[cpu_id]; in arm_gicv3_wait_rwp()
475 base = _gic_table[index].dist_hw_base; in arm_gicv3_wait_rwp()
487 int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) in arm_gic_dist_init() argument
492 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_dist_init()
494 _gic_table[index].dist_hw_base = dist_base; in arm_gic_dist_init()
495 _gic_table[index].offset = irq_start; in arm_gic_dist_init()
565 int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id) in arm_gic_redist_address_set() argument
567 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_redist_address_set()
569 _gic_table[index].redist_hw_base[cpu_id] = redist_addr; in arm_gic_redist_address_set()
574 int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cp… in arm_gic_cpu_interface_address_set() argument
576 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_cpu_interface_address_set()
578 _gic_table[index].cpu_hw_base[cpu_id] = interface_addr; in arm_gic_cpu_interface_address_set()
583 int arm_gic_redist_init(rt_uint32_t index) in arm_gic_redist_init() argument
589 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_redist_init()
592 base = _gic_table[index].redist_hw_base[cpu_id]; in arm_gic_redist_init()
622 int arm_gic_cpu_init(rt_uint32_t index) in arm_gic_cpu_init() argument
625 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_cpu_init()
627 value = arm_gic_get_system_register_enable_mask(index); in arm_gic_cpu_init()
629 arm_gic_set_system_register_enable_mask(index, value); in arm_gic_cpu_init()
632 arm_gic_set_interface_prior_mask(index, 0xFFU); in arm_gic_cpu_init()
658 void arm_gic_dump_type(rt_uint32_t index) in arm_gic_dump_type() argument
662 gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); in arm_gic_dump_type()
664 (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, in arm_gic_dump_type()
665 _gic_table[index].dist_hw_base, in arm_gic_dump_type()
671 void arm_gic_dump(rt_uint32_t index) in arm_gic_dump() argument
681 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, in arm_gic_dump()
688 GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, in arm_gic_dump()
695 GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, in arm_gic_dump()