Lines Matching refs:irq
57 int irq; in arm_gic_get_active_irq() local
61 __get_gicv3_reg(ICC_IAR1, irq); in arm_gic_get_active_irq()
63 irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; in arm_gic_get_active_irq()
64 return irq; in arm_gic_get_active_irq()
67 void arm_gic_ack(rt_uint32_t index, int irq) in arm_gic_ack() argument
70 RT_ASSERT(irq >= 0U); in arm_gic_ack()
74 __set_gicv3_reg(ICC_EOIR1, irq); in arm_gic_ack()
77 void arm_gic_mask(rt_uint32_t index, int irq) in arm_gic_mask() argument
79 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_mask()
83 irq = irq - _gic_table[index].offset; in arm_gic_mask()
84 RT_ASSERT(irq >= 0U); in arm_gic_mask()
86 if (irq < 32U) in arm_gic_mask()
94 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
98 void arm_gic_umask(rt_uint32_t index, int irq) in arm_gic_umask() argument
100 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_umask()
104 irq = irq - _gic_table[index].offset; in arm_gic_umask()
105 RT_ASSERT(irq >= 0U); in arm_gic_umask()
107 if (irq < 32U) in arm_gic_umask()
115 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_umask()
119 rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq) in arm_gic_get_pending_irq() argument
125 irq = irq - _gic_table[index].offset; in arm_gic_get_pending_irq()
126 RT_ASSERT(irq >= 0U); in arm_gic_get_pending_irq()
128 if (irq >= 16U) in arm_gic_get_pending_irq()
130 pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_pending_irq()
135 … pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_pending_irq()
150 void arm_gic_set_pending_irq(rt_uint32_t index, int irq) in arm_gic_set_pending_irq() argument
154 irq = irq - _gic_table[index].offset; in arm_gic_set_pending_irq()
155 RT_ASSERT(irq >= 0U); in arm_gic_set_pending_irq()
157 if (irq >= 16U) in arm_gic_set_pending_irq()
159 GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); in arm_gic_set_pending_irq()
165 GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); in arm_gic_set_pending_irq()
169 void arm_gic_clear_pending_irq(rt_uint32_t index, int irq) in arm_gic_clear_pending_irq() argument
175 irq = irq - _gic_table[index].offset; in arm_gic_clear_pending_irq()
176 RT_ASSERT(irq >= 0U); in arm_gic_clear_pending_irq()
178 if (irq >= 16U) in arm_gic_clear_pending_irq()
180 mask = 1U << (irq % 32U); in arm_gic_clear_pending_irq()
181 GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
185 mask = 1U << ((irq % 4U) * 8U); in arm_gic_clear_pending_irq()
186 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
190 void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config) in arm_gic_set_configuration() argument
197 irq = irq - _gic_table[index].offset; in arm_gic_set_configuration()
198 RT_ASSERT(irq >= 0U); in arm_gic_set_configuration()
200 icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); in arm_gic_set_configuration()
201 shift = (irq % 16U) << 1U; in arm_gic_set_configuration()
206 GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; in arm_gic_set_configuration()
209 rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq) in arm_gic_get_configuration() argument
213 irq = irq - _gic_table[index].offset; in arm_gic_get_configuration()
214 RT_ASSERT(irq >= 0U); in arm_gic_get_configuration()
216 return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); in arm_gic_get_configuration()
219 void arm_gic_clear_active(rt_uint32_t index, int irq) in arm_gic_clear_active() argument
221 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_clear_active()
225 irq = irq - _gic_table[index].offset; in arm_gic_clear_active()
226 RT_ASSERT(irq >= 0U); in arm_gic_clear_active()
228 GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_active()
232 void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) in arm_gic_set_cpu() argument
238 irq = irq - _gic_table[index].offset; in arm_gic_set_cpu()
239 RT_ASSERT(irq >= 0U); in arm_gic_set_cpu()
241 old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); in arm_gic_set_cpu()
243 old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); in arm_gic_set_cpu()
244 old_tgt |= cpumask << ((irq % 4U) * 8U); in arm_gic_set_cpu()
246 GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; in arm_gic_set_cpu()
249 rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq) in arm_gic_get_target_cpu() argument
253 irq = irq - _gic_table[index].offset; in arm_gic_get_target_cpu()
254 RT_ASSERT(irq >= 0U); in arm_gic_get_target_cpu()
256 return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_target_cpu()
259 void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) in arm_gic_set_priority() argument
265 irq = irq - _gic_table[index].offset; in arm_gic_set_priority()
266 RT_ASSERT(irq >= 0U); in arm_gic_set_priority()
268 if (irq < 32U) in arm_gic_set_priority()
273 mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); in arm_gic_set_priority()
274 mask &= ~(0xFFUL << ((irq % 4U) * 8U)); in arm_gic_set_priority()
275 mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); in arm_gic_set_priority()
276 GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; in arm_gic_set_priority()
280 mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); in arm_gic_set_priority()
281 mask &= ~(0xFFUL << ((irq % 4U) * 8U)); in arm_gic_set_priority()
282 mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); in arm_gic_set_priority()
283 GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_set_priority()
287 rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq) in arm_gic_get_priority() argument
291 irq = irq - _gic_table[index].offset; in arm_gic_get_priority()
292 RT_ASSERT(irq >= 0U); in arm_gic_get_priority()
294 if (irq < 32U) in arm_gic_get_priority()
299 …return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U… in arm_gic_get_priority()
303 return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; in arm_gic_get_priority()
362 rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq) in arm_gic_get_irq_status() argument
369 irq = irq - _gic_table[index].offset; in arm_gic_get_irq_status()
370 RT_ASSERT(irq >= 0U); in arm_gic_get_irq_status()
372 active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_irq_status()
373 pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_irq_status()
378 void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routin… in arm_gic_send_affinity_sgi() argument
384 …sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, ex… in arm_gic_send_affinity_sgi()
397 sgi_val = ((irq & 0x0FULL) << 24 | in arm_gic_send_affinity_sgi()
414 rt_uint32_t irq; in arm_gic_get_high_pending_irq() local
418 __get_gicv3_reg(ICC_HPPIR1, irq); in arm_gic_get_high_pending_irq()
419 return irq; in arm_gic_get_high_pending_irq()
429 void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group) in arm_gic_set_group() argument
437 irq = irq - _gic_table[index].offset; in arm_gic_set_group()
438 RT_ASSERT(irq >= 0U); in arm_gic_set_group()
440 igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); in arm_gic_set_group()
441 shift = (irq % 32U); in arm_gic_set_group()
445 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; in arm_gic_set_group()
448 rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq) in arm_gic_get_group() argument
452 irq = irq - _gic_table[index].offset; in arm_gic_get_group()
453 RT_ASSERT(irq >= 0U); in arm_gic_get_group()
455 return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_group()
458 static int arm_gicv3_wait_rwp(rt_uint32_t index, rt_uint32_t irq) in arm_gicv3_wait_rwp() argument
465 if (irq < 32u) in arm_gicv3_wait_rwp()