Lines Matching refs:mask
79 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_mask() local
90 GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; in arm_gic_mask()
94 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
100 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_umask() local
111 GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; in arm_gic_umask()
115 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_umask()
171 rt_uint32_t mask; in arm_gic_clear_pending_irq() local
180 mask = 1U << (irq % 32U); in arm_gic_clear_pending_irq()
181 GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
185 mask = 1U << ((irq % 4U) * 8U); in arm_gic_clear_pending_irq()
186 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
221 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_clear_active() local
228 GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_active()
261 rt_uint32_t mask; in arm_gic_set_priority() local
273 mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); in arm_gic_set_priority()
274 mask &= ~(0xFFUL << ((irq % 4U) * 8U)); in arm_gic_set_priority()
275 mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); in arm_gic_set_priority()
276 GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; in arm_gic_set_priority()
280 mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); in arm_gic_set_priority()
281 mask &= ~(0xFFUL << ((irq % 4U) * 8U)); in arm_gic_set_priority()
282 mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); in arm_gic_set_priority()
283 GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_set_priority()