Lines Matching refs:r0
39 MRS r0, PRIMASK
49 MSR PRIMASK, r0
73 STR r0, [r2]
79 LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
81 STR r1, [r0]
96 LDR r0, =rt_thread_switch_interrupt_flag /* r0 = &rt_thread_switch_interrupt_flag */
97 LDR r1, [r0] /* r1 = *r1 */
108 STR r1, [r0] /* *r0 = r1 */
111 LDR r0, =rt_interrupt_from_thread /* r0 = &rt_interrupt_from_thread */
112 LDR r1, [r0] /* r1 = *r0 */
121 STMFD sp!, {r0-r1, lr} /* push register */
122 MOV r0, r1 /* r0 = rt_secure_current_context */
124 LDMFD sp!, {r0-r1, lr} /* pop register */
138 LDR r0, [r0] /* r0 = rt_thread_switch_interrupt_flag */
139 STR r5, [r0] /* *r0 = r5 */
161 LDR r0, [r0]
162 STR r1, [r0] /* update from thread stack pointer */
176 MOV r0, r2 /* r0 = r2 */
179 CBZ r0, contex_ns_load /* if r0 == 0, goto contex_ns_load */
198 PUSH {r0-r3, r12, lr}
201 POP {r0-r3, r12, lr}
220 STR r0, [r1]
231 MOV r0, #0x0
232 STR r0, [r1]
236 MOV r0, #1
237 STR r0, [r1]
240 LDR r0, =NVIC_SYSPRI2
242 LDR.W r2, [r0,#0x00] /* read */
244 STR r1, [r0] /* write-back */
246 LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
248 STR r1, [r0]
251 LDR r0, =SCB_VTOR
252 LDR r0, [r0]
253 LDR r0, [r0]
255 MSR msp, r0
278 MRS r0, msp /* get fault context from handler. */
281 MRS r0, psp /* get fault context from thread. */
287 VSTMDBEQ r0!, {d8 - d15} /* push FPU register s16~s31 */
290 STMFD r0!, {r4 - r11} /* push r4 - r11 register */
297 STMFD r0!, {r2-r5} /* push to thread stack */
299 STMFD r0!, {lr} /* push exec_return register */
303 MSR psp, r0 /* update stack pointer to PSP. */
306 MSR msp, r0 /* update stack pointer to MSP. */