Lines Matching refs:r0
57 mov r0, #0x0000
89 ldr r0, =stack_top
92 mov sp, r0
96 mov sp, r0
97 sub r0, r0, #UND_Stack_Size
101 mov sp, r0
102 sub r0, r0, #ABT_Stack_Size
106 mov sp, r0
107 sub r0, r0, #FIQ_Stack_Size
111 mov sp, r0
112 sub r0, r0, #IRQ_Stack_Size
135 ldr r0, [r1, #0]
136 str r0, [r3]
145 mov r0,#0 /* get a zero */
151 strlo r0,[r1],#4 /* clear 4 bytes */
155 ldr r0, =__ctors_start__
159 cmp r0, r1
161 ldr r2, [r0], #4
162 stmfd sp!, {r0-r3, ip, lr}
165 ldmfd sp!, {r0-r3, ip, lr}
176 stmfd sp!, {r0}
177 mrc p15, #0x00, r0, c1, c0, #0x01
178 orr r0, r0, #0x0C000000
179 mcr p15, #0x00, r0, c1, c0, #0x01
180 ldmfd sp!, {r0}
189 stmfd sp!, {r0}
190 mrc p15, #0x00, r0, c1, c0, #0x01
191 bic r0, r0, #0x0C000000
192 mcr p15, #0x00, r0, c1, c0, #0x01
193 ldmfd sp!, {r0}
203 stmfd sp!, {r0}
204 mrc p15, #0x00, r0, c1, c0, #0x01
205 orr r0, r0, #0x02000000
207 mcr p15, #0x00, r0, c1, c0, #0x01
208 ldmfd sp!, {r0}
217 stmfd sp!, {r0}
218 mrc p15, #0x00, r0, c1, c0, #0x01
219 bic r0, r0, #0x02000000
220 mcr p15, #0x00, r0, c1, c0, #0x01
221 ldmfd sp!, {r0}
231 mrc p15, #0, r0, c5, c0, #0
242 stmfd sp!, {r0}
243 mov r0, #0
244 mcr p15, #0, r0, c5, c0, #0
245 ldmfd sp!, {r0}
256 mrc p15, #0, r0, c5, c0, #1
267 stmfd sp!, {r0}
268 mov r0, #0
269 mcr p15, #0, r0, c5, c0, #1
270 ldmfd sp!, {r0}
281 mrc p15, #0, r0, c6, c0, #0
292 stmfd sp!, {r0}
293 mov r0, #0
294 mcr p15, #0, r0, c6, c0, #0
295 ldmfd sp!, {r0}
306 mrc p15, #0, r0, c6, c0, #2
317 stmfd sp!, {r0}
318 mov r0, #0
319 mcr p15, #0, r0, c6, c0, #2
320 ldmfd sp!, {r0}
331 mrc p15, #0, r0, c5, c1, #0
342 stmfd sp!, {r0}
343 mov r0, #0
344 mcr p15, #0, r0, c5, c1, #0
345 ldmfd sp!, {r0}
356 mrc p15, #0, r0, c5, c1, #1
366 stmfd sp!, {r0}
367 mov r0, #0
368 mrc p15, #0, r0, c5, c1, #1
369 ldmfd sp!, {r0}
379 stmfd sp!, {r0-r2}
380 ldr r0, ESMSR1_REG @ load the ESMSR1 status register address
382 str r2, [r0] @ clear the ESMSR1 register
384 ldr r0, ESMSR2_REG @ load the ESMSR2 status register address
386 str r2, [r0] @ clear the ESMSR2 register
388 ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address
390 str r2, [r0] @ clear the ESMSSR2 register
392 ldr r0, ESMKEY_REG @ load the ESMKEY register address
394 str r2, [r0] @ clear the ESMKEY register
396 ldr r0, VIM_INTREQ @ load the INTREQ register address
398 str r2, [r0] @ clear the INTREQ register
399 ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address
401 str r2, [r0] @ clear the CCMR4 status register
402 ldmfd sp!, {r0-r2}
432 push {r0}
433 mrc p15, #0, r0, c15, c0, #0 @ Read Secondary Auxiliary Control Register
434 orr r0, r0, #0x10000 @ Set BIT 16 (Set DOOFMACS)
435 mcr p15, #0, r0, c15, c0, #0 @ Write Secondary Auxiliary Control Register
436 pop {r0}
452 push {r0}
453 mrc p15, #0, r0, c1, c0, #1 @ Read Auxiliary Control register
454 orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion
456 mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register
457 pop {r0}
463 STMDB sp!, {r0}
464 fmrx r0, fpexc
465 orr r0, r0, #0x40000000
466 fmxr fpexc, r0
467 LDMIA sp!, {r0}
472 stmia sp, {r0 - r12} @/* Calling r0-r12 */
473 mov r0, sp
475 str lr, [r0, #15*4] @/* Push PC */
476 str r6, [r0, #16*4] @/* Push CPSR */
478 str sp, [r0, #13*4] @/* Save calling SP */
479 str lr, [r0, #14*4] @/* Save calling PC */