Lines Matching refs:r0
55 mov r0, #0x0000
87 ldr r0, =stack_top
90 mov sp, r0
94 mov sp, r0
95 sub r0, r0, #UND_Stack_Size
99 mov sp, r0
100 sub r0, r0, #ABT_Stack_Size
104 mov sp, r0
105 sub r0, r0, #FIQ_Stack_Size
109 mov sp, r0
110 sub r0, r0, #IRQ_Stack_Size
133 ldr r0, [r1, #0]
134 str r0, [r3]
143 mov r0,#0 /* get a zero */
149 strlo r0,[r1],#4 /* clear 4 bytes */
153 ldr r0, =__ctors_start__
157 cmp r0, r1
159 ldr r2, [r0], #4
160 stmfd sp!, {r0-r3, ip, lr}
163 ldmfd sp!, {r0-r3, ip, lr}
174 stmfd sp!, {r0}
175 mrc p15, #0x00, r0, c1, c0, #0x01
176 orr r0, r0, #0x0C000000
177 mcr p15, #0x00, r0, c1, c0, #0x01
178 ldmfd sp!, {r0}
187 stmfd sp!, {r0}
188 mrc p15, #0x00, r0, c1, c0, #0x01
189 bic r0, r0, #0x0C000000
190 mcr p15, #0x00, r0, c1, c0, #0x01
191 ldmfd sp!, {r0}
201 stmfd sp!, {r0}
202 mrc p15, #0x00, r0, c1, c0, #0x01
203 orr r0, r0, #0x02000000
205 mcr p15, #0x00, r0, c1, c0, #0x01
206 ldmfd sp!, {r0}
215 stmfd sp!, {r0}
216 mrc p15, #0x00, r0, c1, c0, #0x01
217 bic r0, r0, #0x02000000
218 mcr p15, #0x00, r0, c1, c0, #0x01
219 ldmfd sp!, {r0}
229 mrc p15, #0, r0, c5, c0, #0
240 stmfd sp!, {r0}
241 mov r0, #0
242 mcr p15, #0, r0, c5, c0, #0
243 ldmfd sp!, {r0}
254 mrc p15, #0, r0, c5, c0, #1
265 stmfd sp!, {r0}
266 mov r0, #0
267 mcr p15, #0, r0, c5, c0, #1
268 ldmfd sp!, {r0}
279 mrc p15, #0, r0, c6, c0, #0
290 stmfd sp!, {r0}
291 mov r0, #0
292 mcr p15, #0, r0, c6, c0, #0
293 ldmfd sp!, {r0}
304 mrc p15, #0, r0, c6, c0, #2
315 stmfd sp!, {r0}
316 mov r0, #0
317 mcr p15, #0, r0, c6, c0, #2
318 ldmfd sp!, {r0}
329 mrc p15, #0, r0, c5, c1, #0
340 stmfd sp!, {r0}
341 mov r0, #0
342 mcr p15, #0, r0, c5, c1, #0
343 ldmfd sp!, {r0}
354 mrc p15, #0, r0, c5, c1, #1
364 stmfd sp!, {r0}
365 mov r0, #0
366 mrc p15, #0, r0, c5, c1, #1
367 ldmfd sp!, {r0}
377 stmfd sp!, {r0-r2}
378 ldr r0, ESMSR1_REG @ load the ESMSR1 status register address
380 str r2, [r0] @ clear the ESMSR1 register
382 ldr r0, ESMSR2_REG @ load the ESMSR2 status register address
384 str r2, [r0] @ clear the ESMSR2 register
386 ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address
388 str r2, [r0] @ clear the ESMSSR2 register
390 ldr r0, ESMKEY_REG @ load the ESMKEY register address
392 str r2, [r0] @ clear the ESMKEY register
394 ldr r0, VIM_INTREQ @ load the INTREQ register address
396 str r2, [r0] @ clear the INTREQ register
397 ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address
399 str r2, [r0] @ clear the CCMR4 status register
400 ldmfd sp!, {r0-r2}
430 push {r0}
431 mrc p15, #0, r0, c15, c0, #0 @ Read Secondary Auxiliary Control Register
432 orr r0, r0, #0x10000 @ Set BIT 16 (Set DOOFMACS)
433 mcr p15, #0, r0, c15, c0, #0 @ Write Secondary Auxiliary Control Register
434 pop {r0}
450 push {r0}
451 mrc p15, #0, r0, c1, c0, #1 @ Read Auxiliary Control register
452 orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion
454 mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register
455 pop {r0}
461 STMDB sp!, {r0}
462 fmrx r0, fpexc
463 orr r0, r0, #0x40000000
464 fmxr fpexc, r0
465 LDMIA sp!, {r0}
470 stmia sp, {r0 - r12} @/* Calling r0-r12 */
471 mov r0, sp
473 str lr, [r0, #15*4] @/* Push PC */
474 str r6, [r0, #16*4] @/* Push CPSR */
476 str sp, [r0, #13*4] @/* Save calling SP */
477 str lr, [r0, #14*4] @/* Save calling PC */