Lines Matching refs:R4
1187 LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N)
1188 AND R3, R3, R4
1189 LDR R4, =PLLCFG_Val
1190 EORS R3, R3, R4
1233 LDR R4, =EMC_PCONP_Const ; Enable EMC
1235 ORR R4, R4, R3
1236 STR R4, [R1, #PCONP_OFS]
1238 LDR R4, =EMC_CTRL_Val
1239 STR R4, [R0, #EMC_CTRL_OFS]
1240 LDR R4, =EMC_CONFIG_Val
1241 STR R4, [R0, #EMC_CONFIG_OFS]
1244 LDR R4, =EMC_PINSEL5_Val
1245 STR R4, [R2, #PINSEL5_OFS]
1246 LDR R4, =EMC_PINSEL6_Val
1247 STR R4, [R2, #PINSEL6_OFS]
1248 LDR R4, =EMC_PINSEL8_Val
1249 STR R4, [R2, #PINSEL8_OFS]
1250 LDR R4, =EMC_PINSEL9_Val
1251 STR R4, [R2, #PINSEL9_OFS]
1256 LDR R4, =EMC_DYN_RP_Val
1257 STR R4, [R0, #EMC_DYN_RP_OFS]
1258 LDR R4, =EMC_DYN_RAS_Val
1259 STR R4, [R0, #EMC_DYN_RAS_OFS]
1260 LDR R4, =EMC_DYN_SREX_Val
1261 STR R4, [R0, #EMC_DYN_SREX_OFS]
1262 LDR R4, =EMC_DYN_APR_Val
1263 STR R4, [R0, #EMC_DYN_APR_OFS]
1264 LDR R4, =EMC_DYN_DAL_Val
1265 STR R4, [R0, #EMC_DYN_DAL_OFS]
1266 LDR R4, =EMC_DYN_WR_Val
1267 STR R4, [R0, #EMC_DYN_WR_OFS]
1268 LDR R4, =EMC_DYN_RC_Val
1269 STR R4, [R0, #EMC_DYN_RC_OFS]
1270 LDR R4, =EMC_DYN_RFC_Val
1271 STR R4, [R0, #EMC_DYN_RFC_OFS]
1272 LDR R4, =EMC_DYN_XSR_Val
1273 STR R4, [R0, #EMC_DYN_XSR_OFS]
1274 LDR R4, =EMC_DYN_RRD_Val
1275 STR R4, [R0, #EMC_DYN_RRD_OFS]
1276 LDR R4, =EMC_DYN_MRD_Val
1277 STR R4, [R0, #EMC_DYN_MRD_OFS]
1279 LDR R4, =EMC_DYN_RD_CFG_Val
1280 STR R4, [R0, #EMC_DYN_RD_CFG_OFS]
1283 LDR R4, =EMC_DYN_RASCAS0_Val
1284 STR R4, [R0, #EMC_DYN_RASCAS0_OFS]
1285 LDR R4, =EMC_DYN_CFG0_Val
1287 AND R4, R4, R5
1288 STR R4, [R0, #EMC_DYN_CFG0_OFS]
1291 LDR R4, =EMC_DYN_RASCAS1_Val
1292 STR R4, [R0, #EMC_DYN_RASCAS1_OFS]
1293 LDR R4, =EMC_DYN_CFG1_Val
1295 AND R4, R4, R5
1296 STR R4, [R0, #EMC_DYN_CFG1_OFS]
1299 LDR R4, =EMC_DYN_RASCAS2_Val
1300 STR R4, [R0, #EMC_DYN_RASCAS2_OFS]
1301 LDR R4, =EMC_DYN_CFG2_Val
1303 AND R4, R4, R5
1304 STR R4, [R0, #EMC_DYN_CFG2_OFS]
1307 LDR R4, =EMC_DYN_RASCAS3_Val
1308 STR R4, [R0, #EMC_DYN_RASCAS3_OFS]
1309 LDR R4, =EMC_DYN_CFG3_Val
1311 AND R4, R4, R5
1312 STR R4, [R0, #EMC_DYN_CFG3_OFS]
1319 LDR R4, =(NOP_CMD:OR:0x03) ; Write NOP Command
1320 STR R4, [R0, #EMC_DYN_CTRL_OFS]
1326 LDR R4, =(PALL_CMD:OR:0x03) ; Write Precharge All Command
1327 STR R4, [R0, #EMC_DYN_CTRL_OFS]
1329 MOV R4, #2
1330 STR R4, [R0, #EMC_DYN_RFSH_OFS]
1336 LDR R4, =EMC_DYN_RFSH_Val
1337 STR R4, [R0, #EMC_DYN_RFSH_OFS]
1339 LDR R4, =(MODE_CMD:OR:0x03) ; Write MODE Command
1340 STR R4, [R0, #EMC_DYN_CTRL_OFS]
1344 LDR R4, =DYN_MEM0_BASE
1346 ADD R4, R4, R5
1347 LDR R4, [R4, #0]
1350 LDR R4, =DYN_MEM1_BASE
1352 ADD R4, R4, R5
1353 LDR R4, [R4, #0]
1356 LDR R4, =DYN_MEM2_BASE
1358 ADD R4, R4, R5
1359 LDR R4, [R4, #0]
1362 LDR R4, =DYN_MEM3_BASE
1364 ADD R4, R4, R5
1365 LDR R4, [R4, #0]
1368 LDR R4, =NORMAL_CMD ; Write NORMAL Command
1369 STR R4, [R0, #EMC_DYN_CTRL_OFS]
1373 LDR R4, =EMC_DYN_CFG0_Val
1374 STR R4, [R0, #EMC_DYN_CFG0_OFS]
1377 LDR R4, =EMC_DYN_CFG1_Val
1378 STR R4, [R0, #EMC_DYN_CFG1_OFS]
1381 LDR R4, =EMC_DYN_CFG2_Val
1382 STR R4, [R0, #EMC_DYN_CFG2_OFS]
1385 LDR R4, =EMC_DYN_CFG3_Val
1386 STR R4, [R0, #EMC_DYN_CFG3_OFS]
1403 LDR R4, =EMC_STA_CFG0_Val
1404 STR R4, [R0, #EMC_STA_CFG0_OFS]
1405 LDR R4, =EMC_STA_WWEN0_Val
1406 STR R4, [R0, #EMC_STA_WWEN0_OFS]
1407 LDR R4, =EMC_STA_WOEN0_Val
1408 STR R4, [R0, #EMC_STA_WOEN0_OFS]
1409 LDR R4, =EMC_STA_WRD0_Val
1410 STR R4, [R0, #EMC_STA_WRD0_OFS]
1411 LDR R4, =EMC_STA_WPAGE0_Val
1412 STR R4, [R0, #EMC_STA_WPAGE0_OFS]
1413 LDR R4, =EMC_STA_WWR0_Val
1414 STR R4, [R0, #EMC_STA_WWR0_OFS]
1415 LDR R4, =EMC_STA_WTURN0_Val
1416 STR R4, [R0, #EMC_STA_WTURN0_OFS]
1420 LDR R4, =EMC_STA_CFG1_Val
1421 STR R4, [R0, #EMC_STA_CFG1_OFS]
1422 LDR R4, =EMC_STA_WWEN1_Val
1423 STR R4, [R0, #EMC_STA_WWEN1_OFS]
1424 LDR R4, =EMC_STA_WOEN1_Val
1425 STR R4, [R0, #EMC_STA_WOEN1_OFS]
1426 LDR R4, =EMC_STA_WRD1_Val
1427 STR R4, [R0, #EMC_STA_WRD1_OFS]
1428 LDR R4, =EMC_STA_WPAGE1_Val
1429 STR R4, [R0, #EMC_STA_WPAGE1_OFS]
1430 LDR R4, =EMC_STA_WWR1_Val
1431 STR R4, [R0, #EMC_STA_WWR1_OFS]
1432 LDR R4, =EMC_STA_WTURN1_Val
1433 STR R4, [R0, #EMC_STA_WTURN1_OFS]
1437 LDR R4, =EMC_STA_CFG2_Val
1438 STR R4, [R0, #EMC_STA_CFG2_OFS]
1439 LDR R4, =EMC_STA_WWEN2_Val
1440 STR R4, [R0, #EMC_STA_WWEN2_OFS]
1441 LDR R4, =EMC_STA_WOEN2_Val
1442 STR R4, [R0, #EMC_STA_WOEN2_OFS]
1443 LDR R4, =EMC_STA_WRD2_Val
1444 STR R4, [R0, #EMC_STA_WRD2_OFS]
1445 LDR R4, =EMC_STA_WPAGE2_Val
1446 STR R4, [R0, #EMC_STA_WPAGE2_OFS]
1447 LDR R4, =EMC_STA_WWR2_Val
1448 STR R4, [R0, #EMC_STA_WWR2_OFS]
1449 LDR R4, =EMC_STA_WTURN2_Val
1450 STR R4, [R0, #EMC_STA_WTURN2_OFS]
1454 LDR R4, =EMC_STA_CFG3_Val
1455 STR R4, [R0, #EMC_STA_CFG3_OFS]
1456 LDR R4, =EMC_STA_WWEN3_Val
1457 STR R4, [R0, #EMC_STA_WWEN3_OFS]
1458 LDR R4, =EMC_STA_WOEN3_Val
1459 STR R4, [R0, #EMC_STA_WOEN3_OFS]
1460 LDR R4, =EMC_STA_WRD3_Val
1461 STR R4, [R0, #EMC_STA_WRD3_OFS]
1462 LDR R4, =EMC_STA_WPAGE3_Val
1463 STR R4, [R0, #EMC_STA_WPAGE3_OFS]
1464 LDR R4, =EMC_STA_WWR3_Val
1465 STR R4, [R0, #EMC_STA_WWR3_OFS]
1466 LDR R4, =EMC_STA_WTURN3_Val
1467 STR R4, [R0, #EMC_STA_WTURN3_OFS]
1474 LDR R4, =EMC_STA_EXT_W_Val
1477 STR R4, [R5, #0]