Lines Matching refs:CtrlReg
68 register u32 CtrlReg; in Xil_DCacheEnable() local
72 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DCacheEnable()
74 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_DCacheEnable()
76 if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) == 0x00000000U) in Xil_DCacheEnable()
82 CtrlReg |= (XREG_CP15_CONTROL_C_BIT); in Xil_DCacheEnable()
84 mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_DCacheEnable()
90 register u32 CtrlReg; in Xil_DCacheDisable() local
97 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DCacheDisable()
99 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_DCacheDisable()
102 CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); in Xil_DCacheDisable()
104 mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_DCacheDisable()
307 register u32 CtrlReg; in Xil_ICacheEnable() local
311 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_ICacheEnable()
313 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_ICacheEnable()
315 if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) == 0x00000000U) in Xil_ICacheEnable()
321 CtrlReg |= (XREG_CP15_CONTROL_I_BIT); in Xil_ICacheEnable()
323 mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_ICacheEnable()
329 register u32 CtrlReg; in Xil_ICacheDisable() local
338 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_ICacheDisable()
340 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_ICacheDisable()
343 CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT); in Xil_ICacheDisable()
345 mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_ICacheDisable()
431 register u32 CtrlReg; in rt_hw_cpu_icache_status() local
433 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in rt_hw_cpu_icache_status()
435 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in rt_hw_cpu_icache_status()
437 return CtrlReg & XREG_CP15_CONTROL_I_BIT; in rt_hw_cpu_icache_status()
442 register u32 CtrlReg; in rt_hw_cpu_dcache_status() local
444 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in rt_hw_cpu_dcache_status()
446 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in rt_hw_cpu_dcache_status()
448 return CtrlReg & XREG_CP15_CONTROL_C_BIT; in rt_hw_cpu_dcache_status()