Lines Matching refs:size
32 void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) in r4k_icache_flush_range() argument
36 if (size > g_mips_core.icache_size) in r4k_icache_flush_range()
45 end = ((addr + size) - 1) & ~(ic_lsize - 1); in r4k_icache_flush_range()
56 void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) in r4k_icache_lock_range() argument
62 end = ((addr + size) - 1) & ~(ic_lsize - 1); in r4k_icache_lock_range()
72 void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) in r4k_dcache_inv() argument
78 end = ((addr + size) - 1) & ~(dc_lsize - 1); in r4k_dcache_inv()
88 void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) in r4k_dcache_wback_inv() argument
92 if (size >= g_mips_core.dcache_size) in r4k_dcache_wback_inv()
101 end = ((addr + size) - 1) & ~(dc_lsize - 1); in r4k_dcache_wback_inv()
112 #define dma_cache_wback_inv(start,size) \ argument
113 do { (void) (start); (void) (size); } while (0)
114 #define dma_cache_wback(start,size) \ argument
115 do { (void) (start); (void) (size); } while (0)
116 #define dma_cache_inv(start,size) \ argument
117 do { (void) (start); (void) (size); } while (0)
120 void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction) in r4k_dma_cache_sync() argument
125 r4k_dcache_wback_inv(addr, size); in r4k_dma_cache_sync()
129 r4k_dcache_wback_inv(addr, size); in r4k_dma_cache_sync()
133 dma_cache_wback_inv(addr, size); in r4k_dma_cache_sync()