Lines Matching refs:addr
105 #define cache_op(op, addr) \ argument
113 : "i" (op), "R" (*(unsigned char *)(addr)))
142 static inline void flush_icache_line_indexed(rt_ubase_t addr) in flush_icache_line_indexed() argument
144 cache_op(INDEX_INVALIDATE_I, addr); in flush_icache_line_indexed()
147 static inline void flush_dcache_line_indexed(rt_ubase_t addr) in flush_dcache_line_indexed() argument
149 cache_op(INDEX_WRITEBACK_INV_D, addr); in flush_dcache_line_indexed()
152 static inline void flush_icache_line(rt_ubase_t addr) in flush_icache_line() argument
154 cache_op(HIT_INVALIDATE_I, addr); in flush_icache_line()
157 static inline void lock_icache_line(rt_ubase_t addr) in lock_icache_line() argument
159 cache_op(FETCH_AND_LOCK_I, addr); in lock_icache_line()
162 static inline void lock_dcache_line(rt_ubase_t addr) in lock_dcache_line() argument
164 cache_op(FETCH_AND_LOCK_D, addr); in lock_dcache_line()
167 static inline void flush_dcache_line(rt_ubase_t addr) in flush_dcache_line() argument
169 cache_op(HIT_WRITEBACK_INV_D, addr); in flush_dcache_line()
172 static inline void invalidate_dcache_line(rt_ubase_t addr) in invalidate_dcache_line() argument
174 cache_op(HIT_INVALIDATE_D, addr); in invalidate_dcache_line()
180 rt_ubase_t addr; in blast_dcache16() local
182 for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) in blast_dcache16()
183 cache16_unroll32(addr, INDEX_WRITEBACK_INV_D); in blast_dcache16()
190 rt_ubase_t addr; in inv_dcache16() local
192 for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) in inv_dcache16()
193 cache16_unroll32(addr, HIT_INVALIDATE_D); in inv_dcache16()
200 rt_ubase_t addr; in blast_icache16() local
202 for (addr = start; addr < end; addr += g_mips_core.icache_line_size) in blast_icache16()
203 cache16_unroll32(addr, INDEX_INVALIDATE_I); in blast_icache16()
209 void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size);
210 void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size);
211 void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size);
212 void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size);
213 void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction);