Lines Matching refs:_ULCAST_
154 #define _ULCAST_ macro
156 #define _ULCAST_ (unsigned long) macro
237 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
238 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
239 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
240 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
241 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
242 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
243 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
244 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
245 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
246 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
252 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
254 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
256 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
258 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
260 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
262 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
264 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
266 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
268 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
274 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
280 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
283 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
289 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
291 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
293 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
295 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
297 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
299 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
301 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
303 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
309 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
311 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
312 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
375 #define IE_SW0 (_ULCAST_(1) << 8)
376 #define IE_SW1 (_ULCAST_(1) << 9)
377 #define IE_IRQ0 (_ULCAST_(1) << 10)
378 #define IE_IRQ1 (_ULCAST_(1) << 11)
379 #define IE_IRQ2 (_ULCAST_(1) << 12)
380 #define IE_IRQ3 (_ULCAST_(1) << 13)
381 #define IE_IRQ4 (_ULCAST_(1) << 14)
382 #define IE_IRQ5 (_ULCAST_(1) << 15)
387 #define C_SW0 (_ULCAST_(1) << 8)
388 #define C_SW1 (_ULCAST_(1) << 9)
389 #define C_IRQ0 (_ULCAST_(1) << 10)
390 #define C_IRQ1 (_ULCAST_(1) << 11)
391 #define C_IRQ2 (_ULCAST_(1) << 12)
392 #define C_IRQ3 (_ULCAST_(1) << 13)
393 #define C_IRQ4 (_ULCAST_(1) << 14)
394 #define C_IRQ5 (_ULCAST_(1) << 15)
429 #define ST0_UM (_ULCAST_(1) << 4)
430 #define ST0_IL (_ULCAST_(1) << 23)
431 #define ST0_DL (_ULCAST_(1) << 24)
439 #define STATUSF_IP0 (_ULCAST_(1) << 8)
441 #define STATUSF_IP1 (_ULCAST_(1) << 9)
443 #define STATUSF_IP2 (_ULCAST_(1) << 10)
445 #define STATUSF_IP3 (_ULCAST_(1) << 11)
447 #define STATUSF_IP4 (_ULCAST_(1) << 12)
449 #define STATUSF_IP5 (_ULCAST_(1) << 13)
451 #define STATUSF_IP6 (_ULCAST_(1) << 14)
453 #define STATUSF_IP7 (_ULCAST_(1) << 15)
455 #define STATUSF_IP8 (_ULCAST_(1) << 0)
457 #define STATUSF_IP9 (_ULCAST_(1) << 1)
459 #define STATUSF_IP10 (_ULCAST_(1) << 2)
461 #define STATUSF_IP11 (_ULCAST_(1) << 3)
463 #define STATUSF_IP12 (_ULCAST_(1) << 4)
465 #define STATUSF_IP13 (_ULCAST_(1) << 5)
467 #define STATUSF_IP14 (_ULCAST_(1) << 6)
469 #define STATUSF_IP15 (_ULCAST_(1) << 7)
490 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
492 #define CAUSEF_IP (_ULCAST_(255) << 8)
494 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
496 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
498 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
500 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
502 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
504 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
506 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
508 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
510 #define CAUSEF_IV (_ULCAST_(1) << 23)
512 #define CAUSEF_CE (_ULCAST_(3) << 28)
514 #define CAUSEF_BD (_ULCAST_(1) << 31)
529 #define CONF_BE (_ULCAST_(1) << 15)
532 #define CONF_CU (_ULCAST_(1) << 3)
533 #define CONF_DB (_ULCAST_(1) << 4)
534 #define CONF_IB (_ULCAST_(1) << 5)
535 #define CONF_DC (_ULCAST_(7) << 6)
536 #define CONF_IC (_ULCAST_(7) << 9)
537 #define CONF_EB (_ULCAST_(1) << 13)
538 #define CONF_EM (_ULCAST_(1) << 14)
539 #define CONF_SM (_ULCAST_(1) << 16)
540 #define CONF_SC (_ULCAST_(1) << 17)
541 #define CONF_EW (_ULCAST_(3) << 18)
542 #define CONF_EP (_ULCAST_(15)<< 24)
543 #define CONF_EC (_ULCAST_(7) << 28)
544 #define CONF_CM (_ULCAST_(1) << 31)
547 #define R4K_CONF_SW (_ULCAST_(1) << 20)
548 #define R4K_CONF_SS (_ULCAST_(1) << 21)
549 #define R4K_CONF_SB (_ULCAST_(3) << 22)
552 #define R5K_CONF_SE (_ULCAST_(1) << 12)
553 #define R5K_CONF_SS (_ULCAST_(3) << 20)
556 #define R10K_CONF_DN (_ULCAST_(3) << 3)
557 #define R10K_CONF_CT (_ULCAST_(1) << 5)
558 #define R10K_CONF_PE (_ULCAST_(1) << 6)
559 #define R10K_CONF_PM (_ULCAST_(3) << 7)
560 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
561 #define R10K_CONF_SB (_ULCAST_(1) << 13)
562 #define R10K_CONF_SK (_ULCAST_(1) << 14)
563 #define R10K_CONF_SS (_ULCAST_(7) << 16)
564 #define R10K_CONF_SC (_ULCAST_(7) << 19)
565 #define R10K_CONF_DC (_ULCAST_(7) << 26)
566 #define R10K_CONF_IC (_ULCAST_(7) << 29)
569 #define VR41_CONF_CS (_ULCAST_(1) << 12)
570 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
571 #define VR41_CONF_AD (_ULCAST_(1) << 23)
574 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
575 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
576 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
577 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
578 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
579 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
580 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
581 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
582 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
585 #define TX49_CONF_DC (_ULCAST_(1) << 16)
586 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
587 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
588 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
591 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
592 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
593 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
594 #define MIPS_CONF_M (_ULCAST_(1) << 31)