Lines Matching refs:out_8
71 out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01); in rt_serial_open()
73 out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1); in rt_serial_open()
189 out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r'); in rt_serial_write()
193 out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); in rt_serial_write()
204 out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); in rt_serial_write()
219 out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */ in rt_serial_set_baudrate()
220 out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ in rt_serial_set_baudrate()
263 out_8((rt_uint8_t *)device->hw_base + UART_LSR, in rt_serial_isr()
297 out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */ in rt_hw_serial_init()
300 out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ in rt_hw_serial_init()
301 out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */ in rt_hw_serial_init()
302 out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */ in rt_hw_serial_init()
305 out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */ in rt_hw_serial_init()
306 out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */ in rt_hw_serial_init()