Lines Matching refs:r3
29 MFS r3, RMSR
30 ANDNI r4, r3, IE_BIT
69 MFS r3, RMSR /* save the MSR */
70 SWI r3, r1, STACK_RMSR
74 LWI r3, r1, STACK_RMSR
75 ANDI r3, r3, IE_BIT
76 …BNEI r3, rt_hw_context_switch_ie /*if IE bit set,should be use RTID (return from interrupt). */
78 LWI r3, r1, STACK_RMSR
79 MTS RMSR,r3
87 LWI r3, r1, STACK_RMSR
88 ANDNI r3, r3, IE_BIT /* clear IE bit, prevent interrupt occur immediately*/
89 MTS RMSR,r3
90 LWI r3, r1, STACK_R03
106 LWI r3, r1, STACK_RMSR
107 ANDNI r3, r3, IE_BIT /* clear IE bit, prevent interrupt occur immediately*/
108 MTS RMSR,r3
124 LA r3, r0, rt_thread_switch_interrupt_flag
125 LWI r4, r3, 0 /* load rt_thread_switch_interrupt_flag into r4 */
131 SWI r4, r3, 0
133 LA r3, r0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
134 SWI r5, r3, 0 /* rt_interrupt_from_thread = from */
136 LA r3, r0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
137 SWI r6, r3, 0 /* rt_interrupt_to_thread = to */
151 MFS r3, RMSR
152 ORI r3, r3, IE_BIT
153 SWI r3, r1, STACK_RMSR /* push MSR */
168 LA r3, r0, rt_thread_switch_interrupt_flag
169 LWI r4, r3, 0
174 LWI r3, r1, STACK_RMSR
175 ANDNI r3, r3, IE_BIT
176 MTS RMSR,r3
187 SWI r0, r3, 0 /* clear rt_thread_switch_interrupt_flag */
189 LA r3, r0, rt_interrupt_from_thread
190 LW r4, r0, r3
193 LA r3, r0, rt_interrupt_to_thread
194 LW r4, r0, r3
197 LWI r3, r1, STACK_RMSR
198 ANDI r3, r3, IE_BIT
199 BNEI r3, return_with_ie /*if IE bit set,should be use RTID (return from interrupt). */
201 LWI r3, r1, STACK_RMSR
202 MTS RMSR,r3
210 LWI r3, r1, STACK_RMSR
211 ANDNI r3, r3, IE_BIT /* clear IE bit, prevent interrupt occur immediately*/
212 MTS RMSR,r3
213 LWI r3, r1, STACK_R03