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#ifndef __SPI_SUN8IW20_H__
#define __SPI_SUN8IW20_H__

#define SUNXI_SPI0_PBASE         (0x04025000ul) /* 4K */
#define SUNXI_SPI1_PBASE         (0x04026000ul) /* 4K */
#define SUNXI_IRQ_SPI0                 31
#define SUNXI_IRQ_SPI1                 32

#define SPI_MAX_NUM 2
#define SPI0_PARAMS \
{.reg_base = SUNXI_SPI0_PBASE, .irq_num = SUNXI_IRQ_SPI0, .gpio_num = 6, \
    .gpio_clk = GPIOC(2), .gpio_mosi = GPIOC(4), .gpio_miso = GPIOC(5), \
    .gpio_cs0 = GPIOC(3), .gpio_wp = GPIOC(6), .gpio_hold = GPIOC(7), \
    .mux = 2, .driv_level = GPIO_DRIVING_LEVEL2}
#define SPI1_PARAMS \
{.reg_base = SUNXI_SPI1_PBASE, .irq_num = SUNXI_IRQ_SPI1, .gpio_num = 4, \
    .gpio_clk = GPIOD(11), .gpio_mosi = GPIOD(12), .gpio_miso = GPIOD(13), \
    .gpio_cs0 = GPIOD(10), .gpio_wp = 0, .gpio_hold = 0, \
    .mux = 4, .driv_level = GPIO_DRIVING_LEVEL2}


#define CLK_SPI2 0//RESEVER
#define CLK_BUS_SPI2 0//RESEVER
#define RST_BUS_SPI2 0//RESEVER
#define SUNXI_CLK_SPI(x)    CLK_SPI##x
#define SUNXI_CLK_RST_SPI(x)    RST_BUS_SPI##x
#define SUNXI_CLK_BUS_SPI(x)    CLK_BUS_SPI##x
#define SUNXI_CLK_PLL_SPI CLK_PLL_PERIPH0

#endif /*__SPI_SUN8IW20_H__  */