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#ifndef __TWI_SUN8IW19_H__
#define __TWI_SUN8IW19_H__

/** the base address of TWI*/
#define SUNXI_TWI0_PBASE 0x05002000
#define SUNXI_TWI1_PBASE 0x05002400
#define SUNXI_TWI2_PBASE 0x05002800
#define SUNXI_TWI3_PBASE 0x05002c00
#define SUNXI_S_TWI0_PBASE 0x07081400

/** the irq of each TWI **/
#define SUNXI_GIC_START 32
#define SUNXI_IRQ_TWI0 (SUNXI_GIC_START + 41)
#define SUNXI_IRQ_TWI1 (SUNXI_GIC_START + 42)
#define SUNXI_IRQ_TWI2 (SUNXI_GIC_START + 43)
#define SUNXI_IRQ_TWI3 (SUNXI_GIC_START + 44)
#define SUNXI_IRQ_S_TWI0 (SUNXI_GIC_START + 107)

#define TWI0_PIN_MUXSEL 5
#define TWI1_PIN_MUXSEL 5
#define TWI2_PIN_MUXSEL 4
#define TWI3_PIN_MUXSEL 5
#define S_TWI0_PIN_MUXSEL 3
#define TWI_DISABLE_PIN_MUXSEL 7
#define TWI_PULL_STATE 1
#define TWI_DRIVE_STATE 0

#define TWI0_SCK GPIOI(3)
#define TWI0_SDA GPIOI(4)
#define TWI1_SCK GPIOI(1)
#define TWI1_SDA GPIOI(2)
#define TWI2_SCK GPIOH(5)
#define TWI2_SDA GPIOH(6)
#define TWI3_SCK GPIOH(13)
#define TWI3_SDA GPIOH(14)
#define S_TWI0_SCK GPIOL(0)
#define S_TWI0_SDA GPIOI(1)

#endif /*__TWI_SUN8IW19_H__  */