1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef HPM_SOC_FEATURE_H
9 #define HPM_SOC_FEATURE_H
10 
11 #include "hpm_soc.h"
12 
13 /*
14  * I2C Section
15  */
16 #define I2C_SOC_FIFO_SIZE (4U)
17 #define I2C_SOC_TRANSFER_COUNT_MAX (256U)
18 
19 /*
20  * PMIC Section
21  */
22 #define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U)
23 #define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U)
24 #define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125)
25 #define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U)
26 #define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U)
27 #define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U)
28 
29 /*
30  * I2S Section
31  */
32 #define I2S_SOC_MAX_CHANNEL_NUM (16U)
33 #define I2S_SOC_MAX_TX_CHANNEL_NUM (8U)
34 #define I2S_SOC_MAX_TX_FIFO_DEPTH (8U)
35 #define PDM_I2S HPM_I2S0
36 #define DAO_I2S HPM_I2S1
37 #define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U)
38 #define VAD_SOC_SAMPLE_RATE_IN_HZ (16000U)
39 #define DAO_SOC_SAMPLE_RATE_IN_HZ (48000U)
40 #define DAO_SOC_PDM_SAMPLE_RATE_RATIO (3U)
41 #define DAO_SOC_VAD_SAMPLE_RATE_RATIO (3U)
42 
43 /*
44  * PLLCTL Section
45  */
46 #define PLLCTL_SOC_PLL_MAX_COUNT (5U)
47 /* PLL reference clock in hz */
48 #define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL)
49 /* only PLL1 and PLL2 have DIV0, DIV1 */
50 #define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0)
51 #define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0)
52 
53 
54 /*
55  * PWM Section
56  */
57 #define PWM_SOC_PWM_MAX_COUNT (8U)
58 #define PWM_SOC_CMP_MAX_COUNT (24U)
59 #define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U)
60 
61 /*
62  * DMA Section
63  */
64 #define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD)
65 #define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T)
66 #define DMA_SOC_CHANNEL_NUM (8U)
67 #define DMA_SOC_MAX_COUNT (2U)
68 #define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n))
69 
70 /*
71  * PDMA Section
72  */
73 #define PDMA_SOC_PS_MAX_COUNT (2U)
74 #define PDMA_SOC_SUPPORT_BS16 (1U)
75 /*
76  * LCDC Section
77  */
78 #define LCDC_SOC_MAX_LAYER_COUNT         (8U)
79 #define LCDC_SOC_MAX_CSC_LAYER_COUNT     (2U)
80 #define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2)
81 #define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2)
82 
83 /*
84  * USB Section
85  */
86 #define USB_SOC_MAX_COUNT                          (2U)
87 
88 #define USB_SOC_DCD_QTD_NEXT_INVALID               (1U)
89 #define USB_SOC_DCD_QHD_BUFFER_COUNT               (5U)
90 #define USB_SOC_DCD_MAX_ENDPOINT_COUNT             (8U)
91 #ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT
92 #define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT        (8U)
93 #endif
94 #define USB_SOC_DCD_MAX_QTD_COUNT                  (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT)
95 #define USB_SOS_DCD_MAX_QHD_COUNT                  (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U)
96 #define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT     (2048U)
97 
98 #define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS         (1024U)
99 
100 /*
101  * ENET Section
102  */
103 #define ENET_SOC_RGMII_EN                          (1U)
104 #define ENET_SOC_DESC_ADDR_ALIGNMENT               (32U)
105 #define ENET_SOC_BUFF_ADDR_ALIGNMENT               (4U)
106 #define ENET_SOC_ADDR_MAX_COUNT                    (5U)
107 #define ENET_SOC_ALT_EHD_DES_MIN_LEN               (4U)
108 #define ENET_SOC_ALT_EHD_DES_MAX_LEN               (8U)
109 #define ENET_SOC_ALT_EHD_DES_LEN                   (8U)
110 #define ENET_SOC_PPS_MAX_COUNT                     (4L)
111 #define ENET_SOC_PPS1_EN                           (0U)
112 
113 /*
114  * ACMP Section
115  */
116 #define ACMP_SOC_BANDGAP                           (1U)
117 
118 /*
119  * ADC Section
120  */
121 #define ADC_SOC_IP_VERSION                         (0U)
122 #define ADC_SOC_SEQ_MAX_LEN                        (16U)
123 #define ADC_SOC_MAX_TRIG_CH_LEN                    (4U)
124 #define ADC_SOC_MAX_TRIG_CH_NUM                    (11U)
125 #define ADC_SOC_DMA_ADDR_ALIGNMENT                 (4U)
126 #define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE         (8U)
127 #define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT        (0U)
128 #define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES     (4096U)
129 #define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES     (48U)
130 #define ADC_SOC_OTP_TSNS_REF25_MASK                (0xffffUL)
131 #define ADC_SOC_OTP_TSNS_REF25_SHIFT               (21U)
132 #define ADC_SOC_REF_TEMP                           (25U)
133 #define ADC_SOC_REF_SLOPE                          (1.0f/6)
134 #define ADC_SOC_TEMPSENS_REF25_VOL                 (3300U)
135 #define ADC_SOC_VOUT25C_MAX_SAMPLE_VALUE           (65535U)
136 
137 #define ADC12_SOC_CLOCK_CLK_DIV                    (2U)
138 #define ADC12_SOC_CALIBRATION_WAITING_LOOP_CNT     (10)
139 #define ADC12_SOC_MAX_CH_NUM                       (17U)
140 #define ADC12_SOC_MAX_SAMPLE_VALUE                 (4095U)
141 
142 #define ADC16_SOC_PARAMS_LEN                       (34U)
143 #define ADC16_SOC_MAX_CH_NUM                       (7U)
144 #define ADC16_SOC_TEMP_CH_NUM                      (14U)
145 #define ADC16_SOC_TEMP_CH_EN                       (1U)
146 #define ADC16_SOC_MAX_SAMPLE_VALUE                 (65535U)
147 #define ADC16_SOC_MAX_CONV_CLK_NUM                 (21U)
148 
149 /*
150  * SYSCTL Section
151  */
152 #define SYSCTL_SOC_CPU_GPR_COUNT (14U)
153 #define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U)
154 
155 /*
156  * PTPC Section
157  */
158 #define PTPC_SOC_TIMER_MAX_COUNT       (2U)
159 
160 /*
161  * CAN Section
162  */
163 #define CAN_SOC_MAX_COUNT       (4U)
164 #define CAN_SOC_CANFD_TDC_REQUIRE_STUFF_EXCEPTION_WORKAROUND (1)    /* Refer to E00016 in HPM6700/6400 Errata */
165 
166 /*
167  * UART Section
168  */
169 #define UART_SOC_FIFO_SIZE       (16U)
170 
171 /*
172  * SPI Section
173  */
174 #define SPI_SOC_TRANSFER_COUNT_MAX  (512U)
175 #define SPI_SOC_FIFO_DEPTH          (4U)
176 
177 /*
178  * SDXC Section
179  */
180 #define SDXC_SOC_MAX_COUNT      (2)
181 
182 
183 /*
184  * ROM API section
185  */
186 #define ROMAPI_HAS_SW_SM3 (1)
187 #define ROMAPI_HAS_SW_SM4 (1)
188 
189 /*
190  * OTP Section
191  */
192 #define OTP_SOC_MAC0_IDX   (65U)
193 #define OTP_SOC_MAC0_LEN   (6U)  /* in bytes */
194 
195 #define OTP_SOC_UUID_IDX   (88U)
196 #define OTP_SOC_UUID_LEN   (16U) /* in bytes */
197 
198 /**
199  * PWM Section
200  *
201  */
202 #define PWM_SOC_HRPWM_SUPPORT  (0U)
203 #define PWM_SOC_SHADOW_TRIG_SUPPORT (0U)
204 #define PWM_SOC_TIMER_RESET_SUPPORT (0U)
205 
206 /**
207  * IOC Section
208  *
209  */
210 #define IOC_SOC_PAD_CTRL_SETTING_WORKAROUND (1U)    /* Refer to E00029 in HPM6700/HPM6400 Errata */
211 
212 #endif /* HPM_SOC_FEATURE_H */
213