1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_adc.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_ADC_H 22 #define __REG_ADC_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 //////////////////////////////////////////////////////////////////////////////// 43 /// @brief ADC Base Address Definition 44 //////////////////////////////////////////////////////////////////////////////// 45 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) ///< Base Address: 0x40012400 46 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) ///< Base Address: 0x40012800 47 #define ADC3_BASE (APB2PERIPH_BASE + 0x4C00) ///< Base Address: 0x40014C00 48 49 50 51 52 53 //////////////////////////////////////////////////////////////////////////////// 54 /// @brief Analog-to-Digital Converter register 55 //////////////////////////////////////////////////////////////////////////////// 56 #define USENCOMBINEREGISTER 57 #ifdef USENCOMBINEREGISTER 58 59 typedef struct { 60 union { 61 __IO u32 DR; ///< ADC data register, offset: 0x00 62 __IO u32 ADDATA; 63 }; 64 union { 65 __IO u32 CFGR; ///< ADC configuration register, offset: 0x04 66 __IO u32 ADCFG; 67 }; 68 union { 69 __IO u32 CR; ///< ADC control register, offset: 0x08 70 __IO u32 ADCR; 71 }; 72 union { 73 __IO u32 CHSR; ///< ADC channel selection register, offset: 0x0C 74 __IO u32 ADCHS; 75 }; 76 union { 77 __IO u32 CMPR; ///< ADC window compare register, offset: 0x10 78 __IO u32 ADCMPR; 79 }; 80 union { 81 __IO u32 SR; ///< ADC status register, offset: 0x14 82 __IO u32 ADSTA; 83 }; 84 union { 85 __IO u32 CH0DR; ///< ADC channel0 data register, offset: 0x18 86 __IO u32 ADDR0; 87 }; 88 union { 89 __IO u32 CH1DR; ///< ADC channel1 data register, offset: 0x1C 90 __IO u32 ADDR1; 91 }; 92 union { 93 __IO u32 CH2DR; ///< ADC channel2 data register, offset: 0x20 94 __IO u32 ADDR2; 95 }; 96 union { 97 __IO u32 CH3DR; ///< ADC channel3 data register, offset: 0x24 98 __IO u32 ADDR3; 99 }; 100 union { 101 __IO u32 CH4DR; ///< ADC channel4 data register, offset: 0x28 102 __IO u32 ADDR4; 103 }; 104 union { 105 __IO u32 CH5DR; ///< ADC channel5 data register, offset: 0x2C 106 __IO u32 ADDR5; 107 }; 108 union { 109 __IO u32 CH6DR; ///< ADC channel6 data register, offset: 0x30 110 __IO u32 ADDR6; 111 }; 112 union { 113 __IO u32 CH7DR; ///< ADC channel7 data register, offset: 0x34 114 __IO u32 ADDR7; 115 }; 116 union { 117 __IO u32 CH8DR; ///< ADC channel8 data register, offset: 0x38 118 __IO u32 ADDR8; 119 }; 120 union { 121 __IO u32 CH9DR; ///< ADC channel9 data register, offset: 0x3C 122 __IO u32 ADDR9; 123 }; 124 __IO u32 ADDR10; ///< offset: 0x40 125 __IO u32 ADDR11; ///< offset: 0x44 126 __IO u32 ADDR12; ///< offset: 0x48 127 __IO u32 ADDR13; ///< offset: 0x4C 128 union { 129 __IO u32 CH14DR; ///< ADC channel14 data register, offset: 0x50 130 __IO u32 ADDR14; 131 }; 132 union { 133 __IO u32 CH15DR; ///< ADC channel15 data register, offset: 0x54 134 __IO u32 ADDR15; 135 }; 136 __IO u32 SREXT; ///< ADC Extended Status Register, offset: 0x58 137 __IO u32 CHANY0; ///< ADC any Chan Select Register 0, offset: 0x5C 138 __IO u32 CHANY1; ///< ADC any Chan Select Register 1, offset: 0x60 139 __IO u32 ANYCFG; ///< ADC any Chan config Register, offset: 0x64 140 __IO u32 ANYCR; ///< ADC any Chan control Register, offset: 0x68 141 __IO u32 RESERVED0; ///< offset 0x6C 142 __IO u32 SMPR1; ///< Sampling configuration register 1 offset 0x70 143 __IO u32 SMPR2; ///< Sampling configuration register 2 offset 0x74 144 __IO u32 RESERVED1; ///< offset 0x78 145 __IO u32 JOFR0; ///< Injection channel data compensation register 0 offset 0x7C 146 __IO u32 JOFR1; ///< Injection channel data compensation register 1 offset 0x80 147 __IO u32 JOFR2; ///< Injection channel data compensation register 2 offset 0x84 148 __IO u32 JOFR3; ///< Injection channel data compensation register 3 offset 0x88 149 __IO u32 JSQR; ///< Injection sequence register offset 0x8C 150 __IO u32 JDATA; ///< Inject data register offset 0x90 151 __IO u32 RESERVED2; ///< offset 0x94 152 __IO u32 RESERVED3; ///< offset 0x98 153 __IO u32 RESERVED4; ///< offset 0x9C 154 __IO u32 RESERVED5; ///< offset 0xA0 155 __IO u32 RESERVED6; ///< offset 0xA4 156 __IO u32 RESERVED7; ///< offset 0xA8 157 __IO u32 RESERVED8; ///< offset 0xAC 158 __IO u32 JDR0; ///< Injection channel data register 0 offset 0xB0 159 __IO u32 JDR1; ///< Injection channel data register 1 offset 0xB4 160 __IO u32 JDR2; ///< Injection channel data register 2 offset 0xB8 161 __IO u32 JDR3; ///< Injection channel data register 3 offset 0xBC 162 } ADC_TypeDef; 163 164 #endif 165 #ifdef USENNEWREGISTER 166 //////////////////////////////////////////////////////////////////////////////// 167 /// @brief Analog-to-Digital Converter register 168 //////////////////////////////////////////////////////////////////////////////// 169 typedef struct { 170 __IO u32 DR; ///< ADC data register, offset: 0x00 171 __IO u32 CFGR; ///< ADC configuration register, offset: 0x04 172 __IO u32 CR; ///< ADC control register, offset: 0x08 173 __IO u32 CHSR; ///< ADC channel selection register, offset: 0x0C 174 __IO u32 CMPR; ///< ADC window compare register, offset: 0x10 175 __IO u32 SR; ///< ADC status register, offset: 0x14 176 __IO u32 CH0DR; ///< ADC channel0 data register, offset: 0x18 177 __IO u32 CH1DR; ///< ADC channel1 data register, offset: 0x1C 178 __IO u32 CH2DR; ///< ADC channel2 data register, offset: 0x20 179 __IO u32 CH3DR; ///< ADC channel3 data register, offset: 0x24 180 __IO u32 CH4DR; ///< ADC channel4 data register, offset: 0x28 181 __IO u32 CH5DR; ///< ADC channel5 data register, offset: 0x2C 182 __IO u32 CH6DR; ///< ADC channel6 data register, offset: 0x30 183 __IO u32 CH7DR; ///< ADC channel7 data register, offset: 0x34 184 __IO u32 CH8DR; ///< ADC channel8 data register, offset: 0x38 185 } ADC_TypeDef; 186 #endif 187 #ifdef USENOLDREGISTER 188 typedef struct { 189 __IO u32 ADDATA; ///< ADC data register, offset: 0x00 190 __IO u32 ADCFG; ///< ADC configuration register, offset: 0x04 191 __IO u32 ADCR; ///< ADC control register, offset: 0x08 192 __IO u32 ADCHS; ///< ADC channel selection register, offset: 0x0C 193 __IO u32 ADCMPR; ///< ADC window compare register, offset: 0x10 194 __IO u32 ADSTA; ///< ADC status register, offset: 0x14 195 __IO u32 ADDR0; ///< ADC channel0 data register, offset: 0x18 196 __IO u32 ADDR1; ///< ADC channel1 data register, offset: 0x1C 197 __IO u32 ADDR2; ///< ADC channel2 data register, offset: 0x20 198 __IO u32 ADDR3; ///< ADC channel3 data register, offset: 0x24 199 __IO u32 ADDR4; ///< ADC channel4 data register, offset: 0x28 200 __IO u32 ADDR5; ///< ADC channel5 data register, offset: 0x2C 201 __IO u32 ADDR6; ///< ADC channel6 data register, offset: 0x30 202 __IO u32 ADDR7; ///< ADC channel7 data register, offset: 0x34 203 __IO u32 ADDR8; ///< ADC channel8 data register, offset: 0x38 204 } ADC_TypeDef; 205 #endif 206 207 208 209 //////////////////////////////////////////////////////////////////////////////// 210 /// @brief ADC type pointer Definition 211 //////////////////////////////////////////////////////////////////////////////// 212 #define ADC1 ((ADC_TypeDef*) ADC1_BASE) 213 #define ADC2 ((ADC_TypeDef*) ADC2_BASE) 214 #define ADC3 ((ADC_TypeDef*) ADC3_BASE) 215 216 217 //////////////////////////////////////////////////////////////////////////////// 218 /// @brief ADC_DR Register Bit Definition 219 //////////////////////////////////////////////////////////////////////////////// 220 #define ADC_DR_DATA_Pos (0) 221 #define ADC_DR_DATA (0xFFFFU << ADC_DR_DATA_Pos) ///< ADC 12bit convert data 222 223 #define ADC_DR_CH_Pos (16) 224 #define ADC_DR_CH (0x0FU << ADC_DR_CH_Pos) ///< CHANNELSEL[19:16] (ADC current channel convert data) 225 226 #define ADC_DR_CH0 (0x00U << ADC_DR_CH_Pos) ///< ADC Channel select 0 227 #define ADC_DR_CH1 (0x01U << ADC_DR_CH_Pos) ///< ADC Channel select 1 228 #define ADC_DR_CH2 (0x02U << ADC_DR_CH_Pos) ///< ADC Channel select 2 229 #define ADC_DR_CH3 (0x03U << ADC_DR_CH_Pos) ///< ADC Channel select 3 230 #define ADC_DR_CH4 (0x04U << ADC_DR_CH_Pos) ///< ADC Channel select 4 231 #define ADC_DR_CH5 (0x05U << ADC_DR_CH_Pos) ///< ADC Channel select 5 232 #define ADC_DR_CH6 (0x06U << ADC_DR_CH_Pos) ///< ADC Channel select 6 233 #define ADC_DR_CH7 (0x07U << ADC_DR_CH_Pos) ///< ADC Channel select 7 234 235 #define ADC_DR_CH8 (0x08U << ADC_DR_CH_Pos) ///< ADC Channel select 8 236 237 #define ADC_DR_CH10 (0x0AU << ADC_DR_CH_Pos) ///< ADC Channel select 10 238 #define ADC_DR_CH11 (0x0BU << ADC_DR_CH_Pos) ///< ADC Channel select 11 239 #define ADC_DR_CH13 (0x0CU << ADC_DR_CH_Pos) ///< ADC Channel select 13 240 241 #define ADC_DR_CH9 (0x09U << ADC_DR_CH_Pos) ///< ADC Channel select 9 242 #define ADC_DR_CH14 (0x0EU << ADC_DR_CH_Pos) ///< ADC Channel select 14 243 #define ADC_DR_CH15 (0x0FU << ADC_DR_CH_Pos) ///< ADC Channel select 15 244 #define ADC_DR_OVERRUN_Pos (20) 245 #define ADC_DR_OVERRUN (0x01U << ADC_DR_OVERRUN_Pos) ///< ADC data will be cover 246 #define ADC_DR_VALID_Pos (21) 247 #define ADC_DR_VALID (0x01U << ADC_DR_VALID_Pos) ///< ADC data[11:0] is valid 248 249 //////////////////////////////////////////////////////////////////////////////// 250 /// @brief ADC_CFGR Register Bit Definition 251 //////////////////////////////////////////////////////////////////////////////// 252 #define ADC_CFGR_ADEN_Pos (0) 253 #define ADC_CFGR_ADEN (0x01U << ADC_CFGR_ADEN_Pos) ///< Enable ADC convert 254 #define ADC_CFGR_ADWEN_Pos (1) 255 #define ADC_CFGR_ADWEN (0x01U << ADC_CFGR_ADWEN_Pos) ///< Enable ADC window compare 256 257 258 #define ADC_CFGR_RSLTCTL_Pos (7) 259 #define ADC_CFGR_RSLTCTL (0x07U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 260 #define ADC_CFGR_RSLTCTL_12 (0x00U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 12bit 261 #define ADC_CFGR_RSLTCTL_11 (0x01U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 11bit 262 #define ADC_CFGR_RSLTCTL_10 (0x02U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 10bit 263 #define ADC_CFGR_RSLTCTL_9 (0x03U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 9bit 264 #define ADC_CFGR_RSLTCTL_8 (0x04U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 8bit 265 266 #define ADC_CFGR_TEN_Pos (2) 267 #define ADC_CFGR_TEN (0x01U << ADC_CFGR_TEN_Pos) ///< Enable ADC temperature sensor 268 #define ADC_CFGR_VEN_Pos (3) 269 #define ADC_CFGR_VEN (0x01U << ADC_CFGR_VEN_Pos) ///< Enable ADC voltage reference 270 271 272 273 274 275 #define ADC_CFGR_PRE_Pos (4) 276 #define ADC_CFGR_PREL_Pos (14) 277 #define ADC_CFGR_PRE ((0x07U << ADC_CFGR_PRE_Pos) + (0x01U << ADC_CFGR_PREL_Pos)) 278 #define ADC_CFGR_PRE_2 (0x00U << ADC_CFGR_PRE_Pos) ///< ADC preclk 2 279 #define ADC_CFGR_PRE_4 (0x01U << ADC_CFGR_PRE_Pos) ///< ADC preclk 4 280 #define ADC_CFGR_PRE_6 (0x02U << ADC_CFGR_PRE_Pos) ///< ADC preclk 6 281 #define ADC_CFGR_PRE_8 (0x03U << ADC_CFGR_PRE_Pos) ///< ADC preclk 8 282 #define ADC_CFGR_PRE_10 (0x04U << ADC_CFGR_PRE_Pos) ///< ADC preclk 10 283 #define ADC_CFGR_PRE_12 (0x05U << ADC_CFGR_PRE_Pos) ///< ADC preclk 12 284 #define ADC_CFGR_PRE_14 (0x06U << ADC_CFGR_PRE_Pos) ///< ADC preclk 14 285 #define ADC_CFGR_PRE_16 (0x07U << ADC_CFGR_PRE_Pos) ///< ADC preclk 16 286 #define ADC_CFGR_PRE_3 ((0x01U << ADC_CFGR_PREL_Pos) + (0x00U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 3 287 #define ADC_CFGR_PRE_5 ((0x01U << ADC_CFGR_PREL_Pos) + (0x01U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 5 288 #define ADC_CFGR_PRE_7 ((0x01U << ADC_CFGR_PREL_Pos) + (0x02U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 7 289 #define ADC_CFGR_PRE_9 ((0x01U << ADC_CFGR_PREL_Pos) + (0x03U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 9 290 #define ADC_CFGR_PRE_11 ((0x01U << ADC_CFGR_PREL_Pos) + (0x04U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 11 291 #define ADC_CFGR_PRE_13 ((0x01U << ADC_CFGR_PREL_Pos) + (0x05U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 13 292 #define ADC_CFGR_PRE_15 ((0x01U << ADC_CFGR_PREL_Pos) + (0x06U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 15 293 #define ADC_CFGR_PRE_17 ((0x01U << ADC_CFGR_PREL_Pos) + (0x07U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 17 294 295 #define ADC_CFGR_JADWEN_Pos (16) 296 #define ADC_CFGR_JADWEN (0x01U << ADC_CFGR_JADWEN_Pos) ///< Inject ADC conversion window comparison enable 297 298 299 300 301 //////////////////////////////////////////////////////////////////////////////// 302 /// @brief ADC_CR Register Bit Definition 303 //////////////////////////////////////////////////////////////////////////////// 304 #define ADC_CR_ADIE_Pos (0) 305 #define ADC_CR_ADIE (0x01U << ADC_CR_ADIE_Pos) ///< ADC interrupt enable 306 #define ADC_CR_ADWIE_Pos (1) 307 #define ADC_CR_ADWIE (0x01U << ADC_CR_ADWIE_Pos) ///< ADC window compare interrupt enable 308 #define ADC_CR_TRGEN_Pos (2) 309 #define ADC_CR_TRGEN (0x01U << ADC_CR_TRGEN_Pos) ///< extranal trigger single start AD convert 310 #define ADC_CR_DMAEN_Pos (3) 311 #define ADC_CR_DMAEN (0x01U << ADC_CR_DMAEN_Pos) ///< ADC DMA enable 312 313 #define ADC_CR_ADST_Pos (8) 314 #define ADC_CR_ADST (0x01U << ADC_CR_ADST_Pos) ///< ADC start convert data 315 #define ADC_CR_MODE_Pos (9) 316 #define ADC_CR_MODE (0x03U << ADC_CR_MODE_Pos) ///< ADC convert mode 317 #define ADC_CR_IMM (0x00U << ADC_CR_MODE_Pos) ///< ADC imm convert mode 318 #define ADC_CR_SCAN (0x01U << ADC_CR_MODE_Pos) ///< ADC scan convert mode 319 #define ADC_CR_CONTINUE (0x02U << ADC_CR_MODE_Pos) ///< ADC continue scan convert mode 320 #define ADC_CR_ALIGN_Pos (11) 321 #define ADC_CR_ALIGN (0x01U << ADC_CR_ALIGN_Pos) ///< ADC data align 322 #define ADC_CR_LEFT (0x01U << ADC_CR_ALIGN_Pos) ///< ADC data left align 323 #define ADC_CR_RIGHT (0x00U << ADC_CR_ALIGN_Pos) ///< ADC data right align 324 #define ADC_CR_CMPCH_Pos (12) 325 #define ADC_CR_CMPCH (0x0FU << ADC_CR_CMPCH_Pos) ///< CMPCH[15:12] ADC window compare channel0 convert data 326 #define ADC_CR_CMPCH_0 (0x00U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 0 Conversion Results 327 #define ADC_CR_CMPCH_1 (0x01U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 1 Conversion Results 328 #define ADC_CR_CMPCH_2 (0x02U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 2 Conversion Results 329 #define ADC_CR_CMPCH_4 (0x04U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 4 Conversion Results 330 #define ADC_CR_CMPCH_5 (0x05U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 5 Conversion Results 331 #define ADC_CR_CMPCH_6 (0x06U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 6 Conversion Results 332 #define ADC_CR_CMPCH_7 (0x07U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 7 Conversion Results 333 #define ADC_CR_CMPCH_8 (0x08U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 8 Conversion Results 334 #define ADC_CR_CMPCH_9 (0x09U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 9 Conversion Results 335 #define ADC_CR_CMPCH_10 (0x0AU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 10 Conversion Results 336 #define ADC_CR_CMPCH_11 (0x0BU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 11 Conversion Results 337 #define ADC_CR_CMPCH_13 (0x0DU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 13 Conversion Results 338 #define ADC_CR_CMPCH_14 (0x0EU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 14 Conversion Results 339 #define ADC_CR_CMPCH_ALL (0x0FU << ADC_CR_CMPCH_Pos) ///< Select Compare ALL Channel Conversion Results 340 341 342 343 #define ADC_CR_SCANDIR_Pos (16) 344 #define ADC_CR_SCANDIR (0x01U << ADC_CR_SCANDIR_Pos) ///< ADC scan direction 345 #define ADC_CR_TRGSEL_H_Pos (17) 346 #define ADC_CR_TRGSEL_L_Pos (4) 347 #define ADC_CR_TRGSEL ((0x03U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos)) ///< TRGSEL[6:4][18:17] ADC external trigger source select 348 #define ADC_CR_T1_CC1 (0x00U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC1 349 #define ADC_CR_T1_CC2 (0x01U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC2 350 #define ADC_CR_T1_CC3 (0x02U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC3 351 #define ADC_CR_T2_CC2 (0x03U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T2_CC2 352 #define ADC_CR_T3_TRIG (0x04U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T3_TRIG 353 #define ADC_CR_T1_CC4_CC5 (0x05U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC4_CC5 354 #define ADC_CR_T3_CC1 (0x06U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T3_CC1 355 #define ADC_CR_EXTI_11 (0x07U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is EXTI_11 356 #define ADC_CR_T1_TRIG ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T1_TRIG 357 #define ADC_CR_T8_CC4 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC4 358 #define ADC_CR_T8_CC4_CC5 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x02U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC4_CC5 359 #define ADC_CR_T2_CC1 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x03U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T2_CC1 360 #define ADC_CR_T3_CC4 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x04U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T3_CC4 361 #define ADC_CR_T2_TRIG ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x05U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T2_TRIG 362 #define ADC_CR_T8_CC5 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x06U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC5 363 #define ADC_CR_EXTI_15 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is EXTI_15 364 #define ADC_CR_TIM1_CC4 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is TIM1_CC4 365 #define ADC_CR_TIM1_CC5 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is TIM1_CC5 366 367 #define ADC_CR_TRGSHIFT_Pos (19) 368 #define ADC_CR_TRGSHIFT (0x07U << ADC_CR_TRGSHIFT_Pos) ///< External trigger shift sample 369 #define ADC_CR_TRGSHIFT_0 (0x00U << ADC_CR_TRGSHIFT_Pos) ///< No shift 370 #define ADC_CR_TRGSHIFT_4 (0x01U << ADC_CR_TRGSHIFT_Pos) ///< Shift 4 period 371 #define ADC_CR_TRGSHIFT_16 (0x02U << ADC_CR_TRGSHIFT_Pos) ///< Shift 16 period 372 #define ADC_CR_TRGSHIFT_32 (0x03U << ADC_CR_TRGSHIFT_Pos) ///< Shift 32 period 373 #define ADC_CR_TRGSHIFT_64 (0x04U << ADC_CR_TRGSHIFT_Pos) ///< Shift 64 period 374 #define ADC_CR_TRGSHIFT_128 (0x05U << ADC_CR_TRGSHIFT_Pos) ///< Shift 128 period 375 #define ADC_CR_TRGSHIFT_256 (0x06U << ADC_CR_TRGSHIFT_Pos) ///< Shift 256 period 376 #define ADC_CR_TRGSHIFT_512 (0x07U << ADC_CR_TRGSHIFT_Pos) ///< Shift 512 period 377 #define ADC_CR_CALIBEN_Pos (22) 378 #define ADC_CR_CALIBEN (0x01U << ADC_CR_CALIBEN_Pos) ///< Self-calibration enable 379 #define ADC_CR_CALIBSEL_Pos (23) 380 #define ADC_CR_CALIBSEL (0x01U << ADC_CR_CALIBSEL_Pos) ///< Self-calibration voltage selection 381 #define ADC_CR_TRG_EDGE_Pos (24) 382 #define ADC_CR_TRG_EDGE (0x03U << ADC_CR_TRG_EDGE_Pos) ///< ADC trig edge config 383 #define ADC_CR_TRG_EDGE_DUAL (0x00U << ADC_CR_TRG_EDGE_Pos) ///< ADC dual edge trig mode 384 #define ADC_CR_TRG_EDGE_DOWN (0x01U << ADC_CR_TRG_EDGE_Pos) ///< ADC down edge trig mode 385 #define ADC_CR_TRG_EDGE_UP (0x02U << ADC_CR_TRG_EDGE_Pos) ///< ADC up edge trig mode 386 #define ADC_CR_TRG_EDGE_MASK (0x03U << ADC_CR_TRG_EDGE_Pos) ///< ADC mask edge trig mode 387 388 #define ADC_CR_EOSMPIE_Pos (26) 389 #define ADC_CR_EOSMPIE (0X01U << ADC_CR_EOSMPIE_Pos) ///< ADC end sampling flag interrupt enable 390 #define ADC_CR_EOCIE_Pos (27) 391 #define ADC_CR_EOCIE (0X01U << ADC_CR_EOCIE_Pos) ///< ADC end of conversion interrupt enable 392 //////////////////////////////////////////////////////////////////////////////// 393 /// @brief ADC_CHSR Register Bit Definition 394 //////////////////////////////////////////////////////////////////////////////// 395 #define ADC_CHSR_CH0_Pos (0) 396 #define ADC_CHSR_CH0 (0x01U << ADC_CHSR_CH0_Pos) ///< Enable ADC channel 0 397 #define ADC_CHSR_CH1_Pos (1) 398 #define ADC_CHSR_CH1 (0x01U << ADC_CHSR_CH1_Pos) ///< Enable ADC channel 1 399 #define ADC_CHSR_CH2_Pos (2) 400 #define ADC_CHSR_CH2 (0x01U << ADC_CHSR_CH2_Pos) ///< Enable ADC channel 2 401 #define ADC_CHSR_CH3_Pos (3) 402 #define ADC_CHSR_CH3 (0x01U << ADC_CHSR_CH3_Pos) ///< Enable ADC channel 3 403 #define ADC_CHSR_CH4_Pos (4) 404 #define ADC_CHSR_CH4 (0x01U << ADC_CHSR_CH4_Pos) ///< Enable ADC channel 4 405 #define ADC_CHSR_CH5_Pos (5) 406 #define ADC_CHSR_CH5 (0x01U << ADC_CHSR_CH5_Pos) ///< Enable ADC channel 5 407 #define ADC_CHSR_CH6_Pos (6) 408 #define ADC_CHSR_CH6 (0x01U << ADC_CHSR_CH6_Pos) ///< Enable ADC channel 6 409 #define ADC_CHSR_CH7_Pos (7) 410 #define ADC_CHSR_CH7 (0x01U << ADC_CHSR_CH7_Pos) ///< Enable ADC channel 7 411 412 #define ADC_CHSR_CH8_Pos (8) 413 #define ADC_CHSR_CH8 (0x01U << ADC_CHSR_CH8_Pos) ///< Enable ADC channel 8 414 #define ADC_CHSR_CH9_Pos (9) 415 #define ADC_CHSR_CH9 (0x01U << ADC_CHSR_CH9_Pos) ///< Enable ADC channel 9 416 #define ADC_CHSR_CHT_Pos (14) 417 #define ADC_CHSR_CHT (0x01U << ADC_CHSR_CHT_Pos) ///< Enable Temperature Sensor 418 #define ADC_CHSR_CHV_Pos (15) 419 #define ADC_CHSR_CHV (0x01U << ADC_CHSR_CHV_Pos) ///< Enable Voltage Sensor 420 421 422 #define ADC_CHSR_CH10_Pos (10) 423 #define ADC_CHSR_CH10 (0x01U << ADC_CHSR_CH10_Pos) ///< Enable ADC channel 10 424 #define ADC_CHSR_CH11_Pos (11) 425 #define ADC_CHSR_CH11 (0x01U << ADC_CHSR_CH11_Pos) ///< Enable ADC channel 11 426 #define ADC_CHSR_CH12_Pos (12) 427 #define ADC_CHSR_CH12 (0x01U << ADC_CHSR_CH12_Pos) ///< Enable ADC channel 12 428 #define ADC_CHSR_CH13_Pos (13) 429 #define ADC_CHSR_CH13 (0x01U << ADC_CHSR_CH13_Pos) ///< Enable ADC channel 13 430 //////////////////////////////////////////////////////////////////////////////// 431 /// @brief ADC_CMPR Register Bit Definition 432 //////////////////////////////////////////////////////////////////////////////// 433 #define ADC_CMPR_CMPLDATA_Pos (0) 434 #define ADC_CMPR_CMPLDATA (0x0FFFU << ADC_CMPR_CMPLDATA_Pos) ///< ADC 12bit window compare DOWN LEVEL DATA 435 #define ADC_CMPR_CMPHDATA_Pos (16) 436 #define ADC_CMPR_CMPHDATA (0x0FFFU << ADC_CMPR_CMPHDATA_Pos) ///< ADC 12bit window compare UP LEVEL DATA 437 438 //////////////////////////////////////////////////////////////////////////////// 439 /// @brief ADC_SR Register Bit Definition 440 //////////////////////////////////////////////////////////////////////////////// 441 #define ADC_SR_ADIF_Pos (0) 442 #define ADC_SR_ADIF (0x01U << ADC_SR_ADIF_Pos) ///< ADC convert complete flag 443 #define ADC_SR_ADWIF_Pos (1) 444 #define ADC_SR_ADWIF (0x01U << ADC_SR_ADWIF_Pos) ///< ADC compare flag 445 #define ADC_SR_BUSY_Pos (2) 446 #define ADC_SR_BUSY (0x01U << ADC_SR_BUSY_Pos) ///< ADC busy flag 447 #define ADC_SR_CH_Pos (4) 448 #define ADC_SR_CH (0x0FU << ADC_SR_CH_Pos) ///< CHANNEL[7:4] ADC current channel 449 #define ADC_SR_CH0 (0x00U << ADC_SR_CH_Pos) ///< Channel 0 is the current conversion channel 450 #define ADC_SR_CH1 (0x01U << ADC_SR_CH_Pos) ///< Channel 1 is the current conversion channel 451 #define ADC_SR_CH2 (0x02U << ADC_SR_CH_Pos) ///< Channel 2 is the current conversion channel 452 #define ADC_SR_CH3 (0x03U << ADC_SR_CH_Pos) ///< Channel 3 is the current conversion channel 453 #define ADC_SR_CH4 (0x04U << ADC_SR_CH_Pos) ///< Channel 4 is the current conversion channel 454 #define ADC_SR_CH5 (0x05U << ADC_SR_CH_Pos) ///< Channel 5 is the current conversion channel 455 #define ADC_SR_CH6 (0x06U << ADC_SR_CH_Pos) ///< Channel 6 is the current conversion channel 456 #define ADC_SR_CH7 (0x07U << ADC_SR_CH_Pos) ///< Channel 7 is the current conversion channel 457 #define ADC_SR_CH8 (0x08U << ADC_SR_CH_Pos) ///< Channel 8 is the current conversion channel 458 #define ADC_SR_CH9 (0x09U << ADC_SR_CH_Pos) ///< Channel 9 is the current conversion channel 459 #define ADC_SR_CH10 (0x0AU << ADC_SR_CH_Pos) ///< Channel 10 is the current conversion channel 460 #define ADC_SR_CH11 (0x0BU << ADC_SR_CH_Pos) ///< Channel 11 is the current conversion channel 461 #define ADC_SR_CH13 (0x0DU << ADC_SR_CH_Pos) ///< Channel 13 is the current conversion channel 462 #define ADC_SR_CH14 (0x0EU << ADC_SR_CH_Pos) ///< Channel 14 is the current conversion channel 463 #define ADC_SR_CH15 (0x0FU << ADC_SR_CH_Pos) ///< Channel 15 is the current conversion channel 464 465 466 #define ADC_SR_VALID_Pos (8) 467 #define ADC_SR_VALID (0x0FFFU << ADC_SR_VALID_Pos) ///< VALID[19:8] ADC channel 0..11 valid flag 468 #define ADC_SR_OVERRUN_Pos (20) 469 #define ADC_SR_OVERRUN (0x0FFFU << ADC_SR_OVERRUN_Pos) ///< OVERRUN[31:20] ADC channel 0..11 data covered flag 470 471 //////////////////////////////////////////////////////////////////////////////// 472 /// @brief ADC_CHnDR Register Bit Definition 473 //////////////////////////////////////////////////////////////////////////////// 474 #define ADC_CHDR_DATA_Pos (0) 475 #define ADC_CHDR_DATA (0xFFFFU << ADC_CHDR_DATA_Pos) ///< ADC channel convert data 476 #define ADC_CHDR_OVERRUN_Pos (20) 477 #define ADC_CHDR_OVERRUN (0x01U << ADC_CHDR_OVERRUN_Pos) ///< ADC data covered flag 478 #define ADC_CHDR_VALID_Pos (21) 479 #define ADC_CHDR_VALID (0x01U << ADC_CHDR_VALID_Pos) ///< ADC data valid flag 480 481 //////////////////////////////////////////////////////////////////////////////// 482 /// @brief ADC_SREXT Register Bit Definition 483 //////////////////////////////////////////////////////////////////////////////// 484 #define ADC_SREXT_VALID_Pos (0) 485 #define ADC_SREXT_VALID (0x0FU << ADC_SREXT_VALID_Pos) ///< VALID[3:0] ADC channel 12,14..15 valid flag 486 #define ADC_SREXT_OVERRUN_Pos (4) 487 #define ADC_SREXT_OVERRUN (0x0FU << ADC_SREXT_OVERRUN_Pos) ///< OVERRUN[7:4] ADC channel 12,14..15 data covered flag 488 489 490 #define ADC_SREXT_EOSMPIF_Pos (16) 491 #define ADC_SREXT_EOSMPIF (0x01U << ADC_SREXT_EOSMPIF_Pos) ///< End of sampling interrupt flag 492 #define ADC_SREXT_EOCIF_Pos (17) 493 #define ADC_SREXT_EOCIF (0x01U << ADC_SREXT_EOCIF_Pos) ///< End of conversion interrupt flag 494 #define ADC_SREXT_JEOSMPIF_Pos (18) 495 #define ADC_SREXT_JEOSMPIF (0x01U << ADC_SREXT_JEOSMPIF_Pos) /// Injected channel end of sampling interrupt flag 496 #define ADC_SREXT_JEOCIF_Pos (19) 497 #define ADC_SREXT_JEOCIF (0x03U << ADC_SREXT_JEOCIF_Pos) ///< Injected channel end of conversion interrupt flag 498 #define ADC_SREXT_JEOSIF_Pos (20) 499 #define ADC_SREXT_JEOSIF (0x03U << ADC_SREXT_JEOSIF_Pos) ///< Injected channel end of sequential conversion interrupt flag 500 #define ADC_SREXT_JBUSY_Pos (21) 501 #define ADC_SREXT_JBUSY (0x01U << ADC_SREXT_JBUSY_Pos) ///< Injection mode busy/idle 502 503 //////////////////////////////////////////////////////////////////////////////// 504 /// @brief ADC_CHANY0 select Register Bit Definition 505 //////////////////////////////////////////////////////////////////////////////// 506 #define ADC1_CHANY0_SEL0_Pos (0) ///< CHANY_SEL0 (Bit 0) 507 #define ADC1_CHANY0_SEL0 (0x0FU << ADC1_CHANY0_SEL0_Pos) ///< CHANY_SEL0 (Bitfield-Mask: 0x0f) 508 #define ADC1_CHANY0_SEL1_Pos (4) ///< CHANY_SEL1 (Bit 4) 509 #define ADC1_CHANY0_SEL1 (0x0FU << ADC1_CHANY0_SEL1_Pos) ///< CHANY_SEL1 (Bitfield-Mask: 0x0f) 510 #define ADC1_CHANY0_SEL2_Pos (8) ///< CHANY_SEL2 (Bit 8) 511 #define ADC1_CHANY0_SEL2 (0x0FU << ADC1_CHANY0_SEL2_Pos) ///< CHANY_SEL2 (Bitfield-Mask: 0x0f) 512 #define ADC1_CHANY0_SEL3_Pos (12) ///< CHANY_SEL3 (Bit 12) 513 #define ADC1_CHANY0_SEL3 (0x0FU << ADC1_CHANY0_SEL3_Pos) ///< CHANY_SEL3 (Bitfield-Mask: 0x0f) 514 #define ADC1_CHANY0_SEL4_Pos (16) ///< CHANY_SEL4 (Bit 16) 515 #define ADC1_CHANY0_SEL4 (0x0FU << ADC1_CHANY0_SEL4_Pos) ///< CHANY_SEL4 (Bitfield-Mask: 0x0f) 516 #define ADC1_CHANY0_SEL5_Pos (20) ///< CHANY_SEL5 (Bit 20) 517 #define ADC1_CHANY0_SEL5 (0x0FU << ADC1_CHANY0_SEL5_Pos) ///< CHANY_SEL5 (Bitfield-Mask: 0x0f) 518 #define ADC1_CHANY0_SEL6_Pos (24) ///< CHANY_SEL6 (Bit 24) 519 #define ADC1_CHANY0_SEL6 (0x0FU << ADC1_CHANY0_SEL6_Pos) ///< CHANY_SEL6 (Bitfield-Mask: 0x0f) 520 #define ADC1_CHANY0_SEL7_Pos (28) ///< CHANY_SEL7 (Bit 28) 521 #define ADC1_CHANY0_SEL7 (0x0FU << ADC1_CHANY0_SEL7_Pos) ///< CHANY_SEL7 (Bitfield-Mask: 0x0f) 522 523 //////////////////////////////////////////////////////////////////////////////// 524 /// @brief ADC_CHANY1 select Register Bit Definition 525 //////////////////////////////////////////////////////////////////////////////// 526 #define ADC1_CHANY1_SEL8_Pos (0) ///< CHANY_SEL8 (Bit 0) 527 #define ADC1_CHANY1_SEL8 (0x0FU << ADC1_CHANY1_SEL8_Pos) ///< CHANY_SEL8 (Bitfield-Mask: 0x0f) 528 #define ADC1_CHANY1_SEL9_Pos (4) ///< CHANY_SEL9 (Bit 4) 529 #define ADC1_CHANY1_SEL9 (0x0FU << ADC1_CHANY1_SEL9_Pos) ///< CHANY_SEL9 (Bitfield-Mask: 0x0f) 530 531 #define ADC1_CHANY1_SEL14_Pos (24) ///< CHANY_SEL14 (Bit 24) 532 #define ADC1_CHANY1_SEL14 (0x0FU << ADC1_CHANY1_SEL14_Pos) ///< CHANY_SEL14 (Bitfield-Mask: 0x0f) 533 #define ADC1_CHANY1_SEL15_Pos (28) ///< CHANY_SEL15 (Bit 28) 534 #define ADC1_CHANY1_SEL15 (0x0FU << ADC1_CHANY1_SEL15_Pos) ///< CHANY_SEL15 (Bitfield-Mask: 0x0f) 535 #define ADC1_CHANY1_SEL10_Pos (8) ///< CHANY_SEL10 (Bit 8) 536 #define ADC1_CHANY1_SEL10 (0x0FU << ADC1_CHANY1_SEL10_Pos) ///< CHANY_SEL10 (Bitfield-Mask: 0x0f) 537 #define ADC1_CHANY1_SEL11_Pos (12) ///< CHANY_SEL11 (Bit 12) 538 #define ADC1_CHANY1_SEL11 (0x0FU << ADC1_CHANY1_SEL11_Pos) ///< CHANY_SEL11 (Bitfield-Mask: 0x0f) 539 #define ADC1_CHANY1_SEL12_Pos (16) ///< CHANY_SEL12 (Bit 16) 540 #define ADC1_CHANY1_SEL12 (0x0FU << ADC1_CHANY1_SEL12_Pos) ///< CHANY_SEL12 (Bitfield-Mask: 0x0f) 541 #define ADC1_CHANY1_SEL13_Pos (20) ///< CHANY_SEL13 (Bit 20) 542 #define ADC1_CHANY1_SEL13 (0x0FU << ADC1_CHANY1_SEL13_Pos) ///< CHANY_SEL13 (Bitfield-Mask: 0x0f) 543 //////////////////////////////////////////////////////////////////////////////// 544 /// @brief ADC_CHANY config number Register Bit Definition 545 //////////////////////////////////////////////////////////////////////////////// 546 #define ADC1_CHANY_CFG_NUM_Max (16) ///< CHANY_CFG_NUM Max Value is 16 547 548 //////////////////////////////////////////////////////////////////////////////// 549 /// @brief ADC_CHANY mode enable Register Bit Definition 550 //////////////////////////////////////////////////////////////////////////////// 551 #define ADC1_CHANY_CR_MDEN_Pos (0) ///< CHANY_MDEN (Bit 0) 552 #define ADC1_CHANY_CR_MDEN (0x01U << ADC1_CHANY_CR_MDEN_Pos) ///< CHANY_MDEN (Bitfield-Mask: 0x01) 553 554 555 //////////////////////////////////////////////////////////////////////////////// 556 /// @brief ADC_ANY_CR mode enable Register Bit Definition 557 //////////////////////////////////////////////////////////////////////////////// 558 #define ADC_ANY_CR_JTRGEDGE_Pos (16) ///< Injection mode triggers edge selection 559 #define ADC_ANY_CR_JTRGEDGE_R_F (0x00U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Triggered along both rising and falling edges 560 #define ADC_ANY_CR_JTRGEDGE_F (0x01U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Drop edge trigger 561 #define ADC_ANY_CR_JTRGEDGE_R (0x02U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Rising edge trigger 562 #define ADC_ANY_CR_JTRGEDGE_S (0x03U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Shield trigger 563 564 #define ADC_ANY_CR_JTRGSHIFT_Pos (13) ///< Injection mode external trigger delay sampling 565 #define ADC_ANY_CR_JTRGSHIFT_0 (0x00U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 0 cycle 566 #define ADC_ANY_CR_JTRGSHIFT_4 (0x01U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 4 cycle 567 #define ADC_ANY_CR_JTRGSHIFT_16 (0x02U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 16 cycle 568 #define ADC_ANY_CR_JTRGSHIFT_32 (0x03U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 32 cycle 569 #define ADC_ANY_CR_JTRGSHIFT_64 (0x04U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 64 cycle 570 #define ADC_ANY_CR_JTRGSHIFT_128 (0x05U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 128 cycle 571 #define ADC_ANY_CR_JTRGSHIFT_256 (0x06U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 256 cycle 572 #define ADC_ANY_CR_JTRGSHIFT_512 (0x07U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 512 cycle 573 574 #define ADC_ANY_CR_JTRGSEL_Pos (8) ///< External event select for injected group 575 #define ADC_ANY_CR_JTRGSEL (0x07U << ADC_ANY_CR_JTRGSEL_Pos) 576 #define ADC_ANY_CR_JTRGSEL_TIM1_TRGO (0x00U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 TRGO 577 #define ADC_ANY_CR_JTRGSEL_TIM1_CC4 (0x01U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 CC4 578 #define ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5 (0x02U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 CC4 and CC5 579 #define ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1 (0x03U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM2 CC1 and TIM4 CC1 580 #define ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4 (0x04U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM3 CC4 and TIM5 CC4 581 #define ADC_ANY_CR_JTRGSEL_TIM8_CC4 (0x05U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM8 CC4 582 #define ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5 (0x06U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM8 CC4 and CC5 583 #define ADC_ANY_CR_JTRGSEL_EXTI12 (0x07U << ADC_ANY_CR_JTRGSEL_Pos) ///< EXTI12 584 585 #define ADC_ANY_CR_JTRGEN_Pos (7) 586 #define ADC_ANY_CR_JTRGEN (0x01U << ADC_ANY_CR_JTRGEN_Pos) ///< External trigger conversion mode for injected channels 587 #define ADC_ANY_CR_JADST_Pos (6) 588 #define ADC_ANY_CR_JADST (0x01U << ADC_ANY_CR_JADST_Pos) ///< Start conversion of injected channels 589 #define ADC_ANY_CR_JAUTO_Pos (5) 590 #define ADC_ANY_CR_JAUTO (0x01U << ADC_ANY_CR_JAUTO_Pos) ///<Automatic Injected group conversion 591 #define ADC_ANY_CR_JEOSIE_Pos (4) 592 #define ADC_ANY_CR_JEOSIE (0x01U << ADC_ANY_CR_JEOSIE_Pos) ///< Interrupt enable the end of sequence conversion for injected channel 593 #define ADC_ANY_CR_JEOCIE_Pos (3) 594 #define ADC_ANY_CR_JEOCIE (0x01U << ADC_ANY_CR_JEOCIE_Pos) ///< Interrupt enable the end of conversion for injected channel 595 #define ADC_ANY_CR_JEOSMPIE_Pos (2) 596 #define ADC_ANY_CR_JEOSMPIE (0x01U << ADC_ANY_CR_JEOSMPIE_Pos) ///< Interrupt enable the end of sequence conversion for injected channel 597 #define ADC_ANY_CR_JCEN_Pos (1) 598 #define ADC_ANY_CR_JCEN (0x01U << ADC_ANY_CR_JCEN_Pos) ///< Injected channel enable 599 600 #define ADC_ANY_CR_CHANY_MDEN_Pos (0) 601 #define ADC_ANY_CR_CHANY_MDEN (0x01U << ADC_ANY_CR_CHANY_MDEN_Pos) ///< Enable bits for any channel configuration mode: 602 603 //////////////////////////////////////////////////////////////////////////////// 604 /// @brief ADC_SMPR1 mode enable Register Bit Definition 605 //////////////////////////////////////////////////////////////////////////////// 606 #define ADC_SMPR_SAMCTL_Pos (0) ///< Injection mode external trigger delay sampling off_set Position 607 #define ADC_SMPR_SAMCTL_Msk (0x0FU << ADC_SMPR_SAMCTL_Pos) ///< Injection mode external trigger delay sampling mask for Value 608 #define ADC_SMPR_SAMCTL_2_5 (0x00U << ADC_SMPR_SAMCTL_Pos) ///< 2.5 cycle 609 #define ADC_SMPR_SAMCTL_8_5 (0x01U << ADC_SMPR_SAMCTL_Pos) ///< 8.5 cycle 610 #define ADC_SMPR_SAMCTL_14_5 (0x02U << ADC_SMPR_SAMCTL_Pos) ///< 14.5 cycle 611 #define ADC_SMPR_SAMCTL_29_5 (0x03U << ADC_SMPR_SAMCTL_Pos) ///< 29.5 cycle 612 #define ADC_SMPR_SAMCTL_42_5 (0x04U << ADC_SMPR_SAMCTL_Pos) ///< 42.5 cycle 613 #define ADC_SMPR_SAMCTL_56_5 (0x05U << ADC_SMPR_SAMCTL_Pos) ///< 56.5 cycle 614 #define ADC_SMPR_SAMCTL_72_5 (0x06U << ADC_SMPR_SAMCTL_Pos) ///< 72.5 cycle 615 #define ADC_SMPR_SAMCTL_240_5 (0x07U << ADC_SMPR_SAMCTL_Pos) ///< 240.5 cycle 616 #define ADC_SMPR_SAMCTL_3_5 (0x08U << ADC_SMPR_SAMCTL_Pos) ///< 3.5 cycle 617 #define ADC_SMPR_SAMCTL_4_5 (0x09U << ADC_SMPR_SAMCTL_Pos) ///< 4.5 cycle 618 #define ADC_SMPR_SAMCTL_5_5 (0x0AU << ADC_SMPR_SAMCTL_Pos) ///< 5.5 cycle 619 #define ADC_SMPR_SAMCTL_6_5 (0x0BU << ADC_SMPR_SAMCTL_Pos) ///< 6.5 cycle 620 #define ADC_SMPR_SAMCTL_7_5 (0x0CU << ADC_SMPR_SAMCTL_Pos) ///< 7.5 cycle 621 622 623 #define ADC_SMPR1_SAMCTL7_Pos (28) ///< Injection mode external trigger delay sampling 624 #define ADC_SMPR1_SAMCTL7_Msk (0x0FU << ADC_SMPR1_SAMCTL7_Pos) ///< Injection mode external trigger delay sampling mask for Value 625 #define ADC_SMPR1_SAMCTL7_2_5 (0x00U << ADC_SMPR1_SAMCTL7_Pos) ///< 2.5 cycle 626 #define ADC_SMPR1_SAMCTL7_8_5 (0x01U << ADC_SMPR1_SAMCTL7_Pos) ///< 8.5 cycle 627 #define ADC_SMPR1_SAMCTL7_14_5 (0x02U << ADC_SMPR1_SAMCTL7_Pos) ///< 14.5 cycle 628 #define ADC_SMPR1_SAMCTL7_29_5 (0x03U << ADC_SMPR1_SAMCTL7_Pos) ///< 29.5 cycle 629 #define ADC_SMPR1_SAMCTL7_42_5 (0x04U << ADC_SMPR1_SAMCTL7_Pos) ///< 42.5 cycle 630 #define ADC_SMPR1_SAMCTL7_56_5 (0x05U << ADC_SMPR1_SAMCTL7_Pos) ///< 56.5 cycle 631 #define ADC_SMPR1_SAMCTL7_72_5 (0x06U << ADC_SMPR1_SAMCTL7_Pos) ///< 72.5 cycle 632 #define ADC_SMPR1_SAMCTL7_240_5 (0x07U << ADC_SMPR1_SAMCTL7_Pos) ///< 240.5 cycle 633 #define ADC_SMPR1_SAMCTL7_3_5 (0x08U << ADC_SMPR1_SAMCTL7_Pos) ///< 3.5 cycle 634 #define ADC_SMPR1_SAMCTL7_4_5 (0x09U << ADC_SMPR1_SAMCTL7_Pos) ///< 4.5 cycle 635 #define ADC_SMPR1_SAMCTL7_5_5 (0x0AU << ADC_SMPR1_SAMCTL7_Pos) ///< 5.5 cycle 636 #define ADC_SMPR1_SAMCTL7_6_5 (0x0BU << ADC_SMPR1_SAMCTL7_Pos) ///< 6.5 cycle 637 #define ADC_SMPR1_SAMCTL7_7_5 (0x0CU << ADC_SMPR1_SAMCTL7_Pos) ///< 7.5 cycle 638 #define ADC_SMPR1_SAMCTL6_Pos (24) ///< Injection mode external trigger delay sampling 639 #define ADC_SMPR1_SAMCTL6_2_5 (0x00U << ADC_SMPR1_SAMCTL6_Pos) ///< 2.5 cycle 640 #define ADC_SMPR1_SAMCTL6_8_5 (0x01U << ADC_SMPR1_SAMCTL6_Pos) ///< 8.5 cycle 641 #define ADC_SMPR1_SAMCTL6_14_5 (0x02U << ADC_SMPR1_SAMCTL6_Pos) ///< 14.5 cycle 642 #define ADC_SMPR1_SAMCTL6_29_5 (0x03U << ADC_SMPR1_SAMCTL6_Pos) ///< 29.5 cycle 643 #define ADC_SMPR1_SAMCTL6_42_5 (0x04U << ADC_SMPR1_SAMCTL6_Pos) ///< 42.5 cycle 644 #define ADC_SMPR1_SAMCTL6_56_5 (0x05U << ADC_SMPR1_SAMCTL6_Pos) ///< 56.5 cycle 645 #define ADC_SMPR1_SAMCTL6_72_5 (0x06U << ADC_SMPR1_SAMCTL6_Pos) ///< 72.5 cycle 646 #define ADC_SMPR1_SAMCTL6_240_5 (0x07U << ADC_SMPR1_SAMCTL6_Pos) ///< 240.5 cycle 647 #define ADC_SMPR1_SAMCTL6_3_5 (0x08U << ADC_SMPR1_SAMCTL6_Pos) ///< 3.5 cycle 648 #define ADC_SMPR1_SAMCTL6_4_5 (0x09U << ADC_SMPR1_SAMCTL6_Pos) ///< 4.5 cycle 649 #define ADC_SMPR1_SAMCTL6_5_5 (0x0AU << ADC_SMPR1_SAMCTL6_Pos) ///< 5.5 cycle 650 #define ADC_SMPR1_SAMCTL6_6_5 (0x0BU << ADC_SMPR1_SAMCTL6_Pos) ///< 6.5 cycle 651 #define ADC_SMPR1_SAMCTL6_7_5 (0x0CU << ADC_SMPR1_SAMCTL6_Pos) ///< 7.5 cycle 652 #define ADC_SMPR1_SAMCTL5_Pos (20) ///< Injection mode external trigger delay sampling 653 #define ADC_SMPR1_SAMCTL5_2_5 (0x00U << ADC_SMPR1_SAMCTL5_Pos) ///< 2.5 cycle 654 #define ADC_SMPR1_SAMCTL5_8_5 (0x01U << ADC_SMPR1_SAMCTL5_Pos) ///< 8.5 cycle 655 #define ADC_SMPR1_SAMCTL5_14_5 (0x02U << ADC_SMPR1_SAMCTL5_Pos) ///< 14.5 cycle 656 #define ADC_SMPR1_SAMCTL5_29_5 (0x03U << ADC_SMPR1_SAMCTL5_Pos) ///< 29.5 cycle 657 #define ADC_SMPR1_SAMCTL5_42_5 (0x04U << ADC_SMPR1_SAMCTL5_Pos) ///< 42.5 cycle 658 #define ADC_SMPR1_SAMCTL5_56_5 (0x05U << ADC_SMPR1_SAMCTL5_Pos) ///< 56.5 cycle 659 #define ADC_SMPR1_SAMCTL5_72_5 (0x06U << ADC_SMPR1_SAMCTL5_Pos) ///< 72.5 cycle 660 #define ADC_SMPR1_SAMCTL5_240_5 (0x07U << ADC_SMPR1_SAMCTL5_Pos) ///< 240.5 cycle 661 #define ADC_SMPR1_SAMCTL5_3_5 (0x08U << ADC_SMPR1_SAMCTL5_Pos) ///< 3.5 cycle 662 #define ADC_SMPR1_SAMCTL5_4_5 (0x09U << ADC_SMPR1_SAMCTL5_Pos) ///< 4.5 cycle 663 #define ADC_SMPR1_SAMCTL5_5_5 (0x0AU << ADC_SMPR1_SAMCTL5_Pos) ///< 5.5 cycle 664 #define ADC_SMPR1_SAMCTL5_6_5 (0x0BU << ADC_SMPR1_SAMCTL5_Pos) ///< 6.5 cycle 665 #define ADC_SMPR1_SAMCTL5_7_5 (0x0CU << ADC_SMPR1_SAMCTL5_Pos) ///< 7.5 cycle 666 #define ADC_SMPR1_SAMCTL4_Pos (16) ///< Injection mode external trigger delay sampling 667 #define ADC_SMPR1_SAMCTL4_2_5 (0x00U << ADC_SMPR1_SAMCTL4_Pos) ///< 2.5 cycle 668 #define ADC_SMPR1_SAMCTL4_8_5 (0x01U << ADC_SMPR1_SAMCTL4_Pos) ///< 8.5 cycle 669 #define ADC_SMPR1_SAMCTL4_14_5 (0x02U << ADC_SMPR1_SAMCTL4_Pos) ///< 14.5 cycle 670 #define ADC_SMPR1_SAMCTL4_29_5 (0x03U << ADC_SMPR1_SAMCTL4_Pos) ///< 29.5 cycle 671 #define ADC_SMPR1_SAMCTL4_42_5 (0x04U << ADC_SMPR1_SAMCTL4_Pos) ///< 42.5 cycle 672 #define ADC_SMPR1_SAMCTL4_56_5 (0x05U << ADC_SMPR1_SAMCTL4_Pos) ///< 56.5 cycle 673 #define ADC_SMPR1_SAMCTL4_72_5 (0x06U << ADC_SMPR1_SAMCTL4_Pos) ///< 72.5 cycle 674 #define ADC_SMPR1_SAMCTL4_240_5 (0x07U << ADC_SMPR1_SAMCTL4_Pos) ///< 240.5 cycle 675 #define ADC_SMPR1_SAMCTL4_3_5 (0x08U << ADC_SMPR1_SAMCTL4_Pos) ///< 3.5 cycle 676 #define ADC_SMPR1_SAMCTL4_4_5 (0x09U << ADC_SMPR1_SAMCTL4_Pos) ///< 4.5 cycle 677 #define ADC_SMPR1_SAMCTL4_5_5 (0x0AU << ADC_SMPR1_SAMCTL4_Pos) ///< 5.5 cycle 678 #define ADC_SMPR1_SAMCTL4_6_5 (0x0BU << ADC_SMPR1_SAMCTL4_Pos) ///< 6.5 cycle 679 #define ADC_SMPR1_SAMCTL4_7_5 (0x0CU << ADC_SMPR1_SAMCTL4_Pos) ///< 7.5 cycle 680 #define ADC_SMPR1_SAMCTL3_Pos (12) ///< Injection mode external trigger delay sampling 681 #define ADC_SMPR1_SAMCTL3_2_5 (0x00U << ADC_SMPR1_SAMCTL3_Pos) ///< 2.5 cycle 682 #define ADC_SMPR1_SAMCTL3_8_5 (0x01U << ADC_SMPR1_SAMCTL3_Pos) ///< 8.5 cycle 683 #define ADC_SMPR1_SAMCTL3_14_5 (0x02U << ADC_SMPR1_SAMCTL3_Pos) ///< 14.5 cycle 684 #define ADC_SMPR1_SAMCTL3_29_5 (0x03U << ADC_SMPR1_SAMCTL3_Pos) ///< 29.5 cycle 685 #define ADC_SMPR1_SAMCTL3_42_5 (0x04U << ADC_SMPR1_SAMCTL3_Pos) ///< 42.5 cycle 686 #define ADC_SMPR1_SAMCTL3_56_5 (0x05U << ADC_SMPR1_SAMCTL3_Pos) ///< 56.5 cycle 687 #define ADC_SMPR1_SAMCTL3_72_5 (0x06U << ADC_SMPR1_SAMCTL3_Pos) ///< 72.5 cycle 688 #define ADC_SMPR1_SAMCTL3_240_5 (0x07U << ADC_SMPR1_SAMCTL3_Pos) ///< 240.5 cycle 689 #define ADC_SMPR1_SAMCTL3_3_5 (0x08U << ADC_SMPR1_SAMCTL3_Pos) ///< 3.5 cycle 690 #define ADC_SMPR1_SAMCTL3_4_5 (0x09U << ADC_SMPR1_SAMCTL3_Pos) ///< 4.5 cycle 691 #define ADC_SMPR1_SAMCTL3_5_5 (0x0AU << ADC_SMPR1_SAMCTL3_Pos) ///< 5.5 cycle 692 #define ADC_SMPR1_SAMCTL3_6_5 (0x0BU << ADC_SMPR1_SAMCTL3_Pos) ///< 6.5 cycle 693 #define ADC_SMPR1_SAMCTL3_7_5 (0x0CU << ADC_SMPR1_SAMCTL3_Pos) ///< 7.5 cycle 694 #define ADC_SMPR1_SAMCTL2_Pos (8) ///< Injection mode external trigger delay sampling 695 #define ADC_SMPR1_SAMCTL2_2_5 (0x00U << ADC_SMPR1_SAMCTL2_Pos) ///< 2.5 cycle 696 #define ADC_SMPR1_SAMCTL2_8_5 (0x01U << ADC_SMPR1_SAMCTL2_Pos) ///< 8.5 cycle 697 #define ADC_SMPR1_SAMCTL2_14_5 (0x02U << ADC_SMPR1_SAMCTL2_Pos) ///< 14.5 cycle 698 #define ADC_SMPR1_SAMCTL2_29_5 (0x03U << ADC_SMPR1_SAMCTL2_Pos) ///< 29.5 cycle 699 #define ADC_SMPR1_SAMCTL2_42_5 (0x04U << ADC_SMPR1_SAMCTL2_Pos) ///< 42.5 cycle 700 #define ADC_SMPR1_SAMCTL2_56_5 (0x05U << ADC_SMPR1_SAMCTL2_Pos) ///< 56.5 cycle 701 #define ADC_SMPR1_SAMCTL2_72_5 (0x06U << ADC_SMPR1_SAMCTL2_Pos) ///< 72.5 cycle 702 #define ADC_SMPR1_SAMCTL2_240_5 (0x07U << ADC_SMPR1_SAMCTL2_Pos) ///< 240.5 cycle 703 #define ADC_SMPR1_SAMCTL2_3_5 (0x08U << ADC_SMPR1_SAMCTL2_Pos) ///< 3.5 cycle 704 #define ADC_SMPR1_SAMCTL2_4_5 (0x09U << ADC_SMPR1_SAMCTL2_Pos) ///< 4.5 cycle 705 #define ADC_SMPR1_SAMCTL2_5_5 (0x0AU << ADC_SMPR1_SAMCTL2_Pos) ///< 5.5 cycle 706 #define ADC_SMPR1_SAMCTL2_6_5 (0x0BU << ADC_SMPR1_SAMCTL2_Pos) ///< 6.5 cycle 707 #define ADC_SMPR1_SAMCTL2_7_5 (0x0CU << ADC_SMPR1_SAMCTL2_Pos) ///< 7.5 cycle 708 #define ADC_SMPR1_SAMCTL1_Pos (4) ///< Injection mode external trigger delay sampling 709 #define ADC_SMPR1_SAMCTL1_2_5 (0x00U << ADC_SMPR1_SAMCTL1_Pos) ///< 2.5 cycle 710 #define ADC_SMPR1_SAMCTL1_8_5 (0x01U << ADC_SMPR1_SAMCTL1_Pos) ///< 8.5 cycle 711 #define ADC_SMPR1_SAMCTL1_14_5 (0x02U << ADC_SMPR1_SAMCTL1_Pos) ///< 14.5 cycle 712 #define ADC_SMPR1_SAMCTL1_29_5 (0x03U << ADC_SMPR1_SAMCTL1_Pos) ///< 29.5 cycle 713 #define ADC_SMPR1_SAMCTL1_42_5 (0x04U << ADC_SMPR1_SAMCTL1_Pos) ///< 42.5 cycle 714 #define ADC_SMPR1_SAMCTL1_56_5 (0x05U << ADC_SMPR1_SAMCTL1_Pos) ///< 56.5 cycle 715 #define ADC_SMPR1_SAMCTL1_72_5 (0x06U << ADC_SMPR1_SAMCTL1_Pos) ///< 72.5 cycle 716 #define ADC_SMPR1_SAMCTL1_240_5 (0x07U << ADC_SMPR1_SAMCTL1_Pos) ///< 240.5 cycle 717 #define ADC_SMPR1_SAMCTL1_3_5 (0x08U << ADC_SMPR1_SAMCTL1_Pos) ///< 3.5 cycle 718 #define ADC_SMPR1_SAMCTL1_4_5 (0x09U << ADC_SMPR1_SAMCTL1_Pos) ///< 4.5 cycle 719 #define ADC_SMPR1_SAMCTL1_5_5 (0x0AU << ADC_SMPR1_SAMCTL1_Pos) ///< 5.5 cycle 720 #define ADC_SMPR1_SAMCTL1_6_5 (0x0BU << ADC_SMPR1_SAMCTL1_Pos) ///< 6.5 cycle 721 #define ADC_SMPR1_SAMCTL1_7_5 (0x0CU << ADC_SMPR1_SAMCTL1_Pos) ///< 7.5 cycle 722 #define ADC_SMPR1_SAMCTL0_Pos (0) ///< Injection mode external trigger delay sampling 723 #define ADC_SMPR1_SAMCTL0_2_5 (0x00U << ADC_SMPR1_SAMCTL0_Pos) ///< 2.5 cycle 724 #define ADC_SMPR1_SAMCTL0_8_5 (0x01U << ADC_SMPR1_SAMCTL0_Pos) ///< 8.5 cycle 725 #define ADC_SMPR1_SAMCTL0_14_5 (0x02U << ADC_SMPR1_SAMCTL0_Pos) ///< 14.5 cycle 726 #define ADC_SMPR1_SAMCTL0_29_5 (0x03U << ADC_SMPR1_SAMCTL0_Pos) ///< 29.5 cycle 727 #define ADC_SMPR1_SAMCTL0_42_5 (0x04U << ADC_SMPR1_SAMCTL0_Pos) ///< 42.5 cycle 728 #define ADC_SMPR1_SAMCTL0_56_5 (0x05U << ADC_SMPR1_SAMCTL0_Pos) ///< 56.5 cycle 729 #define ADC_SMPR1_SAMCTL0_72_5 (0x06U << ADC_SMPR1_SAMCTL0_Pos) ///< 72.5 cycle 730 #define ADC_SMPR1_SAMCTL0_240_5 (0x07U << ADC_SMPR1_SAMCTL0_Pos) ///< 240.5 cycle 731 #define ADC_SMPR1_SAMCTL0_3_5 (0x08U << ADC_SMPR1_SAMCTL0_Pos) ///< 3.5 cycle 732 #define ADC_SMPR1_SAMCTL0_4_5 (0x09U << ADC_SMPR1_SAMCTL0_Pos) ///< 4.5 cycle 733 #define ADC_SMPR1_SAMCTL0_5_5 (0x0AU << ADC_SMPR1_SAMCTL0_Pos) ///< 5.5 cycle 734 #define ADC_SMPR1_SAMCTL0_6_5 (0x0BU << ADC_SMPR1_SAMCTL0_Pos) ///< 6.5 cycle 735 #define ADC_SMPR1_SAMCTL0_7_5 (0x0CU << ADC_SMPR1_SAMCTL0_Pos) ///< 7.5 cycle 736 //////////////////////////////////////////////////////////////////////////////// 737 /// @brief ADC_SMPR2 mode enable Register Bit Definition 738 //////////////////////////////////////////////////////////////////////////////// 739 #define ADC_SMPR2_SAMCTL15_Pos (28) ///< Injection mode external trigger delay sampling 740 #define ADC_SMPR2_SAMCTL15_2_5 (0x00U << ADC_SMPR2_SAMCTL15_Pos) ///< 2.5 cycle 741 #define ADC_SMPR2_SAMCTL15_8_5 (0x01U << ADC_SMPR2_SAMCTL15_Pos) ///< 8.5 cycle 742 #define ADC_SMPR2_SAMCTL15_14_5 (0x02U << ADC_SMPR2_SAMCTL15_Pos) ///< 14.5 cycle 743 #define ADC_SMPR2_SAMCTL15_29_5 (0x03U << ADC_SMPR2_SAMCTL15_Pos) ///< 29.5 cycle 744 #define ADC_SMPR2_SAMCTL15_42_5 (0x04U << ADC_SMPR2_SAMCTL15_Pos) ///< 42.5 cycle 745 #define ADC_SMPR2_SAMCTL15_56_5 (0x05U << ADC_SMPR2_SAMCTL15_Pos) ///< 56.5 cycle 746 #define ADC_SMPR2_SAMCTL15_72_5 (0x06U << ADC_SMPR2_SAMCTL15_Pos) ///< 72.5 cycle 747 #define ADC_SMPR2_SAMCTL15_240_5 (0x07U << ADC_SMPR2_SAMCTL15_Pos) ///< 240.5 cycle 748 #define ADC_SMPR2_SAMCTL15_3_5 (0x08U << ADC_SMPR2_SAMCTL15_Pos) ///< 3.5 cycle 749 #define ADC_SMPR2_SAMCTL15_4_5 (0x09U << ADC_SMPR2_SAMCTL15_Pos) ///< 4.5 cycle 750 #define ADC_SMPR2_SAMCTL15_5_5 (0x0AU << ADC_SMPR2_SAMCTL15_Pos) ///< 5.5 cycle 751 #define ADC_SMPR2_SAMCTL15_6_5 (0x0BU << ADC_SMPR2_SAMCTL15_Pos) ///< 6.5 cycle 752 #define ADC_SMPR2_SAMCTL15_7_5 (0x0CU << ADC_SMPR2_SAMCTL15_Pos) ///< 7.5 cycle 753 #define ADC_SMPR2_SAMCTL14_Pos (24) ///< Injection mode external trigger delay sampling 754 #define ADC_SMPR2_SAMCTL14_2_5 (0x00U << ADC_SMPR2_SAMCTL14_Pos) ///< 2.5 cycle 755 #define ADC_SMPR2_SAMCTL14_8_5 (0x01U << ADC_SMPR2_SAMCTL14_Pos) ///< 8.5 cycle 756 #define ADC_SMPR2_SAMCTL14_14_5 (0x02U << ADC_SMPR2_SAMCTL14_Pos) ///< 14.5 cycle 757 #define ADC_SMPR2_SAMCTL14_29_5 (0x03U << ADC_SMPR2_SAMCTL14_Pos) ///< 29.5 cycle 758 #define ADC_SMPR2_SAMCTL14_42_5 (0x04U << ADC_SMPR2_SAMCTL14_Pos) ///< 42.5 cycle 759 #define ADC_SMPR2_SAMCTL14_56_5 (0x05U << ADC_SMPR2_SAMCTL14_Pos) ///< 56.5 cycle 760 #define ADC_SMPR2_SAMCTL14_72_5 (0x06U << ADC_SMPR2_SAMCTL14_Pos) ///< 72.5 cycle 761 #define ADC_SMPR2_SAMCTL14_240_5 (0x07U << ADC_SMPR2_SAMCTL14_Pos) ///< 240.5 cycle 762 #define ADC_SMPR2_SAMCTL14_3_5 (0x08U << ADC_SMPR2_SAMCTL14_Pos) ///< 3.5 cycle 763 #define ADC_SMPR2_SAMCTL14_4_5 (0x09U << ADC_SMPR2_SAMCTL14_Pos) ///< 4.5 cycle 764 #define ADC_SMPR2_SAMCTL14_5_5 (0x0AU << ADC_SMPR2_SAMCTL14_Pos) ///< 5.5 cycle 765 #define ADC_SMPR2_SAMCTL14_6_5 (0x0BU << ADC_SMPR2_SAMCTL14_Pos) ///< 6.5 cycle 766 #define ADC_SMPR2_SAMCTL14_7_5 (0x0CU << ADC_SMPR2_SAMCTL14_Pos) ///< 7.5 cycle 767 #define ADC_SMPR2_SAMCTL13_Pos (20) ///< Injection mode external trigger delay sampling 768 #define ADC_SMPR2_SAMCTL13_2_5 (0x00U << ADC_SMPR2_SAMCTL13_Pos) ///< 2.5 cycle 769 #define ADC_SMPR2_SAMCTL13_8_5 (0x01U << ADC_SMPR2_SAMCTL13_Pos) ///< 8.5 cycle 770 #define ADC_SMPR2_SAMCTL13_14_5 (0x02U << ADC_SMPR2_SAMCTL13_Pos) ///< 14.5 cycle 771 #define ADC_SMPR2_SAMCTL13_29_5 (0x03U << ADC_SMPR2_SAMCTL13_Pos) ///< 29.5 cycle 772 #define ADC_SMPR2_SAMCTL13_42_5 (0x04U << ADC_SMPR2_SAMCTL13_Pos) ///< 42.5 cycle 773 #define ADC_SMPR2_SAMCTL13_56_5 (0x05U << ADC_SMPR2_SAMCTL13_Pos) ///< 56.5 cycle 774 #define ADC_SMPR2_SAMCTL13_72_5 (0x06U << ADC_SMPR2_SAMCTL13_Pos) ///< 72.5 cycle 775 #define ADC_SMPR2_SAMCTL13_240_5 (0x07U << ADC_SMPR2_SAMCTL13_Pos) ///< 240.5 cycle 776 #define ADC_SMPR2_SAMCTL13_3_5 (0x08U << ADC_SMPR2_SAMCTL13_Pos) ///< 3.5 cycle 777 #define ADC_SMPR2_SAMCTL13_4_5 (0x09U << ADC_SMPR2_SAMCTL13_Pos) ///< 4.5 cycle 778 #define ADC_SMPR2_SAMCTL13_5_5 (0x0AU << ADC_SMPR2_SAMCTL13_Pos) ///< 5.5 cycle 779 #define ADC_SMPR2_SAMCTL13_6_5 (0x0BU << ADC_SMPR2_SAMCTL13_Pos) ///< 6.5 cycle 780 #define ADC_SMPR2_SAMCTL13_7_5 (0x0CU << ADC_SMPR2_SAMCTL13_Pos) ///< 7.5 cycle 781 #define ADC_SMPR2_SAMCTL12_Pos (16) ///< Injection mode external trigger delay sampling 782 #define ADC_SMPR2_SAMCTL12_2_5 (0x00U << ADC_SMPR2_SAMCTL12_Pos) ///< 2.5 cycle 783 #define ADC_SMPR2_SAMCTL12_8_5 (0x01U << ADC_SMPR2_SAMCTL12_Pos) ///< 8.5 cycle 784 #define ADC_SMPR2_SAMCTL12_14_5 (0x02U << ADC_SMPR2_SAMCTL12_Pos) ///< 14.5 cycle 785 #define ADC_SMPR2_SAMCTL12_29_5 (0x03U << ADC_SMPR2_SAMCTL12_Pos) ///< 29.5 cycle 786 #define ADC_SMPR2_SAMCTL12_42_5 (0x04U << ADC_SMPR2_SAMCTL12_Pos) ///< 42.5 cycle 787 #define ADC_SMPR2_SAMCTL12_56_5 (0x05U << ADC_SMPR2_SAMCTL12_Pos) ///< 56.5 cycle 788 #define ADC_SMPR2_SAMCTL12_72_5 (0x06U << ADC_SMPR2_SAMCTL12_Pos) ///< 72.5 cycle 789 #define ADC_SMPR2_SAMCTL12_240_5 (0x07U << ADC_SMPR2_SAMCTL12_Pos) ///< 240.5 cycle 790 #define ADC_SMPR2_SAMCTL12_3_5 (0x08U << ADC_SMPR2_SAMCTL12_Pos) ///< 3.5 cycle 791 #define ADC_SMPR2_SAMCTL12_4_5 (0x09U << ADC_SMPR2_SAMCTL12_Pos) ///< 4.5 cycle 792 #define ADC_SMPR2_SAMCTL12_5_5 (0x0AU << ADC_SMPR2_SAMCTL12_Pos) ///< 5.5 cycle 793 #define ADC_SMPR2_SAMCTL12_6_5 (0x0BU << ADC_SMPR2_SAMCTL12_Pos) ///< 6.5 cycle 794 #define ADC_SMPR2_SAMCTL12_7_5 (0x0CU << ADC_SMPR2_SAMCTL12_Pos) ///< 7.5 cycle 795 #define ADC_SMPR2_SAMCTL11_Pos (12) ///< Injection mode external trigger delay sampling 796 #define ADC_SMPR2_SAMCTL11_2_5 (0x00U << ADC_SMPR2_SAMCTL11_Pos) ///< 2.5 cycle 797 #define ADC_SMPR2_SAMCTL11_8_5 (0x01U << ADC_SMPR2_SAMCTL11_Pos) ///< 8.5 cycle 798 #define ADC_SMPR2_SAMCTL11_14_5 (0x02U << ADC_SMPR2_SAMCTL11_Pos) ///< 14.5 cycle 799 #define ADC_SMPR2_SAMCTL11_29_5 (0x03U << ADC_SMPR2_SAMCTL11_Pos) ///< 29.5 cycle 800 #define ADC_SMPR2_SAMCTL11_42_5 (0x04U << ADC_SMPR2_SAMCTL11_Pos) ///< 42.5 cycle 801 #define ADC_SMPR2_SAMCTL11_56_5 (0x05U << ADC_SMPR2_SAMCTL11_Pos) ///< 56.5 cycle 802 #define ADC_SMPR2_SAMCTL11_72_5 (0x06U << ADC_SMPR2_SAMCTL11_Pos) ///< 72.5 cycle 803 #define ADC_SMPR2_SAMCTL11_240_5 (0x07U << ADC_SMPR2_SAMCTL11_Pos) ///< 240.5 cycle 804 #define ADC_SMPR2_SAMCTL11_3_5 (0x08U << ADC_SMPR2_SAMCTL11_Pos) ///< 3.5 cycle 805 #define ADC_SMPR2_SAMCTL11_4_5 (0x09U << ADC_SMPR2_SAMCTL11_Pos) ///< 4.5 cycle 806 #define ADC_SMPR2_SAMCTL11_5_5 (0x0AU << ADC_SMPR2_SAMCTL11_Pos) ///< 5.5 cycle 807 #define ADC_SMPR2_SAMCTL11_6_5 (0x0BU << ADC_SMPR2_SAMCTL11_Pos) ///< 6.5 cycle 808 #define ADC_SMPR2_SAMCTL11_7_5 (0x0CU << ADC_SMPR2_SAMCTL11_Pos) ///< 7.5 cycle 809 #define ADC_SMPR2_SAMCTL10_Pos (8) ///< Injection mode external trigger delay sampling 810 #define ADC_SMPR2_SAMCTL10_2_5 (0x00U << ADC_SMPR2_SAMCTL10_Pos) ///< 2.5 cycle 811 #define ADC_SMPR2_SAMCTL10_8_5 (0x01U << ADC_SMPR2_SAMCTL10_Pos) ///< 8.5 cycle 812 #define ADC_SMPR2_SAMCTL10_14_5 (0x02U << ADC_SMPR2_SAMCTL10_Pos) ///< 14.5 cycle 813 #define ADC_SMPR2_SAMCTL10_29_5 (0x03U << ADC_SMPR2_SAMCTL10_Pos) ///< 29.5 cycle 814 #define ADC_SMPR2_SAMCTL10_42_5 (0x04U << ADC_SMPR2_SAMCTL10_Pos) ///< 42.5 cycle 815 #define ADC_SMPR2_SAMCTL10_56_5 (0x05U << ADC_SMPR2_SAMCTL10_Pos) ///< 56.5 cycle 816 #define ADC_SMPR2_SAMCTL10_72_5 (0x06U << ADC_SMPR2_SAMCTL10_Pos) ///< 72.5 cycle 817 #define ADC_SMPR2_SAMCTL10_240_5 (0x07U << ADC_SMPR2_SAMCTL10_Pos) ///< 240.5 cycle 818 #define ADC_SMPR2_SAMCTL10_3_5 (0x08U << ADC_SMPR2_SAMCTL10_Pos) ///< 3.5 cycle 819 #define ADC_SMPR2_SAMCTL10_4_5 (0x09U << ADC_SMPR2_SAMCTL10_Pos) ///< 4.5 cycle 820 #define ADC_SMPR2_SAMCTL10_5_5 (0x0AU << ADC_SMPR2_SAMCTL10_Pos) ///< 5.5 cycle 821 #define ADC_SMPR2_SAMCTL10_6_5 (0x0BU << ADC_SMPR2_SAMCTL10_Pos) ///< 6.5 cycle 822 #define ADC_SMPR2_SAMCTL10_7_5 (0x0CU << ADC_SMPR2_SAMCTL10_Pos) ///< 7.5 cycle 823 #define ADC_SMPR2_SAMCTL9_Pos (4) ///< Injection mode external trigger delay sampling 824 #define ADC_SMPR2_SAMCTL9_2_5 (0x00U << ADC_SMPR2_SAMCTL9_Pos) ///< 2.5 cycle 825 #define ADC_SMPR2_SAMCTL9_8_5 (0x01U << ADC_SMPR2_SAMCTL9_Pos) ///< 8.5 cycle 826 #define ADC_SMPR2_SAMCTL9_14_5 (0x02U << ADC_SMPR2_SAMCTL9_Pos) ///< 14.5 cycle 827 #define ADC_SMPR2_SAMCTL9_29_5 (0x03U << ADC_SMPR2_SAMCTL9_Pos) ///< 29.5 cycle 828 #define ADC_SMPR2_SAMCTL9_42_5 (0x04U << ADC_SMPR2_SAMCTL9_Pos) ///< 42.5 cycle 829 #define ADC_SMPR2_SAMCTL9_56_5 (0x05U << ADC_SMPR2_SAMCTL9_Pos) ///< 56.5 cycle 830 #define ADC_SMPR2_SAMCTL9_72_5 (0x06U << ADC_SMPR2_SAMCTL9_Pos) ///< 72.5 cycle 831 #define ADC_SMPR2_SAMCTL9_240_5 (0x07U << ADC_SMPR2_SAMCTL9_Pos) ///< 240.5 cycle 832 #define ADC_SMPR2_SAMCTL9_3_5 (0x08U << ADC_SMPR2_SAMCTL9_Pos) ///< 3.5 cycle 833 #define ADC_SMPR2_SAMCTL9_4_5 (0x09U << ADC_SMPR2_SAMCTL9_Pos) ///< 4.5 cycle 834 #define ADC_SMPR2_SAMCTL9_5_5 (0x0AU << ADC_SMPR2_SAMCTL9_Pos) ///< 5.5 cycle 835 #define ADC_SMPR2_SAMCTL9_6_5 (0x0BU << ADC_SMPR2_SAMCTL9_Pos) ///< 6.5 cycle 836 #define ADC_SMPR2_SAMCTL9_7_5 (0x0CU << ADC_SMPR2_SAMCTL9_Pos) ///< 7.5 cycle 837 #define ADC_SMPR2_SAMCTL8_Pos (0) ///< Injection mode external trigger delay sampling 838 #define ADC_SMPR2_SAMCTL8_2_5 (0x00U << ADC_SMPR2_SAMCTL8_Pos) ///< 2.5 cycle 839 #define ADC_SMPR2_SAMCTL8_8_5 (0x01U << ADC_SMPR2_SAMCTL8_Pos) ///< 8.5 cycle 840 #define ADC_SMPR2_SAMCTL8_14_5 (0x02U << ADC_SMPR2_SAMCTL8_Pos) ///< 14.5 cycle 841 #define ADC_SMPR2_SAMCTL8_29_5 (0x03U << ADC_SMPR2_SAMCTL8_Pos) ///< 29.5 cycle 842 #define ADC_SMPR2_SAMCTL8_42_5 (0x04U << ADC_SMPR2_SAMCTL8_Pos) ///< 42.5 cycle 843 #define ADC_SMPR2_SAMCTL8_56_5 (0x05U << ADC_SMPR2_SAMCTL8_Pos) ///< 56.5 cycle 844 #define ADC_SMPR2_SAMCTL8_72_5 (0x06U << ADC_SMPR2_SAMCTL8_Pos) ///< 72.5 cycle 845 #define ADC_SMPR2_SAMCTL8_240_5 (0x07U << ADC_SMPR2_SAMCTL8_Pos) ///< 240.5 cycle 846 #define ADC_SMPR2_SAMCTL8_3_5 (0x08U << ADC_SMPR2_SAMCTL8_Pos) ///< 3.5 cycle 847 #define ADC_SMPR2_SAMCTL8_4_5 (0x09U << ADC_SMPR2_SAMCTL8_Pos) ///< 4.5 cycle 848 #define ADC_SMPR2_SAMCTL8_5_5 (0x0AU << ADC_SMPR2_SAMCTL8_Pos) ///< 5.5 cycle 849 #define ADC_SMPR2_SAMCTL8_6_5 (0x0BU << ADC_SMPR2_SAMCTL8_Pos) ///< 6.5 cycle 850 #define ADC_SMPR2_SAMCTL8_7_5 (0x0CU << ADC_SMPR2_SAMCTL8_Pos) ///< 7.5 cycle 851 //////////////////////////////////////////////////////////////////////////////// 852 /// @brief ADC_JOFR0 mode enable Register Bit Definition 853 //////////////////////////////////////////////////////////////////////////////// 854 #define ADC_JOFR0_JOFR (0xFFFU) ///< Compensates for the A/D conversion results of the injected channel 0 855 //////////////////////////////////////////////////////////////////////////////// 856 /// @brief ADC_JOFR1 mode enable Register Bit Definition 857 //////////////////////////////////////////////////////////////////////////////// 858 #define ADC_JOFR1_JOFR (0xFFFU) ///< Compensates for the A/D conversion results of the injected channel 1 859 //////////////////////////////////////////////////////////////////////////////// 860 /// @brief ADC_JOFR2 mode enable Register Bit Definition 861 //////////////////////////////////////////////////////////////////////////////// 862 #define ADC_JOFR2_JOFR (0xFFFU) ///< Compensates for the A/D conversion results of the injected channel 2 863 //////////////////////////////////////////////////////////////////////////////// 864 /// @brief ADC_JOFR3 mode enable Register Bit Definition 865 //////////////////////////////////////////////////////////////////////////////// 866 #define ADC_JOFR3_JOFR (0xFFFU) ///< Compensates for the A/D conversion results of the injected channel 3 867 //////////////////////////////////////////////////////////////////////////////// 868 /// @brief ADC_JSQR mode enable Register Bit Definition 869 //////////////////////////////////////////////////////////////////////////////// 870 #define ADC_JSQR_JSQ0_Pos (0) ///< 1st conversion in injected sequence 871 #define ADC_JSQR_JSQ0_0 (0x01U << ADC_JSQR_JSQ0_Pos) ///< Bit 0 872 #define ADC_JSQR_JSQ0_1 (0x02U << ADC_JSQR_JSQ0_Pos) ///< Bit 1 873 #define ADC_JSQR_JSQ0_2 (0x04U << ADC_JSQR_JSQ0_Pos) ///< Bit 2 874 #define ADC_JSQR_JSQ0_3 (0x08U << ADC_JSQR_JSQ0_Pos) ///< Bit 3 875 #define ADC_JSQR_JSQ0_4 (0x10U << ADC_JSQR_JSQ0_Pos) ///< Bit 4 876 #define ADC_JSQR_JSQ1_Pos (5 ) ///< 2st conversion in injected sequence 877 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) ///< Bit 0 878 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) ///< Bit 1 879 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) ///< Bit 2 880 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) ///< Bit 3 881 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) ///< Bit 4 882 #define ADC_JSQR_JSQ2_Pos (10) ///< 3st conversion in injected sequence 883 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) ///< Bit 0 884 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) ///< Bit 1 885 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) ///< Bit 2 886 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) ///< Bit 3 887 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) ///< Bit 4 888 #define ADC_JSQR_JSQ3_Pos (15) ///< 4st conversion in injected sequence 889 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) ///< Bit 0 890 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) ///< Bit 1 891 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) ///< Bit 2 892 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) ///< Bit 3 893 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) ///< Bit 4 894 895 #define ADC_JSQR_JL_Pos (20) ///< Injected Sequence length 896 #define ADC_JSQR_JL_0 (0x01U << ADC_JSQR_JL_Pos) ///< Bit 0 897 #define ADC_JSQR_JL_1 (0x02U << ADC_JSQR_JL_Pos) ///< Bit 1 898 //////////////////////////////////////////////////////////////////////////////// 899 /// @brief ADC_JDATA mode enable Register Bit Definition 900 //////////////////////////////////////////////////////////////////////////////// 901 #define ADC_JDATA_JVALID_Pos (22) 902 #define ADC_JDATA_JVALID (0x01U << ADC_JDATA_JVALID_Pos) ///< Valid flag 903 #define ADC_JDATA_JOVERRUN_Pos (21) 904 #define ADC_JDATA_JOVERRUN (0x01U << ADC_JDATA_JOVERRUN_Pos) ///< Overrun flag 905 #define ADC_JDATA_JCHANNELSEL_Pos (16) 906 #define ADC_JDATA_JCHANNELSEL (0xFFU << ADC_JDATA_JCHANNELSEL_Pos) ///< Channel selection 907 #define ADC_JDATA_JDATA_Pos (0) 908 #define ADC_JDATA_JDATA (0xFFFFU << ADC_JSQR_JSQ0_Pos) ///< Transfer data 909 //////////////////////////////////////////////////////////////////////////////// 910 /// @brief ADC_JDR0 mode enable Register Bit Definition 911 //////////////////////////////////////////////////////////////////////////////// 912 #define ADC_JDR0_JVALID_Pos (22) 913 #define ADC_JDR0_JVALID (0x01U << ADC_JDATA_JVALID_Pos) ///< Valid flag 914 #define ADC_JDR0_JOVERRUN_Pos (21) 915 #define ADC_JDR0_JOVERRUN (0x01U << ADC_JDATA_JOVERRUN_Pos) ///< Overrun flag 916 #define ADC_JDR0_JDATA_Pos (0) 917 #define ADC_JDR0_JDATA (0xFFFFU << ADC_JSQR_JSQ0_Pos) ///< Transfer data 918 //////////////////////////////////////////////////////////////////////////////// 919 /// @brief ADC_JDR1 mode enable Register Bit Definition 920 //////////////////////////////////////////////////////////////////////////////// 921 #define ADC_JDR1_JVALID_Pos (22) 922 #define ADC_JDR1_JVALID (0x01U << ADC_JDATA_JVALID_Pos) ///< Valid flag 923 #define ADC_JDR1_JOVERRUN_Pos (21) 924 #define ADC_JDR1_JOVERRUN (0x01U << ADC_JDATA_JOVERRUN_Pos) ///< Overrun flag 925 #define ADC_JDR1_JDATA_Pos (0) 926 #define ADC_JDR1_JDATA (0xFFFFU << ADC_JSQR_JSQ0_Pos) ///< Transfer data 927 //////////////////////////////////////////////////////////////////////////////// 928 /// @brief ADC_JDR2 mode enable Register Bit Definition 929 //////////////////////////////////////////////////////////////////////////////// 930 #define ADC_JDR2_JVALID_Pos (22) 931 #define ADC_JDR2_JVALID (0x01U << ADC_JDATA_JVALID_Pos) ///< Valid flag 932 #define ADC_JDR2_JOVERRUN_Pos (21) 933 #define ADC_JDR2_JOVERRUN (0x01U << ADC_JDATA_JOVERRUN_Pos) ///< Overrun flag 934 #define ADC_JDR2_JDATA_Pos (0) 935 #define ADC_JDR2_JDATA (0xFFFFU << ADC_JSQR_JSQ0_Pos) ///< Transfer data 936 //////////////////////////////////////////////////////////////////////////////// 937 /// @brief ADC_JDR3 mode enable Register Bit Definition 938 //////////////////////////////////////////////////////////////////////////////// 939 #define ADC_JDR3_JVALID_Pos (22) 940 #define ADC_JDR3_JVALID (0x01U << ADC_JDATA_JVALID_Pos) ///< Valid flag 941 #define ADC_JDR3_JOVERRUN_Pos (21) 942 #define ADC_JDR3_JOVERRUN (0x01U << ADC_JDATA_JOVERRUN_Pos) ///< Overrun flag 943 #define ADC_JDR3_JDATA_Pos (0) 944 #define ADC_JDR3_JDATA (0xFFFFU << ADC_JSQR_JSQ0_Pos) ///< Transfer data 945 /// @} 946 947 /// @} 948 949 /// @} 950 951 //////////////////////////////////////////////////////////////////////////////// 952 #endif 953 //////////////////////////////////////////////////////////////////////////////// 954