1 /** 2 ***************************************************************************** 3 * @file cmem7_adc.h 4 * 5 * @brief CMEM7 ADC header file 6 * 7 * 8 * @version V1.0 9 * @date 3. September 2013 10 * 11 * @note 12 * 13 ***************************************************************************** 14 * @attention 15 * 16 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 17 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 18 * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 19 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 20 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 21 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 22 * 23 * <h2><center>© COPYRIGHT 2013 Capital-micro </center></h2> 24 ***************************************************************************** 25 */ 26 27 #ifndef __CMEM7_ADC_H 28 #define __CMEM7_ADC_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include "cmem7.h" 35 #include "cmem7_conf.h" 36 37 /** @defgroup ADC_PERIPH 38 * @{ 39 */ 40 typedef enum { 41 ADC_PERIPH_1, 42 ADC_PERIPH_2, 43 } ADC_PERIPH; 44 45 #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC_PERIPH_1) || \ 46 ((PERIPH) == ADC_PERIPH_2)) 47 48 /** 49 * @} 50 */ 51 52 /** @defgroup ADC_VSEN 53 * @{ 54 */ 55 #define ADC_VSEN_VDDCORE 1 56 #define ADC_VSEN_VDDIO 2 57 #define ADC_VSEN_VDDIO2 4 58 59 #define IS_ADC_VSEN(VSEN) (((VSEN) == ADC_VSEN_VDDCORE) || \ 60 ((VSEN) == ADC_VSEN_VDDIO) || \ 61 ((VSEN) == ADC_VSEN_VDDIO2)) 62 63 /** 64 * @} 65 */ 66 67 /** @defgroup ADC_PHASE_CTRL 68 * @{ 69 */ 70 #define ADC_PHASE_CTRL_0DEG_RISE_EDGE 0 /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(Rising Edge) */ 71 #define ADC_PHASE_CTRL_90DEG_AHEAD 1 /* ADC-1 90DEG ahead of ADC-2 */ 72 #define ADC_PHASE_CTRL_90DEG_LAG 2 /* ADC-1 90DEG lag of ADC-2 */ 73 #define ADC_PHASE_CTRL_0DEG_FALL_EDGE 3 /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(falling Edge) */ 74 75 #define IS_ADC_PHASE_CTRL(CTRL) (((CTRL) == ADC_PHASE_CTRL_0DEG_RISE_EDGE) || \ 76 ((CTRL) == ADC_PHASE_CTRL_90DEG_AHEAD) || \ 77 ((CTRL) == ADC_PHASE_CTRL_90DEG_LAG) || \ 78 ((CTRL) == ADC_PHASE_CTRL_0DEG_FALL_EDGE)) 79 /** 80 * @} 81 */ 82 83 /** @defgroup ADC_CONVERSION 84 * @{ 85 */ 86 #define ADC_SYSTEM_MODE_SINGLE_CONV 1 87 #define ADC_SYSTEM_MODE_CONTINUOUS_CONV 2 88 89 #define IS_ADC_CONVERSION(CONV) (((CONV) == ADC_SYSTEM_MODE_SINGLE_CONV) || \ 90 ((CONV) == ADC_SYSTEM_MODE_CONTINUOUS_CONV)) 91 92 /** 93 * @} 94 */ 95 96 /** @defgroup ADC_CALIBRATION 97 * @{ 98 */ 99 #define ADC_CALIBRATION_OFFSET 3 100 #define ADC_CALIBRATION_NEGTIVE_GAIN 4 101 #define ADC_CALIBRATION_POSTIVE_GAIN 5 102 103 #define IS_ADC_CALIBRATION(CALIB) (((CALIB) == ADC_CALIBRATION_OFFSET) || \ 104 ((CALIB) == ADC_CALIBRATION_NEGTIVE_GAIN) || \ 105 ((CALIB) == ADC_CALIBRATION_POSTIVE_GAIN)) 106 /** 107 * @} 108 */ 109 110 /** @defgroup ADC_CHANNEL 111 * @{ 112 */ 113 #define ADC_CHANNEL_CALIBRATION 0x0 114 115 /** 116 * @} 117 */ 118 119 /** @defgroup ADC1_CHANNEL 120 * @{ 121 */ 122 #define ADC1_CHANNEL_VIP 0x1 123 #define ADC1_CHANNEL_VSEN 0x2 124 #define ADC1_CHANNEL_VADIO_0 0x4 125 #define ADC1_CHANNEL_VADIO_1 0x8 126 #define ADC1_CHANNEL_VADIO_2 0x10 127 #define ADC1_CHANNEL_VADIO_3 0x20 128 #define ADC1_CHANNEL_VADIO_4 0x40 129 #define ADC1_CHANNEL_VADIO_5 0x80 130 #define ADC1_CHANNEL_ALL 0xFF 131 132 #define IS_ADC1_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) & ~ADC1_CHANNEL_ALL) == 0) 133 /** 134 * @} 135 */ 136 137 /** @defgroup ADC2_CHANNEL 138 * @{ 139 */ 140 #define ADC2_CHANNEL_VIN 0x1 141 #define ADC2_CHANNEL_VTMP 0x2 142 #define ADC2_CHANNEL_VADIO_6 0x4 143 #define ADC2_CHANNEL_VADIO_7 0x8 144 #define ADC2_CHANNEL_VADIO_8 0x10 145 #define ADC2_CHANNEL_VADIO_9 0x20 146 #define ADC2_CHANNEL_VADIO_10 0x40 147 #define ADC2_CHANNEL_VADIO_11 0x80 148 #define ADC2_CHANNEL_ALL 0xFF 149 150 #define IS_ADC2_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) & ~ADC2_CHANNEL_ALL) == 0) 151 /** 152 * @} 153 */ 154 155 /** @defgroup ADC_INT 156 * @{ 157 */ 158 #define ADC1_INT_ALMOST_FULL 0x1 159 #define ADC2_INT_ALMOST_FULL 0x8 160 #define ADC_INT_ALL 0x9 161 162 #define IS_ADC_INT(INT) (((INT) != 0) && (((INT) & ~ADC_INT_ALL) == 0)) 163 /** 164 * @} 165 */ 166 167 /** 168 * @brief ADC collection data structure 169 */ 170 typedef struct { 171 uint8_t channel; /*!< The channel of collected data, is a value of 172 @ref ADC_CHANNEL, @ref ADC1_CHANNEL or @ref ADC2_CHANNEL */ 173 uint16_t data; /*!< collected data */ 174 } ADC_Data; 175 176 /** 177 * @brief ADC initialization structure 178 */ 179 typedef struct 180 { 181 uint8_t ADC_PhaseCtrl; /*!< Phase between ADC1 and ADC2, is a value of @ref ADC_PHASE_CTRL */ 182 uint8_t ADC_VsenSelection; /*!< ADC1 VSEN selection, is a value of @ref ADC_VSEN */ 183 } ADC_InitTypeDef; 184 185 /** 186 * @brief ADC initialization 187 * @note This function should be called at first before any other interfaces. 188 * @param[in] init A pointer to structure ADC_InitTypeDef 189 * @retval None 190 */ 191 void ADC_Init(ADC_InitTypeDef* init); 192 193 /** 194 * @brief Enable or disable ADC. 195 * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH 196 * @param[in] Enable The bit indicates if the specific ADC is enable or not 197 * @retval None 198 */ 199 void ADC_Enable(uint8_t adc, BOOL enable); 200 201 /** 202 * @brief Enable or disable ADC interrupt. 203 * @param[in] Int interrupt mask bits, which can be a combination of @ref ADC_INT 204 * @param[in] Enable The bit indicates if specific interrupts are enable or not 205 * @retval None 206 */ 207 void ADC_EnableInt(uint32_t Int, BOOL enable); 208 209 /** 210 * @brief Check specific interrupts are set or not 211 * @param[in] Int interrupt mask bits, which can be a combination of @ref ADC_INT 212 * @retval BOOL The bit indicates if the specific interrupts are set or not 213 */ 214 BOOL ADC_GetIntStatus(uint32_t Int); 215 216 /** 217 * @brief Clear specific interrupts 218 * @param[in] Int interrupt mask bits, which can be a value of @ref ADC_INT 219 * @retval None 220 */ 221 void ADC_ClearInt(uint32_t Int); 222 223 /** 224 * @brief ADC starts to convert data 225 * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH 226 * @param[in] convMode It should be a value of @ref ADC_CONVERSION 227 * @param[in] channel It should be the value of @ref ADC1_CHANNEL 228 * or @ref ADC2_CHANNEL according to parameter 'adc' 229 * @retval BOOL The bit indicates if the specific ADC starts to convert data 230 */ 231 BOOL ADC_StartConversion(uint8_t adc, uint8_t convMode, uint32_t channel); 232 233 /** 234 * @brief ADC starts to calibrate and produces one sample 235 * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH 236 * @param[in] convMode It should be a value of @ref ADC_CALIBRATION 237 * @retval BOOL The bit indicates if the specific ADC starts to convert data 238 */ 239 BOOL ADC_StartCalibration(uint8_t adc, uint8_t calibration); 240 241 /** 242 * @brief ADC stops conversion or calibration 243 * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH 244 * @retval NULL 245 */ 246 void ADC_Stop(uint8_t adc); 247 248 /** 249 * @brief Check if ADC is busy or not 250 * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH 251 * @retval BOOL The bit indicates if the specific ADC is busy or not 252 */ 253 BOOL ADC_IsBusy(uint8_t adc); 254 255 /** 256 * @brief Read data from ADC 257 * @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH 258 * @param[in] Size Expected data size to be read 259 * @param[out] data A user-allocated buffer to fetch data to be read 260 * @retval uint8_t Actual read data size 261 */ 262 uint8_t ADC_Read(uint8_t adc, uint8_t size, ADC_Data* data); 263 264 #ifdef __cplusplus 265 } 266 #endif 267 268 #endif /*__CMEM7_ADC_H */ 269 270