1 /** 2 ********************************************************************************* 3 * 4 * @file ald_cmu.h 5 * @brief Header file of CMU module driver. 6 * 7 * @version V1.0 8 * @date 30 Jan. 2023 9 * @author AE Team 10 * @note 11 * Change Logs: 12 * Date Author Notes 13 * 30 Jan. 2023 Lisq The first version 14 * 15 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 16 * 17 * SPDX-License-Identifier: Apache-2.0 18 * 19 * Licensed under the Apache License, Version 2.0 (the License); you may 20 * not use this file except in compliance with the License. 21 * You may obtain a copy of the License at 22 * 23 * www.apache.org/licenses/LICENSE-2.0 24 * 25 * Unless required by applicable law or agreed to in writing, software 26 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 27 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28 * See the License for the specific language governing permissions and 29 * limitations under the License. 30 ********************************************************************************** 31 */ 32 33 #ifndef __ALD_CMU_H__ 34 #define __ALD_CMU_H__ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif /* __cplusplus */ 39 40 #include "ald_syscfg.h" 41 42 43 /** @addtogroup ALD 44 * @{ 45 */ 46 47 /** @addtogroup CMU 48 * @{ 49 */ 50 51 /** @defgroup CMU_Public_Macros CMU Public Macros 52 * @{ 53 */ 54 55 /** 56 * @} 57 */ 58 59 60 /** @defgroup CMU_Public_Types CMU Public Types 61 * @{ 62 */ 63 /** 64 * @brief CMU state structure definition 65 */ 66 typedef enum 67 { 68 ALD_CMU_CLOCK_HRC48M = 0x1U, /**< HRC48M */ 69 ALD_CMU_CLOCK_LRC = 0x2U, /**< LRC */ 70 ALD_CMU_CLOCK_HOSC = 0x3U, /**< HOSC */ 71 ALD_CMU_CLOCK_PLL = 0x4U, /**< PLL */ 72 ALD_CMU_CLOCK_HRC4M = 0x5U, /**< HRC4M */ 73 } ald_cmu_clock_t; 74 75 /** 76 * @brief PLL output clock 77 */ 78 typedef enum 79 { 80 ALD_CMU_PLL_OUTPUT_72M = 0x0U, /**< 72MHz */ 81 ALD_CMU_PLL_OUTPUT_64M = 0x2U, /**< 64MHz */ 82 ALD_CMU_PLL_OUTPUT_48M = 0x3U, /**< 48MHz */ 83 } ald_cmu_pll_output_t; 84 85 /** 86 * @brief PLL referance clock 87 */ 88 typedef enum 89 { 90 ALD_CMU_PLL_INPUT_HRC4M = 0x0U, /**< HRC4M */ 91 ALD_CMU_PLL_INPUT_HOSC4M = 0x1U, /**< HOSC4M */ 92 ALD_CMU_PLL_INPUT_HOSC8M = 0x2U, /**< HOSC8M */ 93 ALD_CMU_PLL_INPUT_HOSC16M = 0x3U, /**< HOSC16M */ 94 } ald_cmu_pll_input_t; 95 96 /** 97 * @brief HOSC range 98 */ 99 typedef enum { 100 ALD_CMU_HOSC_1M_2M = 0x0U, /**< 1~2MHz */ 101 ALD_CMU_HOSC_2M_4M = 0x1U, /**< 2~4MHz */ 102 ALD_CMU_HOSC_4M_8M = 0x2U, /**< 4~8MHz */ 103 ALD_CMU_HOSC_8M_16M = 0x3U, /**< 8~16MHz */ 104 ALD_CMU_HOSC_16M_24M = 0x4U, /**< 16~24MHz */ 105 } ald_cmu_hosc_range_t; 106 107 /** 108 * @brief Frequency division select bit 109 */ 110 typedef enum 111 { 112 ALD_CMU_DIV_1 = 0x0U, /**< Division by 1 */ 113 ALD_CMU_DIV_2 = 0x1U, /**< Division by 2 */ 114 ALD_CMU_DIV_4 = 0x2U, /**< Division by 4 */ 115 ALD_CMU_DIV_8 = 0x3U, /**< Division by 8 */ 116 ALD_CMU_DIV_16 = 0x4U, /**< Division by 16 */ 117 ALD_CMU_DIV_32 = 0x5U, /**< Division by 32 */ 118 ALD_CMU_DIV_64 = 0x6U, /**< Division by 64 */ 119 ALD_CMU_DIV_128 = 0x7U, /**< Division by 128 */ 120 ALD_CMU_DIV_256 = 0x8U, /**< Division by 256 */ 121 ALD_CMU_DIV_512 = 0x9U, /**< Division by 512 */ 122 ALD_CMU_DIV_1024 = 0xAU, /**< Division by 1024 */ 123 ALD_CMU_DIV_2048 = 0xBU, /**< Division by 2048 */ 124 ALD_CMU_DIV_4096 = 0xCU, /**< Division by 4096 */ 125 } ald_cmu_div_t; 126 127 /** 128 * @brief BUZZ frequency division 129 */ 130 typedef enum { 131 ALD_CMU_BUZZ_DIV_2 = 0x0U, /**< Division by 2 */ 132 ALD_CMU_BUZZ_DIV_4 = 0x1U, /**< Division by 4 */ 133 ALD_CMU_BUZZ_DIV_8 = 0x2U, /**< Division by 8 */ 134 ALD_CMU_BUZZ_DIV_16 = 0x3U, /**< Division by 16 */ 135 ALD_CMU_BUZZ_DIV_32 = 0x4U, /**< Division by 32 */ 136 ALD_CMU_BUZZ_DIV_64 = 0x5U, /**< Division by 64 */ 137 ALD_CMU_BUZZ_DIV_128 = 0x6U, /**< Division by 128 */ 138 ALD_CMU_BUZZ_DIV_256 = 0x7U, /**< Division by 256 */ 139 } ald_cmu_buzz_div_t; 140 141 /** 142 * @brief Safe clock source type 143 */ 144 typedef enum { 145 ALD_CMU_SAFE_CLK_PLL = 0x0U, /**< PLL */ 146 } ald_cmu_clock_safe_type_t; 147 148 /** 149 * @brief Bus type 150 */ 151 typedef enum 152 { 153 ALD_CMU_SYS = 0x1U, /**< SYS bus */ 154 ALD_CMU_PCLK = 0x2U, /**< APB bus */ 155 } ald_cmu_bus_t; 156 157 /** 158 * @brief Output frequency division 159 */ 160 typedef enum { 161 ALD_CMU_OUTPUT_DIV_1 = 0x0U, /**< Division by 1 */ 162 ALD_CMU_OUTPUT_DIV_2 = 0x1U, /**< Division by 2 */ 163 ALD_CMU_OUTPUT_DIV_4 = 0x2U, /**< Division by 4 */ 164 ALD_CMU_OUTPUT_DIV_8 = 0x3U, /**< Division by 8 */ 165 ALD_CMU_OUTPUT_DIV_16 = 0x4U, /**< Division by 16 */ 166 ALD_CMU_OUTPUT_DIV_32 = 0x5U, /**< Division by 32 */ 167 ALD_CMU_OUTPUT_DIV_64 = 0x6U, /**< Division by 64 */ 168 ALD_CMU_OUTPUT_DIV_128 = 0x7U, /**< Division by 128 */ 169 } ald_cmu_output_high_div_t; 170 171 /** 172 * @brief Output high clock select 173 */ 174 typedef enum { 175 ALD_CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U, /**< Select HOSC */ 176 ALD_CMU_OUTPUT_HIGH_SEL_HOSM = 0x1U, /**< Select HOSM */ 177 ALD_CMU_OUTPUT_HIGH_SEL_HRC4M = 0x2U, /**< Select HRC4M */ 178 ALD_CMU_OUTPUT_HIGH_SEL_LRC = 0x3U, /**< Select LRC */ 179 ALD_CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x4U, /**< Select SYSCLK */ 180 ALD_CMU_OUTPUT_HIGH_SEL_HOSC32K = 0x5U, /**< Select HOSC32K */ 181 ALD_CMU_OUTPUT_HIGH_SEL_HRC48M = 0x6U, /**< Select HRC48M */ 182 ALD_CMU_OUTPUT_HIGH_SEL_PLL = 0x7U, /**< Select PLL */ 183 } ald_cmu_output_high_sel_t; 184 185 /** 186 * @brief Output low clock select 187 */ 188 typedef enum { 189 ALD_CMU_OUTPUT_LOW_SEL_LRC = 0x0U, /**< Select LRC */ 190 ALD_CMU_OUTPUT_LOW_SEL_BUZZ = 0x1U, /**< Select BUZZ */ 191 } ald_cmu_output_low_sel_t; 192 193 /** 194 * @brief Peripheral clock enable/disable 195 */ 196 typedef enum { 197 ALD_CMU_PERH_GPIO = (1U << 0), /**< GPIO */ 198 ALD_CMU_PERH_CRC = (1U << 1), /**< CRC */ 199 ALD_CMU_PERH_DMA = (1U << 2), /**< DMA */ 200 ALD_CMU_PERH_PIS = (1U << 5), /**< PIS */ 201 ALD_CMU_PERH_USB = (1U << 6), /**< USB */ 202 ALD_CMU_PERH_CSU = (1U << 7), /**< CSU */ 203 ALD_CMU_PERH_AD16C4T0 = (1U << 0) | (1U << 27), /**< AD16C4T0 */ 204 ALD_CMU_PERH_BS16T0 = (1U << 1) | (1U << 27), /**< BS16T0 */ 205 ALD_CMU_PERH_GP16C4T0 = (1U << 2) | (1U << 27), /**< CP16C4T0 */ 206 ALD_CMU_PERH_GP16C4T1 = (1U << 3) | (1U << 27), /**< GP16C4T1 */ 207 ALD_CMU_PERH_GP16C4T2 = (1U << 4) | (1U << 27), /**< GP16C4T2 */ 208 ALD_CMU_PERH_EUART0 = (1U << 8) | (1U << 27), /**< EUART0 */ 209 ALD_CMU_PERH_EUART1 = (1U << 9) | (1U << 27), /**< EUART1 */ 210 ALD_CMU_PERH_CUART0 = (1U << 12) | (1U << 27), /**< CUART0 */ 211 ALD_CMU_PERH_CUART1 = (1U << 13) | (1U << 27), /**< CUART1 */ 212 ALD_CMU_PERH_CUART2 = (1U << 14) | (1U << 27), /**< CUART2 */ 213 ALD_CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ 214 ALD_CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ 215 ALD_CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ 216 ALD_CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ 217 ALD_CMU_PERH_WWDT = (1U << 22) | (1U << 27), /**< WWDT */ 218 ALD_CMU_PERH_IWDT = (1U << 23) | (1U << 27), /**< IWDT */ 219 ALD_CMU_PERH_DBGC = (1U << 24) | (1U << 27), /**< DBGC */ 220 ALD_CMU_PERH_ADC = (1U << 25) | (1U << 27), /**< ADC */ 221 ALD_CMU_PERH_ALL = (0x7FFFFFFFU), /**< ALL */ 222 } ald_cmu_perh_t; 223 224 /** 225 * @brief CMU interrupt type 226 */ 227 typedef enum { 228 ALD_CMU_HOSC_STOP = 0x0U, /**< HOSC STOP INTERRUPT */ 229 ALD_CMU_PLL_UNLOCK = 0x1U, /**< PLL UNLOCK INTERRUPT */ 230 ALD_CMU_HOSC_START = 0x2U, /**< HOSC START INTERRUPT */ 231 } ald_cmu_security_t; 232 233 /** 234 * @brief CMU clock state type 235 */ 236 typedef enum { 237 ALD_CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ 238 ALD_CMU_CLOCK_STATE_PLLACT = (1U << 1), /**< PLL active */ 239 ALD_CMU_CLOCK_STATE_HRC4MACT = (1U << 2), /**< HRC4M active */ 240 ALD_CMU_CLOCK_STATE_HRC48MACT = (1U << 3), /**< HRC48M active */ 241 ALD_CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ 242 ALD_CMU_CLOCK_STATE_HRC4MRDY = (1U << 17), /**< HRC4M ready */ 243 ALD_CMU_CLOCK_STATE_HRC48MRDY = (1U << 18), /**< HRC48M ready */ 244 ALD_CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ 245 ALD_CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ 246 } ald_cmu_clock_state_t; 247 248 /** 249 * @} 250 */ 251 252 /** 253 * @defgroup CMU_Private_Macros CMU Private Macros 254 * @{ 255 */ 256 #define IS_CMU_CLOCK(x) (((x) == ALD_CMU_CLOCK_HRC48M) || \ 257 ((x) == ALD_CMU_CLOCK_LRC) || \ 258 ((x) == ALD_CMU_CLOCK_HOSC) || \ 259 ((x) == ALD_CMU_CLOCK_PLL) || \ 260 ((x) == ALD_CMU_CLOCK_HRC4M)) 261 #define IS_CMU_PLL_INPUT(x) (((x) == ALD_CMU_PLL_INPUT_HRC4M) || \ 262 ((x) == ALD_CMU_PLL_INPUT_HOSC4M) || \ 263 ((x) == ALD_CMU_PLL_INPUT_HOSC8M) || \ 264 ((x) == ALD_CMU_PLL_INPUT_HOSC16M)) 265 #define IS_CMU_PLL_OUTPUT(x) (((x) == ALD_CMU_PLL_OUTPUT_48M) || \ 266 ((x) == ALD_CMU_PLL_OUTPUT_64M) || \ 267 ((x) == ALD_CMU_PLL_OUTPUT_72M)) 268 #define IS_CMU_HOSC_RANGE(x) (((x) == ALD_CMU_HOSC_1M_2M) || \ 269 ((x) == ALD_CMU_HOSC_2M_4M) || \ 270 ((x) == ALD_CMU_HOSC_4M_8M) || \ 271 ((x) == ALD_CMU_HOSC_8M_16M) || \ 272 ((x) == ALD_CMU_HOSC_16M_24M)) 273 #define IS_CMU_DIV(x) (((x) == ALD_CMU_DIV_1) || \ 274 ((x) == ALD_CMU_DIV_2) || \ 275 ((x) == ALD_CMU_DIV_4) || \ 276 ((x) == ALD_CMU_DIV_8) || \ 277 ((x) == ALD_CMU_DIV_16) || \ 278 ((x) == ALD_CMU_DIV_32) || \ 279 ((x) == ALD_CMU_DIV_64) || \ 280 ((x) == ALD_CMU_DIV_128) || \ 281 ((x) == ALD_CMU_DIV_256) || \ 282 ((x) == ALD_CMU_DIV_512) || \ 283 ((x) == ALD_CMU_DIV_1024) || \ 284 ((x) == ALD_CMU_DIV_2048) || \ 285 ((x) == ALD_CMU_DIV_4096)) 286 #define IS_CMU_BUS(x) (((x) == ALD_CMU_PCLK) || \ 287 ((x) == ALD_CMU_SYS)) 288 #define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == ALD_CMU_OUTPUT_HIGH_SEL_HOSC) || \ 289 ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HOSM) || \ 290 ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HRC4M) || \ 291 ((x) == ALD_CMU_OUTPUT_HIGH_SEL_LRC) || \ 292 ((x) == ALD_CMU_OUTPUT_HIGH_SEL_SYSCLK) || \ 293 ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HOSC32K) || \ 294 ((x) == ALD_CMU_OUTPUT_HIGH_SEL_HRC48M) || \ 295 ((x) == ALD_CMU_OUTPUT_HIGH_SEL_PLL)) 296 #define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == ALD_CMU_OUTPUT_DIV_1) || \ 297 ((x) == ALD_CMU_OUTPUT_DIV_2) || \ 298 ((x) == ALD_CMU_OUTPUT_DIV_4) || \ 299 ((x) == ALD_CMU_OUTPUT_DIV_8) || \ 300 ((x) == ALD_CMU_OUTPUT_DIV_16) || \ 301 ((x) == ALD_CMU_OUTPUT_DIV_32) || \ 302 ((x) == ALD_CMU_OUTPUT_DIV_64) || \ 303 ((x) == ALD_CMU_OUTPUT_DIV_128)) 304 #define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == ALD_CMU_OUTPUT_LOW_SEL_LRC) || \ 305 ((x) == ALD_CMU_OUTPUT_LOW_SEL_BUZZ)) 306 #define IS_CMU_SAFE_CLOCK_TYPE(x) (((x) == ALD_CMU_SAFE_CLK_PLL)) 307 #define IS_CMU_BUZZ_DIV(x) (((x) == ALD_CMU_BUZZ_DIV_2) || \ 308 ((x) == ALD_CMU_BUZZ_DIV_4) || \ 309 ((x) == ALD_CMU_BUZZ_DIV_8) || \ 310 ((x) == ALD_CMU_BUZZ_DIV_16) || \ 311 ((x) == ALD_CMU_BUZZ_DIV_32) || \ 312 ((x) == ALD_CMU_BUZZ_DIV_64) || \ 313 ((x) == ALD_CMU_BUZZ_DIV_128) || \ 314 ((x) == ALD_CMU_BUZZ_DIV_256)) 315 #define IS_CMU_PERH(x) (((x) == ALD_CMU_PERH_GPIO) || \ 316 ((x) == ALD_CMU_PERH_CRC) || \ 317 ((x) == ALD_CMU_PERH_DMA) || \ 318 ((x) == ALD_CMU_PERH_PIS) || \ 319 ((x) == ALD_CMU_PERH_USB) || \ 320 ((x) == ALD_CMU_PERH_CSU) || \ 321 ((x) == ALD_CMU_PERH_AD16C4T0) || \ 322 ((x) == ALD_CMU_PERH_BS16T0) || \ 323 ((x) == ALD_CMU_PERH_GP16C4T0) || \ 324 ((x) == ALD_CMU_PERH_GP16C4T1) || \ 325 ((x) == ALD_CMU_PERH_GP16C4T2) || \ 326 ((x) == ALD_CMU_PERH_EUART0) || \ 327 ((x) == ALD_CMU_PERH_EUART1) || \ 328 ((x) == ALD_CMU_PERH_CUART0) || \ 329 ((x) == ALD_CMU_PERH_CUART1) || \ 330 ((x) == ALD_CMU_PERH_CUART2) || \ 331 ((x) == ALD_CMU_PERH_SPI0) || \ 332 ((x) == ALD_CMU_PERH_SPI1) || \ 333 ((x) == ALD_CMU_PERH_I2C0) || \ 334 ((x) == ALD_CMU_PERH_I2C1) || \ 335 ((x) == ALD_CMU_PERH_WWDT) || \ 336 ((x) == ALD_CMU_PERH_IWDT) || \ 337 ((x) == ALD_CMU_PERH_DBGC) || \ 338 ((x) == ALD_CMU_PERH_ADC) || \ 339 ((x) == ALD_CMU_PERH_ALL)) 340 #define IS_CMU_CLOCK_STATE(x) (((x) == ALD_CMU_CLOCK_STATE_HOSCACT) || \ 341 ((x) == ALD_CMU_CLOCK_STATE_PLLACT) || \ 342 ((x) == ALD_CMU_CLOCK_STATE_HRC4MACT) || \ 343 ((x) == ALD_CMU_CLOCK_STATE_HRC48MACT) || \ 344 ((x) == ALD_CMU_CLOCK_STATE_HOSCRDY) || \ 345 ((x) == ALD_CMU_CLOCK_STATE_HRC4MRDY) || \ 346 ((x) == ALD_CMU_CLOCK_STATE_HRC48MRDY) || \ 347 ((x) == ALD_CMU_CLOCK_STATE_LRCRDY) || \ 348 ((x) == ALD_CMU_CLOCK_STATE_PLLRDY)) 349 /** 350 * @} 351 */ 352 353 /** @addtogroup CMU_Public_Functions 354 * @{ 355 */ 356 /** @addtogroup CMU_Public_Functions_Group1 357 * @{ 358 */ 359 /* System clock configure */ 360 ald_status_t ald_cmu_clock_config_default(void); 361 ald_status_t ald_cmu_clock_config(ald_cmu_clock_t clk, uint32_t clock); 362 void ald_cmu_pll_config(ald_cmu_pll_input_t input, ald_cmu_pll_output_t output); 363 uint32_t ald_cmu_get_clock(void); 364 /** 365 * @} 366 */ 367 368 /** @addtogroup CMU_Public_Functions_Group2 369 * @{ 370 */ 371 /* BUS division control */ 372 void ald_cmu_div_config(ald_cmu_bus_t bus, ald_cmu_div_t div); 373 uint32_t ald_cmu_get_sys_clock(void); 374 uint32_t ald_cmu_get_pclk_clock(void); 375 /** 376 * @} 377 */ 378 379 /** @addtogroup CMU_Public_Functions_Group3 380 * @{ 381 */ 382 /* Clock safe configure */ 383 void ald_cmu_hosc_safe_config(ald_cmu_hosc_range_t clock, type_func_t status); 384 void ald_cmu_pll_safe_config(type_func_t status); 385 uint32_t ald_cmu_pulmcr_current_clock_source_get(void); 386 flag_status_t ald_cmu_get_clock_state(ald_cmu_clock_state_t sr); 387 void ald_cmu_irq_handler(void); 388 void ald_cmu_irq_cbk(ald_cmu_security_t se); 389 /** 390 * @} 391 */ 392 393 /** @addtogroup CMU_Public_Functions_Group4 394 * @{ 395 */ 396 /* Clock output configure */ 397 void ald_cmu_output_high_clock_config(ald_cmu_output_high_sel_t sel, 398 ald_cmu_output_high_div_t div, type_func_t status); 399 void ald_cmu_output_low_clock_config(ald_cmu_output_low_sel_t sel, type_func_t status); 400 /** 401 * @} 402 */ 403 404 /** @addtogroup CMU_Public_Functions_Group5 405 * @{ 406 */ 407 /* Peripheral Clock configure */ 408 void ald_cmu_buzz_config(ald_cmu_buzz_div_t div, uint16_t dat, type_func_t status); 409 void ald_cmu_perh_clock_config(ald_cmu_perh_t perh, type_func_t status); 410 /** 411 * @} 412 */ 413 /** 414 * @} 415 */ 416 417 /** 418 * @} 419 */ 420 421 /** 422 * @} 423 */ 424 #ifdef __cplusplus 425 } 426 #endif /* __cplusplus */ 427 428 #endif /* __ALD_CMU_H__ */ 429