1 /** 2 ********************************************************************************* 3 * 4 * @file ald_i2c.h 5 * @brief Header file of I2C driver 6 * 7 * @version V1.0 8 * @date 24 Feb. 2023 9 * @author AE Team 10 * @note 11 * Change Logs: 12 * Date Author Notes 13 * 24 Feb. 2023 Lisq The first version 14 * 15 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 16 * 17 * SPDX-License-Identifier: Apache-2.0 18 * 19 * Licensed under the Apache License, Version 2.0 (the License); you may 20 * not use this file except in compliance with the License. 21 * You may obtain a copy of the License at 22 * 23 * www.apache.org/licenses/LICENSE-2.0 24 * 25 * Unless required by applicable law or agreed to in writing, software 26 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 27 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28 * See the License for the specific language governing permissions and 29 * limitations under the License. 30 ********************************************************************************** 31 */ 32 33 #ifndef __ALD_I2C_H__ 34 #define __ALD_I2C_H__ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif /* __cplusplus */ 39 40 #include <string.h> 41 #include "ald_cmu.h" 42 #include "ald_dma.h" 43 44 /** @addtogroup ES32VF2264_ALD 45 * @{ 46 */ 47 48 /** @addtogroup I2C 49 * @{ 50 */ 51 52 /** @defgroup I2C_Public_Types I2C Public Types 53 * @{ 54 */ 55 /** 56 * @brief I2C Error Code 57 */ 58 typedef enum { 59 ALD_I2C_ERROR_NONE = 0x0U, /**< No error */ 60 ALD_I2C_ERROR_BERR = 0x1U, /**< Berr error */ 61 ALD_I2C_ERROR_ARLO = 0x2U, /**< Arlo error */ 62 ALD_I2C_ERROR_RUD = 0x4U, /**< Rx underflow error */ 63 ALD_I2C_ERROR_AF = 0x8U, /**< Af error */ 64 ALD_I2C_ERROR_ROV = 0x10U, /**< Rx overflow error */ 65 ALD_I2C_ERROR_RF = 0x20U, /**< Rx full error */ 66 ALD_I2C_ERROR_TUD = 0x40U, /**< Tx underflow error */ 67 ALD_I2C_ERROR_TOV = 0x80U, /**< Tx overflow error */ 68 ALD_I2C_ERROR_TE = 0x100U, /**< Tx empty error */ 69 ALD_I2C_ERROR_DMA = 0x200U, /**< Dma error */ 70 ALD_I2C_ERROR_TIMEOUT = 0x400U, /**< Timeout error */ 71 } ald_i2c_error_t; 72 73 /** 74 * @brief I2C state structure definition 75 */ 76 typedef enum { 77 ALD_I2C_STATE_RESET = 0x0U, /**< Peripheral is not yet Initialized */ 78 ALD_I2C_STATE_READY = 0x20U, /**< Peripheral Initialized and ready for use */ 79 ALD_I2C_STATE_BUSY = 0x24U, /**< An internal process is ongoing */ 80 ALD_I2C_STATE_BUSY_TX = 0x21U, /**< Data Transmission process is ongoing */ 81 ALD_I2C_STATE_BUSY_RX = 0x22U, /**< Data Reception process is ongoing */ 82 83 ALD_I2C_STATE_LISTEN = 0x28U, /**< Address Listen */ 84 ALD_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /**< Address Listen and Data Transmission */ 85 ALD_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /**< Address Listen and Data Receive */ 86 87 ALD_I2C_STATE_ABORT = 0x60U, /**< Abort user request */ 88 ALD_I2C_STATE_TIMEOUT = 0xA0U, /**< timeout state */ 89 ALD_I2C_STATE_ERROR = 0xE0U, /**< Error */ 90 } ald_i2c_state_t; 91 92 /** 93 * @brief I2C Addressing Mode 94 */ 95 typedef enum { 96 ALD_I2C_ADDR_7BIT = 0x0U, /**< 7 bit address */ 97 ALD_I2C_ADDR_10BIT = 0x1U, /**< 10 bit address */ 98 } ald_i2c_addr_t; 99 100 /** 101 * @brief I2C Dual Addressing Mode 102 */ 103 typedef enum { 104 ALD_I2C_DUALADDR_DISABLE = 0x0U, /**< dual address is disable */ 105 ALD_I2C_DUALADDR_ENABLE = 0x1U, /**< dual address is enable */ 106 } ald_i2c_dual_addr_t; 107 108 /** 109 * @brief I2C General Call Addressing mode 110 */ 111 typedef enum { 112 ALD_I2C_GENERALCALL_DISABLE = 0x0U, /**< general call address is disable */ 113 ALD_I2C_GENERALCALL_ENABLE = 0x1U, /**< general call address is enable */ 114 } ald_i2c_general_addr_t; 115 116 /** 117 * @brief I2C Nostretch Mode 118 */ 119 typedef enum { 120 ALD_I2C_NOSTRETCH_DISABLE = 0x0U, /**< Nostretch disable */ 121 ALD_I2C_NOSTRETCH_ENABLE = 0x1U, /**< Nostretch enable */ 122 } ald_i2c_nostretch_t; 123 124 /** 125 * @brief I2C Memory Address Size 126 */ 127 typedef enum { 128 ALD_I2C_MEMADD_SIZE_8BIT = 0x8U, /**< 8 bit memory address size */ 129 ALD_I2C_MEMADD_SIZE_16BIT = 0x10U, /**< 10 bit memory address size */ 130 } ald_i2c_addr_size_t; 131 132 /** 133 * @brief I2C mode structure definition 134 */ 135 typedef enum { 136 ALD_I2C_MODE_NONE = 0x0U, /**< No I2C communication on going */ 137 ALD_I2C_MODE_MASTER = 0x10U, /**< I2C communication is in Master mode */ 138 ALD_I2C_MODE_SLAVE = 0x20U, /**< I2C communication is in Slave mode */ 139 ALD_I2C_MODE_MEM = 0x40U, /**< I2C communication is in Memory mode */ 140 } ald_i2c_mode_t; 141 142 /** 143 * @brief I2C Clock 144 */ 145 typedef enum { 146 ALD_I2C_STANDARD_MODE_MAX_CLK = 100000U, /**< Standard mode clock */ 147 ALD_I2C_FAST_MODE_MAX_CLK = 400000U, /**< Fast mode clock */ 148 ALD_I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000U, /**< Extreme mode clock */ 149 } ald_i2c_clock_t; 150 151 /** 152 * @brief I2C OAR2 Register 153 */ 154 typedef enum { 155 ALD_I2C_OAR2_ENDUAL = (1U << 0), /**< ENDUAL BIT */ 156 ALD_I2C_OAR2_ADD2 = (1U << 1) /**< ADD2 BIT */ 157 } ald_i2c_oar2_t; 158 159 /** 160 * @brief I2C CON1 Register 161 */ 162 typedef enum { 163 ALD_I2C_CON1_PE = (1U << 0), /**< Peripheral enable BIT */ 164 ALD_I2C_CON1_TXDMA = (1U << 14), /**< Transmit DMA BIT */ 165 ALD_I2C_CON1_RXDMA = (1U << 15), /**< Receive DMA BIT */ 166 ALD_I2C_CON1_SBC = (1U << 16), /**< Receive DMA BIT */ 167 ALD_I2C_CON1_NOSTRETCH = (1U << 17), /**< Slave bytes control BIT */ 168 ALD_I2C_CON1_GCEN = (1U << 19), /**< General call BIT */ 169 ALD_I2C_CON1_SMBHEN = (1U << 20), /**< SMBus slave device enable BIT */ 170 ALD_I2C_CON1_SMBDEN = (1U << 21), /**< SMBus master device enable BIT */ 171 ALD_I2C_CON1_ALERTEN = (1U << 22), /**< SMBus alert device enable BIT */ 172 ALD_I2C_CON1_PECEN = (1U << 23), /**< PEC enable BIT */ 173 } ald_i2c_con1_t; 174 175 /** 176 * @brief I2C CON2 Register 177 */ 178 typedef enum { 179 ALD_I2C_CON2_RD_WRN = (1U << 10), /**< Master R/W control BIT */ 180 ALD_I2C_CON2_ADD10 = (1U << 11), /**< 10bit address control BIT */ 181 ALD_I2C_CON2_HEAD10R = (1U << 12), /**< 10bit address master Receive control BIT */ 182 ALD_I2C_CON2_START = (1U << 13), /**< Master start singal control BIT */ 183 ALD_I2C_CON2_STOP = (1U << 14), /**< Master stop singal control BIT */ 184 ALD_I2C_CON2_NACK = (1U << 15), /**< Master Nack control BIT */ 185 ALD_I2C_CON2_RELOAD = (1U << 24), /**< Master communication reload control BIT */ 186 ALD_I2C_CON2_AUTOEND = (1U << 25), /**< Master Autoend control BIT */ 187 ALD_I2C_CON2_PECBYTE = (1U << 26), /**< PEC control BIT */ 188 ALD_I2C_CON2_HOLDACK = (1U << 28), /**< Hold ack control BIT */ 189 } ald_i2c_con2_t; 190 191 /** 192 * @brief I2C ADDR1 Register 193 */ 194 typedef enum { 195 ALD_I2C_OA1MODE = (1U << 10), /**< Addr1 bits choose BIT */ 196 ALD_I2C_OA1EN = (1U << 15), /**< Addr1 enable BIT */ 197 } ald_i2c_addr1_t; 198 199 /** 200 * @brief I2C ADDR2 Register 201 */ 202 typedef enum { 203 ALD_I2C_OA2EN = (1U << 15), /**< Addr2 enable BIT */ 204 } ald_i2c_addr2_t; 205 206 /** 207 * @brief I2C TIMEOUTR Register 208 */ 209 typedef enum { 210 ALD_I2C_TIMEOUTR_TIDLE = (1U << 12), /**< SCL idle check enable BIT */ 211 ALD_I2C_TIMEOUTR_TIMEOUTEN = (1U << 15), /**< Timeout enable BIT */ 212 } ald_i2c_timoutr_t; 213 214 /** 215 * @brief I2C peripherals module 216 */ 217 typedef enum { 218 ALD_I2C_MODULE_MASTER = (1U << 0), /**< Master module */ 219 ALD_I2C_MODULE_SLAVE = (1U << 1) /**< Slave module */ 220 } ald_i2c_module_t; 221 222 /** 223 * @brief I2C STAT Register 224 */ 225 typedef enum { 226 ALD_I2C_STAT_TXE = (1U << 0), /**< Transmit empty flag */ 227 ALD_I2C_STAT_TXOV = (1U << 2), /**< Transmit overrun flag */ 228 ALD_I2C_STAT_TXUD = (1U << 3), /**< Transmit underrun flag */ 229 ALD_I2C_STAT_RXNE = (1U << 5), /**< Receive not empty flag */ 230 ALD_I2C_STAT_RXOV = (1U << 7), /**< Receive overrun flag */ 231 ALD_I2C_STAT_RXUD = (1U << 8), /**< Receive underrun flag */ 232 ALD_I2C_STAT_TC = (1U << 10), /**< Transmit completed flag */ 233 ALD_I2C_STAT_TCR = (1U << 11), /**< Transmit and reload completed flag */ 234 ALD_I2C_STAT_BUSY = (1U << 15), /**< Bus status busy flag */ 235 ALD_I2C_STAT_DIR = (1U << 16), /**< Slave R/W flag */ 236 } ald_i2c_stat_t; 237 238 /** 239 * @brief Interrupt Configuration Definition 240 */ 241 typedef enum { 242 ALD_I2C_IT_TXE = (1U << 0), /**< Transmit empty interrupt */ 243 ALD_I2C_IT_TXOV = (1U << 2), /**< Transmit overrun interrupt */ 244 ALD_I2C_IT_TXUD = (1U << 3), /**< Transmit underrun interrupt */ 245 ALD_I2C_IT_RXNE = (1U << 5), /**< Receive not empty interrupt */ 246 ALD_I2C_IT_RXOV = (1U << 7), /**< Receive overrun interrupt */ 247 ALD_I2C_IT_RXUD = (1U << 8), /**< Receive underrun interrupt */ 248 ALD_I2C_IT_TC = (1U << 10), /**< Transmit completed interrupt */ 249 ALD_I2C_IT_TCR = (1U << 11), /**< Transmit and reload completed interrupt */ 250 ALD_I2C_IT_ADDR = (1U << 12), /**< Address matching interrupt */ 251 ALD_I2C_IT_NACK = (1U << 13), /**< NACK interrupt */ 252 ALD_I2C_IT_STOP = (1U << 14), /**< Stop detection interrupt */ 253 ALD_I2C_IT_BERR = (1U << 16), /**< Bus error interrupt */ 254 ALD_I2C_IT_ARLO = (1U << 17), /**< Arbitration loss interrupt */ 255 ALD_I2C_IT_PECE = (1U << 18), /**< PEC error interrupt */ 256 ALD_I2C_IT_TOUT = (1U << 19), /**< Timeout interrupt */ 257 ALD_I2C_IT_ALERT = (1U << 20), /**< SMBus Alert interrupt */ 258 } ald_i2c_interrupt_t; 259 260 /** 261 * @brief I2C TRISE Register 262 */ 263 typedef enum { 264 ALD_I2C_TRISE_TRISE = 0x3FU, /**< TRISE BITS */ 265 } ald_i2c_trise_t; 266 267 /** 268 * @brief I2C Configuration Structure definition 269 */ 270 typedef struct { 271 ald_i2c_module_t module; /**< Specifies the communication module */ 272 uint32_t clk_speed; /**< Specifies the clock frequency */ 273 uint32_t own_addr1; /**< Specifies the first device own address */ 274 ald_i2c_addr_t addr_mode; /**< Specifies addressing mode */ 275 ald_i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ 276 uint32_t own_addr2; /**< Specifies the second device own address */ 277 ald_i2c_general_addr_t general_call;/**< Specifies if general call mode is selected */ 278 ald_i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ 279 } ald_i2c_init_t; 280 281 /** 282 * @brief I2C handle Structure definition 283 */ 284 typedef struct ald_i2c_handle_s { 285 I2C_TypeDef *perh; /**< I2C registers base address */ 286 ald_i2c_init_t init; /**< I2C communication parameters */ 287 uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ 288 uint16_t xfer_size; /**< I2C transfer size */ 289 __IO uint16_t xfer_count; /**< I2C transfer counter */ 290 291 __IO uint32_t xfer_opt; /**< I2C transfer options */ 292 __IO uint32_t pre_state; /**< I2C previous communication state */ 293 294 ald_dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ 295 ald_dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ 296 297 lock_state_t lock; /**< I2C locking object */ 298 __IO ald_i2c_state_t state; /**< I2C communication state */ 299 __IO ald_i2c_mode_t mode; /**< I2C communication mode */ 300 __IO uint32_t error_code; /**< I2C Error code */ 301 302 void (*addr_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Call Slave Addr callback */ 303 void (*listen_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Listen callback */ 304 305 void (*master_tx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Master Tx completed callback */ 306 void (*master_rx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Master Rx completed callback */ 307 void (*slave_tx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Slave Tx completed callback */ 308 void (*slave_rx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Slave Rx completed callback */ 309 void (*mem_tx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Tx to Memory completed callback */ 310 void (*mem_rx_cplt_cbk)(struct ald_i2c_handle_s *arg); /**< Rx from Memory completed callback */ 311 void (*error_callback)(struct ald_i2c_handle_s *arg); /**< Error callback */ 312 } ald_i2c_handle_t; 313 314 /** 315 * @} 316 */ 317 318 /** @defgroup I2C_Public_Macro I2C Public Macros 319 * @{ 320 */ 321 322 /** 323 * @brief I2C Direction Definition 324 */ 325 #define ALD_I2C_DIRECTION_RECEIVE (0x00000000U) 326 #define ALD_I2C_DIRECTION_TRANSMIT (0x00000001U) 327 /** 328 * @brief I2C Transfer Definition 329 */ 330 #define ALD_I2C_NO_OPTION_FRAME (0xFFFF0000U) 331 332 #define ALD_I2C_FIRST_FRAME (0x00000001U) 333 #define ALD_I2C_FIRST_AND_NEXT_FRAME (0x00000002U) 334 #define ALD_I2C_NEXT_FRAME (0x00000004U) 335 #define ALD_I2C_FIRST_AND_LAST_FRAME (0x00000008U) 336 #define ALD_I2C_LAST_FRAME_NO_STOP (0x00000010U) 337 #define ALD_I2C_LAST_FRAME (0x00000020U) 338 339 #define ALD_I2C_OTHER_FRAME (0x00550000U) 340 #define ALD_I2C_OTHER_AND_LAST_FRAME (0x55000000U) 341 342 #define ALD_I2C_FLAG_MASK (0xFFFFFFFFU) 343 #define ALD_I2C_RESET_HANDLE_STATE(x) ((x)->state = ALD_I2C_STATE_RESET) 344 #define ALD_I2C_ENABLE_IT(x, y) (SET_BIT((x)->perh->IER, (y))) 345 #define ALD_I2C_DISABLE_IT(x, y) (SET_BIT((x)->perh->IDR, (y))) 346 #define ALD_I2C_CLEAR_IT(x, y) (SET_BIT((x)->perh->ICR, (y))) 347 #define ALD_I2C_GET_IT_FLAG(x, y) (READ_BIT((x)->perh->RIF, (y))) 348 #define ALD_I2C_GET_IT_SOURCE(x, y) ((((x)->perh->IFM & (y)) == (y)) ? SET : RESET) 349 #define ALD_I2C_GET_FLAG(x, y) ((((x)->perh->STAT) & ((y) & ALD_I2C_FLAG_MASK)) != RESET) 350 #define ALD_I2C_MASTER_GET_DIR(x) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK)) 351 #define ALD_I2C_SLAVE_GET_DIR(x) (READ_BIT(((x)->perh->STAT), I2C_STAT_DIR_MSK)) 352 #define ALD_I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) 353 #define ALD_I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) 354 /** 355 * @} 356 */ 357 358 /** @defgroup I2C_Private_Macro I2C Private Macros 359 * @{ 360 */ 361 #define IS_I2C_TYPE(x) (((x) == I2C0) || ((x) == I2C1)) 362 #define IS_I2C_MODULE(x) (((x) == ALD_I2C_MODULE_MASTER) || ((x) == ALD_I2C_MODULE_SLAVE)) 363 #define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == ALD_I2C_ADDR_7BIT) || \ 364 ((ADDRESS) == ALD_I2C_ADDR_10BIT)) 365 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == ALD_I2C_DUALADDR_DISABLE) || \ 366 ((ADDRESS) == ALD_I2C_DUALADDR_ENABLE)) 367 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == ALD_I2C_GENERALCALL_DISABLE) || \ 368 ((CALL) == ALD_I2C_GENERALCALL_ENABLE)) 369 #define IS_I2C_MEMADD_size(size) (((size) == ALD_I2C_MEMADD_SIZE_8BIT) || \ 370 ((size) == ALD_I2C_MEMADD_SIZE_16BIT)) 371 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == ALD_I2C_NOSTRETCH_DISABLE) || \ 372 ((STRETCH) == ALD_I2C_NOSTRETCH_ENABLE)) 373 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= ALD_I2C_EXTREME_FAST_MODE_MAX_CLK) ) 374 #define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__) / 1000000) 375 #define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) &\ 376 (uint16_t)(0xFF00))) >> 8))) 377 #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) 378 #define IS_I2C_IT(x) (((x) == ALD_I2C_IT_TXE) || \ 379 ((x) == ALD_I2C_IT_TXOV) || \ 380 ((x) == ALD_I2C_IT_TXUD) || \ 381 ((x) == ALD_I2C_IT_RXNE) || \ 382 ((x) == ALD_I2C_IT_RXOV) || \ 383 ((x) == ALD_I2C_IT_RXUD) || \ 384 ((x) == ALD_I2C_IT_TC) || \ 385 ((x) == ALD_I2C_IT_TCR) || \ 386 ((x) == ALD_I2C_IT_ADDR) || \ 387 ((x) == ALD_I2C_IT_NACK) || \ 388 ((x) == ALD_I2C_IT_STOP) || \ 389 ((x) == ALD_I2C_IT_BERR) || \ 390 ((x) == ALD_I2C_IT_ARLO) || \ 391 ((x) == ALD_I2C_IT_PECE) || \ 392 ((x) == ALD_I2C_IT_TOUT) || \ 393 ((x) == ALD_I2C_IT_ALERT)) 394 395 #define IS_I2C_TRANSFER_OTHER_OPTIONS(OPTION) (((OPTION) == ALD_I2C_OTHER_FRAME) || \ 396 ((OPTION) == ALD_I2C_OTHER_AND_LAST_FRAME)) 397 398 #define IS_I2C_TRANSFER_OPTIONS(OPTION) (((OPTION) == ALD_I2C_FIRST_FRAME) || \ 399 ((OPTION) == ALD_I2C_FIRST_AND_NEXT_FRAME) || \ 400 ((OPTION) == ALD_I2C_NEXT_FRAME) || \ 401 ((OPTION) == ALD_I2C_FIRST_AND_LAST_FRAME) || \ 402 ((OPTION) == ALD_I2C_LAST_FRAME) || \ 403 ((OPTION) == ALD_I2C_LAST_FRAME_NO_STOP) || \ 404 IS_I2C_TRANSFER_OTHER_OPTIONS(OPTION)) 405 406 #define ALD_I2C_STATE_MSK ((ALD_I2C_STATE_BUSY_TX | ALD_I2C_STATE_BUSY_RX) & (~(ALD_I2C_STATE_READY))) 407 #define ALD_I2C_STATE_NONE (ALD_I2C_MODE_NONE) 408 #define ALD_I2C_STATE_MASTER_BUSY_TX ((ALD_I2C_STATE_BUSY_TX | ALD_I2C_STATE_MSK) | (ALD_I2C_MODE_MASTER)) 409 #define ALD_I2C_STATE_MASTER_BUSY_RX ((ALD_I2C_STATE_BUSY_RX | ALD_I2C_STATE_MSK) | (ALD_I2C_MODE_MASTER)) 410 #define ALD_I2C_STATE_SLAVE_BUSY_TX ((ALD_I2C_STATE_BUSY_TX | ALD_I2C_STATE_MSK) | (ALD_I2C_MODE_SLAVE)) 411 #define ALD_I2C_STATE_SLAVE_BUSY_RX ((ALD_I2C_STATE_BUSY_RX | ALD_I2C_STATE_MSK) | (ALD_I2C_MODE_SLAVE)) 412 413 /** 414 * @} 415 */ 416 417 /** @addtogroup I2C_Public_Functions 418 * @{ 419 */ 420 421 /** @addtogroup I2C_Public_Functions_Group1 Initialization and de-initialization functions 422 * @{ 423 */ 424 ald_status_t ald_i2c_init(ald_i2c_handle_t *hperh); 425 ald_status_t ald_i2c_reset(ald_i2c_handle_t *hperh); 426 427 /** 428 * @} 429 */ 430 431 /** @addtogroup I2C_Public_Functions_Group2 Input and Output operation functions 432 * @{ 433 */ 434 /** Blocking mode: Polling */ 435 ald_status_t ald_i2c_master_send(ald_i2c_handle_t *hperh, uint16_t dev_addr, 436 uint8_t *buf, uint32_t size, uint32_t timeout); 437 ald_status_t ald_i2c_master_recv(ald_i2c_handle_t *hperh, uint16_t dev_addr, 438 uint8_t *buf, uint32_t size, uint32_t timeout); 439 ald_status_t ald_i2c_slave_send(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); 440 ald_status_t ald_i2c_slave_recv(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); 441 ald_status_t ald_i2c_mem_write(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 442 ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout); 443 ald_status_t ald_i2c_mem_read(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 444 ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout); 445 446 /** Non-Blocking mode: Interrupt */ 447 ald_status_t ald_i2c_master_send_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size); 448 ald_status_t ald_i2c_master_recv_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size); 449 ald_status_t ald_i2c_slave_send_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size); 450 ald_status_t ald_i2c_slave_recv_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size); 451 ald_status_t ald_i2c_mem_write_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 452 ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size); 453 ald_status_t ald_i2c_mem_read_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 454 ald_i2c_addr_size_t add_size, uint8_t *buf, uint32_t size); 455 456 457 /** Non-Blocking mode: DMA */ 458 ald_status_t ald_i2c_master_send_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, 459 uint8_t *buf, uint16_t size, uint8_t channel); 460 ald_status_t ald_i2c_master_recv_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, 461 uint8_t *buf, uint16_t size, uint8_t channel); 462 ald_status_t ald_i2c_slave_send_by_dma(ald_i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); 463 ald_status_t ald_i2c_slave_recv_by_dma(ald_i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); 464 ald_status_t ald_i2c_mem_write_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, ald_i2c_addr_size_t add_size, 465 uint8_t *buf, uint16_t size, uint8_t channel); 466 ald_status_t ald_i2c_mem_read_by_dma(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, 467 ald_i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); 468 469 /** Non-Blocking Sequence transmit mode */ 470 471 ald_status_t ald_i2c_master_seq_send_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t option); 472 ald_status_t ald_i2c_master_seq_recv_by_it(ald_i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t option); 473 ald_status_t ald_i2c_slave_seq_send_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t option); 474 ald_status_t ald_i2c_slave_seq_recv_by_it(ald_i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t option); 475 ald_status_t ald_i2c_master_abort_it(ald_i2c_handle_t *hperh, uint16_t addr); 476 ald_status_t ald_i2c_enablelisten_it(ald_i2c_handle_t *hperh); 477 ald_status_t ald_i2c_disablelisten_it(ald_i2c_handle_t *hperh); 478 479 void ald_i2c_seq_ev_irq_handler(ald_i2c_handle_t *hperh); 480 void ald_i2c_seq_er_irq_handler(ald_i2c_handle_t *hperh); 481 482 /** 483 * @} 484 */ 485 486 /** @addtogroup I2C_Public_Functions_Group3 Peripheral state and Errors functions 487 * @{ 488 */ 489 ald_i2c_state_t ald_i2c_get_state(ald_i2c_handle_t *hperh); 490 uint32_t ald_i2c_get_error(ald_i2c_handle_t *hperh); 491 void ald_i2c_clear_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag); 492 flag_status_t ald_i2c_get_mask_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag); 493 flag_status_t ald_i2c_get_flag_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t flag); 494 it_status_t ald_i2c_get_it_status(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t it); 495 /** 496 * @} 497 */ 498 499 /** @addtogroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks 500 * @{ 501 */ 502 void ald_i2c_ev_irq_handler(ald_i2c_handle_t *hperh); 503 void ald_i2c_er_irq_handler(ald_i2c_handle_t *hperh); 504 void ald_i2c_interrupt_config(ald_i2c_handle_t *hperh, ald_i2c_interrupt_t it, type_func_t state); 505 /** 506 * @} 507 */ 508 509 /** 510 * @} 511 */ 512 513 /** 514 * @} 515 */ 516 517 /** 518 * @} 519 */ 520 #ifdef __cplusplus 521 } 522 #endif /* __cplusplus */ 523 524 #endif /* __ALD_I2C_H__ */ 525