1 /** 2 ********************************************************************************* 3 * 4 * @file ald_timer.h 5 * @brief TIMER module driver. 6 * This is the common part of the TIMER initialization 7 * 8 * @version V1.0 9 * @date 03 Mar. 2023 10 * @author AE Team 11 * @note 12 * Change Logs: 13 * Date Author Notes 14 * 03 Mar. 2023 Lisq The first version 15 * 16 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 17 * 18 * SPDX-License-Identifier: Apache-2.0 19 * 20 * Licensed under the Apache License, Version 2.0 (the License); you may 21 * not use this file except in compliance with the License. 22 * You may obtain a copy of the License at 23 * 24 * www.apache.org/licenses/LICENSE-2.0 25 * 26 * Unless required by applicable law or agreed to in writing, software 27 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 28 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 29 * See the License for the specific language governing permissions and 30 * limitations under the License. 31 ********************************************************************************** 32 */ 33 34 #ifndef __ALD_TIMER_H__ 35 #define __ALD_TIMER_H__ 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif /* __cplusplus */ 40 41 #include "ald_utils.h" 42 #include "ald_cmu.h" 43 #include "ald_dma.h" 44 45 /** @addtogroup ES32VF2264_ALD 46 * @{ 47 */ 48 49 /** @addtogroup TIMER 50 * @{ 51 */ 52 53 /** @defgroup TIMER_Public_Types TIMER Public Types 54 * @{ 55 */ 56 57 /** 58 * @brief TIMER counter mode 59 */ 60 typedef enum { 61 ALD_TIMER_CNT_MODE_UP = 0U, /**< Counter mode up */ 62 ALD_TIMER_CNT_MODE_DOWN = 1U, /**< Counter mode down */ 63 ALD_TIMER_CNT_MODE_CENTER1 = 2U, /**< Counter mode center1 */ 64 ALD_TIMER_CNT_MODE_CENTER2 = 3U, /**< Counter mode center2 */ 65 ALD_TIMER_CNT_MODE_CENTER3 = 4U, /**< Counter mode center3 */ 66 } ald_timer_cnt_mode_t; 67 68 /** 69 * @brief TIMER clock division 70 */ 71 typedef enum { 72 ALD_TIMER_CLOCK_DIV1 = 0U, /**< No prescaler is used */ 73 ALD_TIMER_CLOCK_DIV2 = 1U, /** Clock is divided by 2 */ 74 ALD_TIMER_CLOCK_DIV4 = 2U, /** Clock is divided by 4 */ 75 } ald_timer_clock_division_t; 76 77 /** 78 * @brief TIMER output compare and PWM modes 79 */ 80 typedef enum { 81 ALD_TIMER_OC_MODE_TIMERING = 0U, /**< Output compare mode is timering */ 82 ALD_TIMER_OC_MODE_ACTIVE = 1U, /**< Output compare mode is active */ 83 ALD_TIMER_OC_MODE_INACTIVE = 2U, /**< Output compare mode is inactive */ 84 ALD_TIMER_OC_MODE_TOGGLE = 3U, /**< Output compare mode is toggle */ 85 ALD_TIMER_OC_MODE_FORCE_INACTIVE = 4U, /**< Output compare mode is force inactive */ 86 ALD_TIMER_OC_MODE_FORCE_ACTIVE = 5U, /**< Output compare mode is force active */ 87 ALD_TIMER_OC_MODE_PWM1 = 6U, /**< Output compare mode is pwm1 */ 88 ALD_TIMER_OC_MODE_PWM2 = 7U, /**< Output compare mode is pwm2 */ 89 } ald_timer_oc_mode_t; 90 91 /** 92 * @brief TIMER output compare polarity 93 */ 94 typedef enum { 95 ALD_TIMER_OC_POLARITY_HIGH = 0U, /**< Output compare polarity is high */ 96 ALD_TIMER_OC_POLARITY_LOW = 1U, /**< Output compare polarity is low */ 97 } ald_timer_oc_polarity_t; 98 99 /** 100 * @brief TIMER complementary output compare polarity 101 */ 102 typedef enum { 103 ALD_TIMER_OCN_POLARITY_HIGH = 0U, /**< Complementary output compare polarity is high */ 104 ALD_TIMER_OCN_POLARITY_LOW = 1U, /**< Complementary output compare polarity is low */ 105 } ald_timer_ocn_polarity_t; 106 107 /** 108 * @brief TIMER output compare idle state 109 */ 110 typedef enum { 111 ALD_TIMER_OC_IDLE_RESET = 0U, /**< Output compare idle state is reset */ 112 ALD_TIMER_OC_IDLE_SET = 1U, /**< Output compare idle state is set */ 113 } ald_timer_oc_idle_t; 114 115 /** 116 * @brief TIMER complementary output compare idle state 117 */ 118 typedef enum { 119 ALD_TIMER_OCN_IDLE_RESET = 0U, /**< Complementary output compare idle state is reset */ 120 ALD_TIMER_OCN_IDLE_SET = 1U, /**< Complementary output compare idle state is set */ 121 } ald_timer_ocn_idle_t; 122 123 /** 124 * @brief TIMER channel 125 */ 126 typedef enum { 127 ALD_TIMER_CHANNEL_1 = 0U, /**< Channel 1 */ 128 ALD_TIMER_CHANNEL_2 = 1U, /**< Channel 2 */ 129 ALD_TIMER_CHANNEL_3 = 2U, /**< Channel 3 */ 130 ALD_TIMER_CHANNEL_4 = 3U, /**< Channel 4 */ 131 ALD_TIMER_CHANNEL_ALL = 0xFU, /**< All channel */ 132 } ald_timer_channel_t; 133 134 /** 135 * @brief TIMER one pulse mode 136 */ 137 typedef enum { 138 ALD_TIMER_OP_MODE_REPEAT = 0U, /**< Repetitive */ 139 ALD_TIMER_OP_MODE_SINGLE = 1U, /**< single */ 140 } ald_timer_op_mode_t; 141 142 /** 143 * @brief TIMER one pulse output channel 144 */ 145 typedef enum { 146 ALD_TIMER_OP_OUTPUT_CHANNEL_1 = 0U, /**< One pulse output channal 1 */ 147 ALD_TIMER_OP_OUTPUT_CHANNEL_2 = 1U, /**< One pulse output channal 2 */ 148 } ald_timer_op_output_channel_t; 149 150 /** 151 * @brief TIMER time base configuration structure definition 152 */ 153 typedef struct { 154 uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ 155 ald_timer_cnt_mode_t mode; /**< Specifies the counter mode. */ 156 uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ 157 ald_timer_clock_division_t clk_div; /**< Specifies the clock division.*/ 158 uint32_t re_cnt; /**< Specifies the repetition counter value. */ 159 } ald_timer_base_init_t; 160 161 /** 162 * @brief TIMER output compare configuration structure definition 163 */ 164 typedef struct { 165 ald_timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ 166 uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ 167 ald_timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ 168 ald_timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ 169 type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ 170 ald_timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ 171 ald_timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ 172 } ald_timer_oc_init_t; 173 174 /** 175 * @brief State structures definition 176 */ 177 typedef enum { 178 ALD_TIMER_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */ 179 ALD_TIMER_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ 180 ALD_TIMER_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ 181 ALD_TIMER_STATE_TIMEREOUT = 0x03U, /**< Timeout state */ 182 ALD_TIMER_STATE_ERROR = 0x04U, /**< Reception process is ongoing */ 183 } ald_timer_state_t; 184 185 /** 186 * @brief Active channel structures definition 187 */ 188 typedef enum { 189 ALD_TIMER_ACTIVE_CHANNEL_1 = 0x01U, /**< The active channel is 1 */ 190 ALD_TIMER_ACTIVE_CHANNEL_2 = 0x02U, /**< The active channel is 2 */ 191 ALD_TIMER_ACTIVE_CHANNEL_3 = 0x04U, /**< The active channel is 3 */ 192 ALD_TIMER_ACTIVE_CHANNEL_4 = 0x08U, /**< The active channel is 4 */ 193 ALD_TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U, /**< All active channels cleared */ 194 } ald_timer_active_channel_t; 195 196 /** 197 * @brief TIMER time base handle structure definition 198 */ 199 typedef struct ald_timer_handle_s { 200 TIMER_TypeDef *perh; /**< Register base address */ 201 ald_timer_base_init_t init; /**< TIMER Time Base required parameters */ 202 ald_timer_active_channel_t ch; /**< Active channel */ 203 lock_state_t lock; /**< Locking object */ 204 ald_timer_state_t state; /**< TIMER operation state */ 205 206 ald_dma_handle_t hdma1; /**< Timer DMA handle parameters */ 207 ald_dma_handle_t hdma2; 208 209 void (*period_elapse_cbk)(struct ald_timer_handle_s *arg); /**< Period elapse callback */ 210 void (*delay_elapse_cbk)(struct ald_timer_handle_s *arg); /**< Delay_elapse callback */ 211 void (*capture_cbk)(struct ald_timer_handle_s *arg); /**< Capture callback */ 212 void (*pwm_pulse_finish_cbk)(struct ald_timer_handle_s *arg); /**< PWM_pulse_finish callback */ 213 void (*trigger_cbk)(struct ald_timer_handle_s *arg); /**< Trigger callback */ 214 void (*break_cbk)(struct ald_timer_handle_s *arg); /**< Break callback */ 215 void (*com_cbk)(struct ald_timer_handle_s *arg); /**< commutation callback */ 216 void (*error_cbk)(struct ald_timer_handle_s *arg); /**< Error callback */ 217 } ald_timer_handle_t; 218 219 220 /** 221 * @brief TIMER encoder mode 222 */ 223 typedef enum { 224 ALD_TIMER_ENC_MODE_TI1 = 1U, /**< encoder mode 1 */ 225 ALD_TIMER_ENC_MODE_TI2 = 2U, /**< encoder mode 2 */ 226 ALD_TIMER_ENC_MODE_TI12 = 3U, /**< encoder mode 3 */ 227 } ald_timer_encoder_mode_t; 228 229 /** 230 * @brief TIMER input capture polarity 231 */ 232 typedef enum { 233 ALD_TIMER_IC_POLARITY_RISE = 0U, /**< Input capture polarity rising */ 234 ALD_TIMER_IC_POLARITY_FALL = 1U, /**< Input capture polarity falling */ 235 } ald_timer_ic_polarity_t; 236 237 /** 238 *@brief TIMER input capture selection 239 */ 240 typedef enum { 241 ALD_TIMER_IC_SEL_DIRECT = 1U, /**< IC1 -- TI1 */ 242 ALD_TIMER_IC_SEL_INDIRECT = 2U, /**< IC1 -- TI2 */ 243 ALD_TIMER_IC_SEL_TRC = 3U, /**< IC1 -- TRC */ 244 } ald_timer_ic_select_t; 245 246 /** 247 * @brief TIMER input capture prescaler 248 */ 249 typedef enum { 250 ALD_TIMER_IC_PSC_DIV1 = 0U, /**< Capture performed once every 1 events */ 251 ALD_TIMER_IC_PSC_DIV2 = 1U, /**< Capture performed once every 2 events */ 252 ALD_TIMER_IC_PSC_DIV4 = 2U, /**< Capture performed once every 4 events */ 253 ALD_TIMER_IC_PSC_DIV8 = 3U, /**< Capture performed once every 4 events */ 254 } ald_timer_ic_prescaler_t; 255 256 /** 257 * @brief TIMER encoder configuration structure definition 258 */ 259 typedef struct { 260 ald_timer_encoder_mode_t mode; /**< Specifies the encoder mode */ 261 ald_timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ 262 ald_timer_ic_select_t ic1_sel; /**< Specifies the input */ 263 ald_timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ 264 uint32_t ic1_filter; /**< Specifies the input capture filter */ 265 ald_timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ 266 ald_timer_ic_select_t ic2_sel; /**< Specifies the input */ 267 ald_timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ 268 uint32_t ic2_filter; /**< Specifies the input capture filter */ 269 } ald_timer_encoder_init_t; 270 271 /** 272 * @brief TIMER input capture configuration structure definition 273 */ 274 typedef struct { 275 ald_timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ 276 ald_timer_ic_select_t sel; /**< Specifies the input */ 277 ald_timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ 278 uint32_t filter; /**< Specifies the input capture filter */ 279 } ald_timer_ic_init_t; 280 281 /** 282 * @brief TIMER one pulse mode configuration structure definition 283 */ 284 typedef struct { 285 ald_timer_oc_mode_t mode; /**< Specifies the TIMER mode */ 286 uint16_t pulse; /**< Specifies the pulse value */ 287 ald_timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ 288 ald_timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ 289 ald_timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ 290 ald_timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ 291 ald_timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ 292 ald_timer_ic_select_t sel; /**< Specifies the input */ 293 uint32_t filter; /**< Specifies the input capture filter */ 294 } ald_timer_one_pulse_init_t; 295 296 /** @brief TIMER clear input source 297 */ 298 typedef enum { 299 ALD_TIMER_INPUT_NONE = 0U, /**< Clear input none */ 300 ALD_TIMER_INPUT_ETR = 1U, /**< Clear input etr */ 301 } ald_timer_clear_input_source_t; 302 303 /** @brief TIMER clear input polarity 304 */ 305 typedef enum { 306 ALD_TIMER_POLARITY_NO_INV = 0U, /**< Polarity for ETRx pin */ 307 ALD_TIMER_POLARITY_INV = 1U, /**< Polarity for ETRx pin */ 308 } ald_timer_clear_input_polarity_t; 309 310 /** @brief TIMER clear input polarity 311 */ 312 typedef enum { 313 ALD_TIMER_ETR_PSC_DIV1 = 0U, /**< No prescaler is used */ 314 ALD_TIMER_ETR_PSC_DIV2 = 1U, /**< ETR input source is divided by 2 */ 315 ALD_TIMER_ETR_PSC_DIV4 = 2U, /**< ETR input source is divided by 4 */ 316 ALD_TIMER_ETR_PSC_DIV8 = 3U, /**< ETR input source is divided by 8 */ 317 } ald_timer_etr_psc_t; 318 319 /** @brief TIMER CHnREF Clear Select 320 */ 321 typedef enum { 322 ALD_TIMER_CHNREF_CLR_CMP_IN = 0U, /**< Comparator CMP_IN */ 323 ALD_TIMER_CHNREF_CLR_ETF = 1U, /**< External Trigger Signal ETF */ 324 } ald_timer_chnref_clr_sel_t; 325 326 /** @brief TIMER clear input configuration handle structure definition 327 */ 328 typedef struct { 329 type_func_t state; /**< TIMER clear Input state */ 330 ald_timer_clear_input_source_t source; /**< TIMER clear Input sources */ 331 ald_timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ 332 ald_timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ 333 ald_timer_chnref_clr_sel_t clrsel; /**<TIMER CHnREF_Clear */ 334 uint32_t filter; /**< TIMER Clear Input filter */ 335 } ald_timer_clear_input_config_t; 336 337 /** @brief TIMER clock source 338 */ 339 typedef enum { 340 ALD_TIMER_SRC_ETRMODE2 = 0U, /**< Clock source is etr mode2 */ 341 ALD_TIMER_SRC_INTER = 1U, /**< Clock source is etr internal */ 342 ALD_TIMER_SRC_ITR0 = 2U, /**< Clock source is etr itr0 */ 343 ALD_TIMER_SRC_ITR1 = 3U, /**< Clock source is etr itr1 */ 344 ALD_TIMER_SRC_ITR2 = 4U, /**< Clock source is etr itr2 */ 345 ALD_TIMER_SRC_ITR3 = 5U, /**< Clock source is etr itr3 */ 346 ALD_TIMER_SRC_TI1ED = 6U, /**< Clock source is etr ti1ed */ 347 ALD_TIMER_SRC_TI1 = 7U, /**< Clock source is etr ti1 */ 348 ALD_TIMER_SRC_TI2 = 8U, /**< Clock source is etr ti2 */ 349 ALD_TIMER_SRC_ETRMODE1 = 9U, /**< Clock source is etr mode1 */ 350 } ald_timer_clock_source_t; 351 352 /** @brief TIMER clock polarity 353 */ 354 typedef enum { 355 ALD_TIMER_CLK_POLARITY_INV = 1U, /**< Polarity for ETRx clock sources */ 356 ALD_TIMER_CLK_POLARITY_NO_INV = 0U, /**< Polarity for ETRx clock sources */ 357 ALD_TIMER_CLK_POLARITY_RISE = 0U, /**< Polarity for TIx clock sources */ 358 ALD_TIMER_CLK_POLARITY_FALL = 1U, /**< Polarity for TIx clock sources */ 359 ALD_TIMER_CLK_POLARITY_BOTH = 3U, /**< Polarity for TIx clock sources */ 360 } ald_timer_clock_polarity_t; 361 362 /** 363 * @brief TIMER clock config structure definition 364 */ 365 typedef struct { 366 ald_timer_clock_source_t source; /**< TIMER clock sources */ 367 ald_timer_clock_polarity_t polarity; /**< TIMER clock polarity */ 368 ald_timer_etr_psc_t psc; /**< TIMER clock prescaler */ 369 uint32_t filter; /**< TIMER clock filter */ 370 } ald_timer_clock_config_t; 371 372 /** 373 * @brief TIMER slave mode 374 */ 375 typedef enum { 376 ALD_TIMER_MODE_DISABLE = 0U, /**< Slave mode is disable */ 377 ALD_TIMER_MODE_ENC1 = 1U, /**< Slave mode is encoder1 */ 378 ALD_TIMER_MODE_ENC2 = 2U, /**< Slave mode is encoder2 */ 379 ALD_TIMER_MODE_ENC3 = 3U, /**< Slave mode is encoder3 */ 380 ALD_TIMER_MODE_RESET = 4U, /**< Slave mode is reset */ 381 ALD_TIMER_MODE_GATED = 5U, /**< Slave mode is gated */ 382 ALD_TIMER_MODE_TRIG = 6U, /**< Slave mode is trigger */ 383 ALD_TIMER_MODE_EXTERNAL1 = 7U, /**< Slave mode is external1 */ 384 } ald_timer_slave_mode_t; 385 386 /** 387 * @brief TIMER ts definition 388 */ 389 typedef enum { 390 ALD_TIMER_TS_ITR0 = 0U, /**< ITR0 */ 391 ALD_TIMER_TS_ITR1 = 1U, /**< ITR1 */ 392 ALD_TIMER_TS_ITR2 = 2U, /**< ITR2 */ 393 ALD_TIMER_TS_ITR3 = 3U, /**< ITR3 */ 394 ALD_TIMER_TS_TI1F_ED = 4U, /**< TI1F_ED */ 395 ALD_TIMER_TS_TI1FP1 = 5U, /**< TI1FP1 */ 396 ALD_TIMER_TS_TI2FP2 = 6U, /**< TI2FP2 */ 397 ALD_TIMER_TS_ETRF = 7U, /**< ETRF */ 398 } ald_timer_ts_t; 399 400 /** 401 * @brief TIMER slave configuration structure definition 402 */ 403 typedef struct { 404 ald_timer_slave_mode_t mode; /**< Slave mode selection */ 405 ald_timer_ts_t input; /**< Input Trigger source */ 406 ald_timer_clock_polarity_t polarity; /**< Input Trigger polarity */ 407 ald_timer_etr_psc_t psc; /**< Input trigger prescaler */ 408 uint32_t filter; /**< Input trigger filter */ 409 } ald_timer_slave_config_t; 410 411 /** 412 * @brief TIMER hall sensor configuretion structure definition 413 */ 414 typedef struct { 415 ald_timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ 416 ald_timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ 417 uint32_t filter; /**< Specifies the input capture filter [0x0, 0xF] */ 418 uint32_t delay; /**< Specifies the pulse value to be loaded into the register [0x0, 0xFFFF] */ 419 } ald_timer_hall_sensor_init_t; 420 421 /** 422 * @brief TIMER lock level 423 */ 424 typedef enum { 425 ALD_TIMER_LOCK_LEVEL_OFF = 0U, /**< Lock off */ 426 ALD_TIMER_LOCK_LEVEL_1 = 1U, /**< Lock level 1 */ 427 ALD_TIMER_LOCK_LEVEL_2 = 2U, /**< Lock level 2 */ 428 ALD_TIMER_LOCK_LEVEL_3 = 3U, /**< Lock level 3 */ 429 } ald_timer_lock_level_t; 430 431 /** 432 * @brief TIMER break polarity 433 */ 434 typedef enum { 435 ALD_TIMER_BREAK_POLARITY_LOW = 0U, /**< LOW */ 436 ALD_TIMER_BREAK_POLARITY_HIGH = 1U, /**< HIGH */ 437 } ald_timer_break_polarity_t; 438 439 /** 440 * @brief TIMER break and dead time configuretion structure definition 441 */ 442 typedef struct { 443 type_func_t off_run; /**< Enalbe/Disable off state in run mode */ 444 type_func_t off_idle; /**< Enalbe/Disable off state in idle mode */ 445 ald_timer_lock_level_t lock_level; /**< Lock level */ 446 uint32_t dead_time; /**< Dead time, [0x0, 0xFF] */ 447 type_func_t break_state; /**< Break state */ 448 ald_timer_break_polarity_t polarity; /**< Break input polarity */ 449 type_func_t auto_out; /**< Enalbe/Disable automatic output */ 450 } ald_timer_break_dead_time_t; 451 452 /** 453 * @brief TIMER commutation event channel configuretion structure definition 454 */ 455 typedef struct { 456 type_func_t en; /**< Enalbe/Disable the channel */ 457 type_func_t n_en; /**< Enalbe/Disable the complementary channel */ 458 ald_timer_oc_mode_t mode; /**< Mode of the channel */ 459 } ald_timer_channel_config_t; 460 461 /** 462 * @brief TIMER commutation event configuretion structure definition 463 */ 464 typedef struct { 465 ald_timer_channel_config_t ch[3]; /**< Configure of channel */ 466 } ald_timer_com_channel_config_t; 467 468 /** 469 * @brief TIMER master mode selection 470 */ 471 typedef enum { 472 ALD_TIMER_TRGO_RESET = 0U, /**< RESET */ 473 ALD_TIMER_TRGO_ENABLE = 1U, /**< ENABLE */ 474 ALD_TIMER_TRGO_UPDATE = 2U, /**< UPDATE */ 475 ALD_TIMER_TRGO_OC1 = 3U, /**< OC1 */ 476 ALD_TIMER_TRGO_OC1REF = 4U, /**< OC1REF */ 477 ALD_TIMER_TRGO_OC2REF = 5U, /**< OC2REF */ 478 ALD_TIMER_TRGO_OC3REF = 6U, /**< OC3REF */ 479 ALD_TIMER_TRGO_OC4REF = 7U, /**< OC4REF */ 480 } ald_timer_master_mode_sel_t; 481 482 /** 483 * @brief TIMER master configuretion structure definition 484 */ 485 typedef struct { 486 ald_timer_master_mode_sel_t sel; /**< Specifies the active edge of the input signal */ 487 type_func_t master_en; /**< Master/Slave mode selection */ 488 } ald_timer_master_config_t; 489 490 /** 491 * @brief Specifies the event source 492 */ 493 typedef enum { 494 ALD_TIMER_SRC_UPDATE = (1U << 0), /**< Event source is update */ 495 ALD_TIMER_SRC_CC1 = (1U << 1), /**< Event source is channel1 */ 496 ALD_TIMER_SRC_CC2 = (1U << 2), /**< Event source is channel2 */ 497 ALD_TIMER_SRC_CC3 = (1U << 3), /**< Event source is channel3 */ 498 ALD_TIMER_SRC_CC4 = (1U << 4), /**< Event source is channel4 */ 499 ALD_TIMER_SRC_COM = (1U << 5), /**< Event source is compare */ 500 ALD_TIMER_SRC_TRIG = (1U << 6), /**< Event source is trigger */ 501 ALD_TIMER_SRC_BREAK = (1U << 7), /**< Event source is break */ 502 } ald_timer_event_source_t; 503 504 /** 505 * @brief TIMER interrupt definition 506 */ 507 typedef enum { 508 ALD_TIMER_IT_UPDATE = (1U << 0), /**< Update interrupt bit */ 509 ALD_TIMER_IT_CC1 = (1U << 1), /**< Channel1 interrupt bit */ 510 ALD_TIMER_IT_CC2 = (1U << 2), /**< Channel2 interrupt bit */ 511 ALD_TIMER_IT_CC3 = (1U << 3), /**< Channel3 interrupt bit */ 512 ALD_TIMER_IT_CC4 = (1U << 4), /**< Channel4 interrupt bit */ 513 ALD_TIMER_IT_COM = (1U << 5), /**< compare interrupt bit */ 514 ALD_TIMER_IT_TRIGGER = (1U << 6), /**< Trigger interrupt bit */ 515 ALD_TIMER_IT_BREAK = (1U << 7), /**< Break interrupt bit */ 516 } ald_timer_it_t; 517 518 /** 519 * @brief TIMER DMA request 520 */ 521 typedef enum { 522 ALD_TIMER_DMA_UPDATE = (1U << 0), /**< DMA request from update */ 523 ALD_TIMER_DMA_CC1 = (1U << 1), /**< DMA request from channel1 */ 524 ALD_TIMER_DMA_CC2 = (1U << 2), /**< DMA request from channel2 */ 525 ALD_TIMER_DMA_CC3 = (1U << 3), /**< DMA request from channel3 */ 526 ALD_TIMER_DMA_CC4 = (1U << 4), /**< DMA request from channel4 */ 527 ALD_TIMER_DMA_COM = (1U << 5), /**< DMA request from compare */ 528 ALD_TIMER_DMA_TRIGGER = (1U << 6), /**< DMA request from trigger */ 529 } ald_timer_dma_req_t; 530 531 /** 532 * @brief TIMER flag definition 533 */ 534 typedef enum { 535 ALD_TIMER_FLAG_UPDATE = (1U << 0), /**< Update interrupt flag */ 536 ALD_TIMER_FLAG_CC1 = (1U << 1), /**< Channel1 interrupt flag */ 537 ALD_TIMER_FLAG_CC2 = (1U << 2), /**< Channel2 interrupt flag */ 538 ALD_TIMER_FLAG_CC3 = (1U << 3), /**< Channel3 interrupt flag */ 539 ALD_TIMER_FLAG_CC4 = (1U << 4), /**< Channel4 interrupt flag */ 540 ALD_TIMER_FLAG_COM = (1U << 5), /**< Compare interrupt flag */ 541 ALD_TIMER_FLAG_TRIGGER = (1U << 6), /**< Trigger interrupt flag */ 542 ALD_TIMER_FLAG_BREAK = (1U << 7), /**< Break interrupt flag */ 543 ALD_TIMER_FLAG_CC1OF = (1U << 9), /**< Channel1 override state flag */ 544 ALD_TIMER_FLAG_CC2OF = (1U << 10), /**< Channel2 override state flag */ 545 ALD_TIMER_FLAG_CC3OF = (1U << 11), /**< Channel3 override state flag */ 546 ALD_TIMER_FLAG_CC4OF = (1U << 12), /**< Channel4 override state flag */ 547 } ald_timer_flag_t; 548 /** 549 * @} 550 */ 551 552 /** @defgroup TIMER_Public_Macros TIMER Public Macros 553 * @{ 554 */ 555 #define ALD_CCER_CCxE_MASK ((1U << 0) | (1U << 4) | (1U << 8) | (1U << 12)) 556 #define ALD_CCER_CCxNE_MASK ((1U << 2) | (1U << 6) | (1U << 10)) 557 558 /** 559 * @brief Reset TIMER handle state 560 */ 561 #define ALD_TIMER_RESET_HANDLE_STATE(hperh) ((hperh)->state = TIMER_STATE_RESET) 562 563 /** 564 * @brief Enable the TIMER peripheral. 565 */ 566 #define ALD_TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK)) 567 568 /** 569 * @brief Enable the TIMER main output. 570 */ 571 #define ALD_TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK)) 572 573 /** 574 * @brief Disable the TIMER peripheral. 575 */ 576 #define ALD_TIMER_DISABLE(hperh) \ 577 do { \ 578 if ((((hperh)->perh->CCEP & ALD_CCER_CCxE_MASK) == 0) \ 579 && (((hperh)->perh->CCEP & ALD_CCER_CCxNE_MASK) == 0)) \ 580 CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ 581 } while (0) 582 583 /** 584 * @brief Disable the TIMER main output. 585 * @note The Main Output Enable of a timer instance is disabled only if 586 * all the CCx and CCxN channels have been disabled 587 */ 588 #define ALD_TIMER_MOE_DISABLE(hperh) \ 589 do { \ 590 if ((((hperh)->perh->CCEP & ALD_CCER_CCxE_MASK) == 0) \ 591 && (((hperh)->perh->CCEP & ALD_CCER_CCxNE_MASK) == 0)) \ 592 CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ 593 } while (0) 594 595 /** 596 * @brief Sets the TIMER autoreload register value on runtime without calling 597 * another time any Init function. 598 */ 599 #define ALD_TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ 600 do { \ 601 (handle)->perh->AR = (AUTORELOAD); \ 602 (handle)->init.period = (AUTORELOAD); \ 603 } while (0) 604 605 /** 606 * @brief Gets the TIMER autoreload register value on runtime 607 */ 608 #define ALD_TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR) 609 610 /** 611 * @brief Gets the TIMER count register value on runtime 612 */ 613 #define ALD_TIMER_GET_CNT(handle) ((handle)->perh->COUNT) 614 615 /** 616 * @brief Gets the TIMER count direction value on runtime 617 */ 618 #define ALD_TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS)) 619 620 /** 621 * @brief CCx DMA request sent when CCx event occurs 622 */ 623 #define ALD_TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) 624 625 /** 626 * @brief CCx DMA request sent when update event occurs 627 */ 628 #define ALD_TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) 629 630 /** 631 * @brief Enable channel 632 * @param handle: TIMER handle 633 * @param ch: Must be one of this: 634 * TIMER_CHANNEL_1 635 * TIMER_CHANNEL_2 636 * TIMER_CHANNEL_3 637 * TIMER_CHANNEL_4 638 */ 639 #define ALD_TIMER_CCx_ENABLE(handle, ch) (((ch) == ALD_TIMER_CHANNEL_4) ? \ 640 (SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) 641 642 /** 643 * @brief Disable channel 644 * @param handle: TIMER handle 645 * @param ch: Must be one of this: 646 * TIMER_CHANNEL_1 647 * TIMER_CHANNEL_2 648 * TIMER_CHANNEL_3 649 * TIMER_CHANNEL_4 650 */ 651 #define ALD_TIMER_CCx_DISABLE(handle, ch) (((ch) == ALD_TIMER_CHANNEL_4) ? \ 652 (CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) 653 654 /** 655 * @brief Enable complementary channel 656 * @param handle: TIMER handle 657 * @param ch: Must be one of this: 658 * TIMER_CHANNEL_1 659 * TIMER_CHANNEL_2 660 * TIMER_CHANNEL_3 661 */ 662 #define ALD_TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) 663 664 /** 665 * @brief Disable complementary channel 666 * @param handle: TIMER handle 667 * @param ch: Must be one of this: 668 * TIMER_CHANNEL_1 669 * TIMER_CHANNEL_2 670 * TIMER_CHANNEL_3 671 */ 672 #define ALD_TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) 673 /** 674 * @} 675 */ 676 677 /** @defgroup TIMER_Private_Macros TIMER Private Macros 678 * @{ 679 */ 680 681 #define IS_TIMER_INSTANCE(x) (((x) == AD16C4T) || \ 682 ((x) == BS16T) || \ 683 ((x) == GP16C4T0) || \ 684 ((x) == GP16C4T1) || \ 685 ((x) == GP16C4T2)) 686 #define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T) 687 #define IS_TIMER_XOR_INSTANCE(x) (((x) == AD16C4T) || \ 688 ((x) == GP16C4T2) || \ 689 ((x) == GP16C4T1) || \ 690 ((x) == GP16C4T0)) 691 #define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == AD16C4T) || \ 692 ((x) == GP16C4T2) || \ 693 ((x) == GP16C4T1) || \ 694 ((x) == GP16C4T0)) 695 #define IS_TIMER_CC2_INSTANCE(x) (((x) == AD16C4T) || \ 696 ((x) == GP16C4T0) || \ 697 ((x) == GP16C4T1) || \ 698 ((x) == GP16C4T2)) 699 #define IS_TIMER_CC4_INSTANCE(x) (((x) == AD16C4T) || \ 700 ((x) == GP16C4T0) || \ 701 ((x) == GP16C4T1) || \ 702 ((x) == GP16C4T2)) 703 #define IS_TIMER_BREAK_INSTANCE(x) ((x) == AD16C4T) 704 #define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == AD16C4T) && \ 705 (((y) == ALD_TIMER_CHANNEL_1) || \ 706 ((y) == ALD_TIMER_CHANNEL_2))) || \ 707 (((x) == GP16C4T0) && \ 708 (((y) == ALD_TIMER_CHANNEL_1) || \ 709 ((y) == ALD_TIMER_CHANNEL_2))) || \ 710 (((x) == GP16C4T1) && \ 711 (((y) == ALD_TIMER_CHANNEL_1) || \ 712 ((y) == ALD_TIMER_CHANNEL_2))) || \ 713 (((x) == GP16C4T2) && \ 714 (((y) == ALD_TIMER_CHANNEL_1) || \ 715 ((y) == ALD_TIMER_CHANNEL_2)))) 716 #define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == AD16C4T) && \ 717 (((y) == ALD_TIMER_CHANNEL_1) || \ 718 ((y) == ALD_TIMER_CHANNEL_2) || \ 719 ((y) == ALD_TIMER_CHANNEL_3) || \ 720 ((y) == ALD_TIMER_CHANNEL_4))) || \ 721 (((x) == GP16C4T0) && \ 722 (((y) == ALD_TIMER_CHANNEL_1) || \ 723 ((y) == ALD_TIMER_CHANNEL_2) || \ 724 ((y) == ALD_TIMER_CHANNEL_3) || \ 725 ((y) == ALD_TIMER_CHANNEL_4))) || \ 726 (((x) == GP16C4T1) && \ 727 (((y) == ALD_TIMER_CHANNEL_1) || \ 728 ((y) == ALD_TIMER_CHANNEL_2) || \ 729 ((y) == ALD_TIMER_CHANNEL_3) || \ 730 ((y) == ALD_TIMER_CHANNEL_4))) || \ 731 (((x) == GP16C4T2) && \ 732 (((y) == ALD_TIMER_CHANNEL_1) || \ 733 ((y) == ALD_TIMER_CHANNEL_2) || \ 734 ((y) == ALD_TIMER_CHANNEL_3) || \ 735 ((y) == ALD_TIMER_CHANNEL_4)))) 736 #define IS_TIMER_CCXN_INSTANCE(x, y) (((x) == AD16C4T) && \ 737 (((y) == ALD_TIMER_CHANNEL_1) || \ 738 ((y) == ALD_TIMER_CHANNEL_2) || \ 739 ((y) == ALD_TIMER_CHANNEL_3) || \ 740 ((y) == ALD_TIMER_CHANNEL_4))) 741 #define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) ((x) == AD16C4T) 742 #define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) 743 744 #define IS_TIMER_COUNTER_MODE(x) (((x) == ALD_TIMER_CNT_MODE_UP) || \ 745 ((x) == ALD_TIMER_CNT_MODE_DOWN) || \ 746 ((x) == ALD_TIMER_CNT_MODE_CENTER1) || \ 747 ((x) == ALD_TIMER_CNT_MODE_CENTER2) || \ 748 ((x) == ALD_TIMER_CNT_MODE_CENTER3)) 749 #define IS_TIMER_CLOCK_DIVISION(x) (((x) == ALD_TIMER_CLOCK_DIV1) || \ 750 ((x) == ALD_TIMER_CLOCK_DIV2) || \ 751 ((x) == ALD_TIMER_CLOCK_DIV4)) 752 #define IS_TIMER_PWM_MODE(x) (((x) == ALD_TIMER_OC_MODE_PWM1) || \ 753 ((x) == ALD_TIMER_OC_MODE_PWM2)) 754 #define IS_TIMER_OC_MODE(x) (((x) == ALD_TIMER_OC_MODE_TIMERING) || \ 755 ((x) == ALD_TIMER_OC_MODE_ACTIVE) || \ 756 ((x) == ALD_TIMER_OC_MODE_INACTIVE) || \ 757 ((x) == ALD_TIMER_OC_MODE_TOGGLE) || \ 758 ((x) == ALD_TIMER_OC_MODE_FORCE_ACTIVE) || \ 759 ((x) == ALD_TIMER_OC_MODE_FORCE_INACTIVE) || \ 760 ((x) == ALD_TIMER_OC_MODE_PWM1) || \ 761 ((x) == ALD_TIMER_OC_MODE_PWM2)) 762 #define IS_TIMER_OC_POLARITY(x) (((x) == ALD_TIMER_OC_POLARITY_HIGH) || \ 763 ((x) == ALD_TIMER_OC_POLARITY_LOW)) 764 #define IS_TIMER_OCN_POLARITY(x) (((x) == ALD_TIMER_OCN_POLARITY_HIGH) || \ 765 ((x) == ALD_TIMER_OCN_POLARITY_LOW)) 766 #define IS_TIMER_OCIDLE_STATE(x) (((x) == ALD_TIMER_OC_IDLE_RESET) || \ 767 ((x) == ALD_TIMER_OC_IDLE_SET)) 768 #define IS_TIMER_OCNIDLE_STATE(x) (((x) == ALD_TIMER_OCN_IDLE_RESET) || \ 769 ((x) == ALD_TIMER_OCN_IDLE_SET)) 770 #define IS_TIMER_CHANNELS(x) (((x) == ALD_TIMER_CHANNEL_1) || \ 771 ((x) == ALD_TIMER_CHANNEL_2) || \ 772 ((x) == ALD_TIMER_CHANNEL_3) || \ 773 ((x) == ALD_TIMER_CHANNEL_4) || \ 774 ((x) == ALD_TIMER_CHANNEL_ALL)) 775 #define IS_TIMER_OP_MODE(x) (((x) == ALD_TIMER_OP_MODE_REPEAT) || \ 776 ((x) == ALD_TIMER_OP_MODE_SINGLE)) 777 #define IS_TIMER_OP_OUTPUT_CH(x) (((x) == ALD_TIMER_OP_OUTPUT_CHANNEL_1) || \ 778 ((x) == ALD_TIMER_OP_OUTPUT_CHANNEL_2)) 779 #define IS_TIMER_ENCODER_MODE(x) (((x) == ALD_TIMER_ENC_MODE_TI1) || \ 780 ((x) == ALD_TIMER_ENC_MODE_TI2) || \ 781 ((x) == ALD_TIMER_ENC_MODE_TI12)) 782 #define IS_TIMER_IC_POLARITY(x) (((x) == ALD_TIMER_IC_POLARITY_RISE) || \ 783 ((x) == ALD_TIMER_IC_POLARITY_FALL)) 784 #define IS_TIMER_IC_SELECT(x) (((x) == ALD_TIMER_IC_SEL_DIRECT) || \ 785 ((x) == ALD_TIMER_IC_SEL_INDIRECT) || \ 786 ((x) == ALD_TIMER_IC_SEL_TRC)) 787 #define IS_TIMER_IC_PSC(x) (((x) == ALD_TIMER_IC_PSC_DIV1) || \ 788 ((x) == ALD_TIMER_IC_PSC_DIV2) || \ 789 ((x) == ALD_TIMER_IC_PSC_DIV4) || \ 790 ((x) == ALD_TIMER_IC_PSC_DIV8)) 791 #define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) 792 #define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) 793 #define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == ALD_TIMER_INPUT_NONE) || \ 794 ((x) == ALD_TIMER_INPUT_ETR)) 795 #define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == ALD_TIMER_POLARITY_NO_INV) || \ 796 ((x) == ALD_TIMER_POLARITY_INV)) 797 #define IS_TIMER_ETR_PSC(x) (((x) == ALD_TIMER_ETR_PSC_DIV1) || \ 798 ((x) == ALD_TIMER_ETR_PSC_DIV2) || \ 799 ((x) == ALD_TIMER_ETR_PSC_DIV4) || \ 800 ((x) == ALD_TIMER_ETR_PSC_DIV8)) 801 #define IS_TIMER_CHNREF_CLEAR(X) (((X) == ALD_TIMER_CHNREF_CLR_CMP_IN) || \ 802 ((X) == ALD_TIMER_CHNREF_CLR_ETF)) 803 #define IS_TIMER_CLOCK_SOURCE(x) (((x) == ALD_TIMER_SRC_ETRMODE2) || \ 804 ((x) == ALD_TIMER_SRC_INTER) || \ 805 ((x) == ALD_TIMER_SRC_ITR0) || \ 806 ((x) == ALD_TIMER_SRC_ITR1) || \ 807 ((x) == ALD_TIMER_SRC_ITR2) || \ 808 ((x) == ALD_TIMER_SRC_ITR3) || \ 809 ((x) == ALD_TIMER_SRC_TI1ED) || \ 810 ((x) == ALD_TIMER_SRC_TI1) || \ 811 ((x) == ALD_TIMER_SRC_TI2) || \ 812 ((x) == ALD_TIMER_SRC_ETRMODE1)) 813 #define IS_TIMER_CLOCK_POLARITY(x) (((x) == ALD_TIMER_CLK_POLARITY_INV) || \ 814 ((x) == ALD_TIMER_CLK_POLARITY_NO_INV) || \ 815 ((x) == ALD_TIMER_CLK_POLARITY_RISE) || \ 816 ((x) == ALD_TIMER_CLK_POLARITY_FALL) || \ 817 ((x) == ALD_TIMER_CLK_POLARITY_BOTH)) 818 #define IS_TIMER_SLAVE_MODE(x) (((x) == ALD_TIMER_MODE_DISABLE) || \ 819 ((x) == ALD_TIMER_MODE_ENC1) || \ 820 ((x) == ALD_TIMER_MODE_ENC2) || \ 821 ((x) == ALD_TIMER_MODE_ENC3) || \ 822 ((x) == ALD_TIMER_MODE_RESET) || \ 823 ((x) == ALD_TIMER_MODE_GATED) || \ 824 ((x) == ALD_TIMER_MODE_TRIG) || \ 825 ((x) == ALD_TIMER_MODE_EXTERNAL1)) 826 #define IS_TIMER_EVENT_SOURCE(x) (((x) == ALD_TIMER_SRC_UPDATE) || \ 827 ((x) == ALD_TIMER_SRC_CC1) || \ 828 ((x) == ALD_TIMER_SRC_CC2) || \ 829 ((x) == ALD_TIMER_SRC_CC3) || \ 830 ((x) == ALD_TIMER_SRC_CC4) || \ 831 ((x) == ALD_TIMER_SRC_COM) || \ 832 ((x) == ALD_TIMER_SRC_TRIG) || \ 833 ((x) == ALD_TIMER_SRC_BREAK)) 834 #define IS_TIMER_TS(x) (((x) == ALD_TIMER_TS_ITR0) || \ 835 ((x) == ALD_TIMER_TS_ITR1) || \ 836 ((x) == ALD_TIMER_TS_ITR2) || \ 837 ((x) == ALD_TIMER_TS_ITR3) || \ 838 ((x) == ALD_TIMER_TS_TI1F_ED) || \ 839 ((x) == ALD_TIMER_TS_TI1FP1) || \ 840 ((x) == ALD_TIMER_TS_TI2FP2) || \ 841 ((x) == ALD_TIMER_TS_ETRF)) 842 #define IS_TIMER_CLOCK_LEVEL(x) (((x) == ALD_TIMER_LOCK_LEVEL_OFF) || \ 843 ((x) == ALD_TIMER_LOCK_LEVEL_1) || \ 844 ((x) == ALD_TIMER_LOCK_LEVEL_2) || \ 845 ((x) == ALD_TIMER_LOCK_LEVEL_3)) 846 #define IS_TIMER_BREAK_POLARITY(x) (((x) == ALD_TIMER_BREAK_POLARITY_LOW) || \ 847 ((x) == ALD_TIMER_BREAK_POLARITY_HIGH)) 848 #define IS_TIMER_MASTER_MODE_SEL(x) (((x) == ALD_TIMER_TRGO_RESET) || \ 849 ((x) == ALD_TIMER_TRGO_ENABLE) || \ 850 ((x) == ALD_TIMER_TRGO_UPDATE) || \ 851 ((x) == ALD_TIMER_TRGO_OC1) || \ 852 ((x) == ALD_TIMER_TRGO_OC1REF) || \ 853 ((x) == ALD_TIMER_TRGO_OC2REF) || \ 854 ((x) == ALD_TIMER_TRGO_OC3REF) || \ 855 ((x) == ALD_TIMER_TRGO_OC4REF)) 856 #define IS_TIMER_IT(x) (((x) == ALD_TIMER_IT_UPDATE) || \ 857 ((x) == ALD_TIMER_IT_CC1) || \ 858 ((x) == ALD_TIMER_IT_CC2) || \ 859 ((x) == ALD_TIMER_IT_CC3) || \ 860 ((x) == ALD_TIMER_IT_CC4) || \ 861 ((x) == ALD_TIMER_IT_COM) || \ 862 ((x) == ALD_TIMER_IT_TRIGGER) || \ 863 ((x) == ALD_TIMER_IT_BREAK)) 864 #define IS_TIMER_DMA_REQ(x) (((x) == ALD_TIMER_DMA_UPDATE) || \ 865 ((x) == ALD_TIMER_DMA_CC1) || \ 866 ((x) == ALD_TIMER_DMA_CC2) || \ 867 ((x) == ALD_TIMER_DMA_CC3) || \ 868 ((x) == ALD_TIMER_DMA_CC4) || \ 869 ((x) == ALD_TIMER_DMA_COM) || \ 870 ((x) == ALD_TIMER_DMA_TRIGGER)) 871 #define IS_TIMER_FLAG(x) (((x) == ALD_TIMER_FLAG_UPDATE) || \ 872 ((x) == ALD_TIMER_FLAG_CC1) || \ 873 ((x) == ALD_TIMER_FLAG_CC2) || \ 874 ((x) == ALD_TIMER_FLAG_CC3) || \ 875 ((x) == ALD_TIMER_FLAG_CC4) || \ 876 ((x) == ALD_TIMER_FLAG_COM) || \ 877 ((x) == ALD_TIMER_FLAG_TRIGGER) || \ 878 ((x) == ALD_TIMER_FLAG_BREAK) || \ 879 ((x) == ALD_TIMER_FLAG_CC1OF) || \ 880 ((x) == ALD_TIMER_FLAG_CC2OF) || \ 881 ((x) == ALD_TIMER_FLAG_CC3OF) || \ 882 ((x) == ALD_TIMER_FLAG_CC4OF)) 883 /** 884 * @} 885 */ 886 887 /** @addtogroup TIMER_Public_Functions 888 * @{ 889 */ 890 /** @addtogroup TIMER_Public_Functions_Group1 891 * @{ 892 */ 893 /* Time Base functions */ 894 ald_status_t ald_timer_base_init(ald_timer_handle_t *hperh); 895 void ald_timer_base_reset(ald_timer_handle_t *hperh); 896 void ald_timer_base_start(ald_timer_handle_t *hperh); 897 void ald_timer_base_stop(ald_timer_handle_t *hperh); 898 void ald_timer_base_start_by_it(ald_timer_handle_t *hperh); 899 void ald_timer_base_stop_by_it(ald_timer_handle_t *hperh); 900 901 ald_status_t ald_timer_base_start_by_dma(ald_timer_handle_t *hperh, 902 uint16_t *buf, uint32_t len, uint8_t dma_ch); 903 void ald_timer_base_stop_by_dma(ald_timer_handle_t *hperh); 904 905 /** 906 * @} 907 */ 908 909 /** @addtogroup TIMER_Public_Functions_Group2 910 * @{ 911 */ 912 /* Timer Output Compare functions */ 913 ald_status_t ald_timer_oc_init(ald_timer_handle_t *hperh); 914 void ald_timer_oc_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 915 void ald_timer_oc_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 916 void ald_timer_oc_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 917 void ald_timer_oc_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 918 919 ald_status_t ald_timer_oc_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, 920 uint16_t *buf, uint32_t len, uint8_t dma_ch); 921 void ald_timer_oc_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 922 923 /** 924 * @} 925 */ 926 927 /** @addtogroup TIMER_Public_Functions_Group3 928 * @{ 929 */ 930 /* Timer PWM functions */ 931 ald_status_t ald_timer_pwm_init(ald_timer_handle_t *hperh); 932 void ald_timer_pwm_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 933 void ald_timer_pwm_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 934 void ald_timer_pwm_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 935 void ald_timer_pwm_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 936 void ald_timer_pwm_set_freq(ald_timer_handle_t *hperh, uint32_t freq); 937 void ald_timer_pwm_set_duty(ald_timer_handle_t *hperh, ald_timer_channel_t ch, uint16_t duty); 938 void ald_timer_pwm_set_input(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 939 940 ald_status_t ald_timer_pwm_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, 941 uint16_t *buf, uint32_t len, uint8_t dma_ch); 942 void ald_timer_pwm_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 943 944 /** 945 * @} 946 */ 947 948 /** @addtogroup TIMER_Public_Functions_Group4 949 * @{ 950 */ 951 /* Timer Input Capture functions */ 952 ald_status_t ald_timer_ic_init(ald_timer_handle_t *hperh); 953 void ald_timer_ic_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 954 void ald_timer_ic_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 955 void ald_timer_ic_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 956 void ald_timer_ic_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 957 958 ald_status_t ald_timer_ic_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, 959 uint16_t *buf, uint32_t len, uint8_t dma_ch); 960 void ald_timer_ic_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 961 962 /** 963 * @} 964 */ 965 966 /** @addtogroup TIMER_Public_Functions_Group5 967 * @{ 968 */ 969 /* Timer One Pulse functions */ 970 ald_status_t ald_timer_one_pulse_init(ald_timer_handle_t *hperh, ald_timer_op_mode_t mode); 971 void ald_timer_one_pulse_start(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch); 972 void ald_timer_one_pulse_stop(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch); 973 void ald_timer_one_pulse_start_by_it(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch); 974 void ald_timer_one_pulse_stop_by_it(ald_timer_handle_t *hperh, ald_timer_op_output_channel_t ch); 975 /** 976 * @} 977 */ 978 979 /** @addtogroup TIMER_Public_Functions_Group6 980 * @{ 981 */ 982 /* Timer encoder functions */ 983 ald_status_t ald_timer_encoder_init(ald_timer_handle_t *hperh, ald_timer_encoder_init_t *config); 984 void ald_timer_encoder_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 985 void ald_timer_encoder_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 986 void ald_timer_encoder_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 987 void ald_timer_encoder_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 988 989 ald_status_t ald_timer_encoder_start_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch, 990 uint16_t *buf1, uint16_t *buf2, uint32_t len, 991 uint8_t dma_ch1, uint8_t dma_ch2); 992 void ald_timer_encoder_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 993 994 /** 995 * @} 996 */ 997 998 /** @addtogroup TIMER_Public_Functions_Group7 999 * @{ 1000 */ 1001 /* Timer hall sensor functions */ 1002 ald_status_t ald_timer_hall_sensor_init(ald_timer_handle_t *hperh, ald_timer_hall_sensor_init_t *config); 1003 void ald_timer_hall_sensor_start(ald_timer_handle_t *hperh); 1004 void ald_timer_hall_sensor_stop(ald_timer_handle_t *hperh); 1005 void ald_timer_hall_sensor_start_by_it(ald_timer_handle_t *hperh); 1006 void ald_timer_hall_sensor_stop_by_it(ald_timer_handle_t *hperh); 1007 1008 ald_status_t ald_timer_hall_sensor_start_by_dma(ald_timer_handle_t *hperh, 1009 uint16_t *buf, uint32_t len, uint8_t dma_ch); 1010 void ald_timer_hall_sensor_stop_by_dma(ald_timer_handle_t *hperh); 1011 1012 /** 1013 * @} 1014 */ 1015 1016 /** @addtogroup TIMER_Public_Functions_Group8 1017 * @{ 1018 */ 1019 /* Timer complementary output compare functions */ 1020 void ald_timer_ocn_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1021 void ald_timer_ocn_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1022 void ald_timer_ocn_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1023 void ald_timer_ocn_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1024 1025 ald_status_t ald_timer_ocn_start_by_dma(ald_timer_handle_t *hperh, 1026 ald_timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); 1027 void ald_timer_ocn_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1028 1029 /** 1030 * @} 1031 */ 1032 1033 /** @addtogroup TIMER_Public_Functions_Group9 1034 * @{ 1035 */ 1036 /* Timer complementary PWM functions */ 1037 void ald_timer_pwmn_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1038 void ald_timer_pwmn_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1039 void ald_timer_pwmn_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1040 void ald_timer_pwmn_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1041 1042 ald_status_t ald_timer_pwmn_start_by_dma(ald_timer_handle_t *hperh, 1043 ald_timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); 1044 void ald_timer_pwmn_stop_by_dma(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1045 1046 /** 1047 * @} 1048 */ 1049 1050 /** @addtogroup TIMER_Public_Functions_Group10 1051 * @{ 1052 */ 1053 /* Timer complementary one pulse functions */ 1054 void ald_timer_one_pulse_n_start(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1055 void ald_timer_one_pulse_n_stop(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1056 void ald_timer_one_pulse_n_start_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1057 void ald_timer_one_pulse_n_stop_by_it(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1058 /** 1059 * @} 1060 */ 1061 1062 /** @addtogroup TIMER_Public_Functions_Group11 1063 * @{ 1064 */ 1065 /* Control functions */ 1066 ald_status_t ald_timer_oc_config_channel(ald_timer_handle_t *hperh, ald_timer_oc_init_t* config, ald_timer_channel_t ch); 1067 ald_status_t ald_timer_ic_config_channel(ald_timer_handle_t *hperh, ald_timer_ic_init_t* config, ald_timer_channel_t ch); 1068 ald_status_t ald_timer_one_pulse_config_channel(ald_timer_handle_t *hperh, ald_timer_one_pulse_init_t *config, ald_timer_channel_t ch_out, ald_timer_channel_t ch_in); 1069 ald_status_t ald_timer_config_oc_ref_clear(ald_timer_handle_t *hperh, ald_timer_clear_input_config_t *config, ald_timer_channel_t ch); 1070 ald_status_t ald_timer_config_clock_source(ald_timer_handle_t *hperh, ald_timer_clock_config_t *config); 1071 ald_status_t ald_timer_config_ti1_input(ald_timer_handle_t *hperh, uint32_t ti1_select); 1072 ald_status_t ald_timer_slave_config_sync(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config); 1073 ald_status_t ald_timer_slave_config_sync_by_it(ald_timer_handle_t *hperh, ald_timer_slave_config_t *config); 1074 ald_status_t ald_timer_generate_event(ald_timer_handle_t *hperh, ald_timer_event_source_t event); 1075 uint32_t ald_timer_read_capture_value(ald_timer_handle_t *hperh, ald_timer_channel_t ch); 1076 void ald_timer_set_output_mode(ald_timer_handle_t *hperh, ald_timer_oc_mode_t mode, ald_timer_channel_t ch); 1077 void ald_timer_com_change_config(ald_timer_handle_t *hperh, ald_timer_com_channel_config_t *config); 1078 void ald_timer_com_event_config(ald_timer_handle_t *hperh, ald_timer_ts_t ts, type_func_t trgi); 1079 void ald_timer_com_event_config_it(ald_timer_handle_t *hperh, ald_timer_ts_t ts, type_func_t trgi); 1080 void ald_timer_break_dead_time_config(ald_timer_handle_t *hperh, ald_timer_break_dead_time_t *config); 1081 void ald_timer_master_sync_config(ald_timer_handle_t *hperh, ald_timer_master_config_t *config); 1082 void ald_timer_irq_handler(ald_timer_handle_t *hperh); 1083 void ald_timer_dma_req_config(ald_timer_handle_t *hperh, ald_timer_dma_req_t req, type_func_t state); 1084 void ald_timer_interrupt_config(ald_timer_handle_t *hperh, ald_timer_it_t it, type_func_t state); 1085 it_status_t ald_timer_get_it_status(ald_timer_handle_t *hperh, ald_timer_it_t it); 1086 flag_status_t ald_timer_get_flag_status(ald_timer_handle_t *hperh, ald_timer_flag_t flag); 1087 void ald_timer_clear_flag_status(ald_timer_handle_t *hperh, ald_timer_flag_t flag); 1088 /** 1089 * @} 1090 */ 1091 1092 /** @addtogroup TIMER_Public_Functions_Group12 1093 * @{ 1094 */ 1095 /* State functions */ 1096 ald_timer_state_t ald_timer_get_state(ald_timer_handle_t *hperh); 1097 /** 1098 * @} 1099 */ 1100 /** 1101 * @} 1102 */ 1103 1104 /** 1105 * @} 1106 */ 1107 /** 1108 * @} 1109 */ 1110 1111 #ifdef __cplusplus 1112 } 1113 #endif /* __cplusplus */ 1114 1115 #endif /* __ALD_TIMER_H__ */ 1116