1 //***************************************************************************** 2 // 3 // am_hal_gpio.h 4 //! @file 5 //! 6 //! @brief Functions for accessing and configuring the GPIO module. 7 //! 8 //! @addtogroup gpio2 GPIO 9 //! @ingroup apollo2hal 10 //! @{ 11 // 12 //***************************************************************************** 13 14 //***************************************************************************** 15 // 16 // Copyright (c) 2017, Ambiq Micro 17 // All rights reserved. 18 // 19 // Redistribution and use in source and binary forms, with or without 20 // modification, are permitted provided that the following conditions are met: 21 // 22 // 1. Redistributions of source code must retain the above copyright notice, 23 // this list of conditions and the following disclaimer. 24 // 25 // 2. Redistributions in binary form must reproduce the above copyright 26 // notice, this list of conditions and the following disclaimer in the 27 // documentation and/or other materials provided with the distribution. 28 // 29 // 3. Neither the name of the copyright holder nor the names of its 30 // contributors may be used to endorse or promote products derived from this 31 // software without specific prior written permission. 32 // 33 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 34 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 37 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 38 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 39 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 40 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 41 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 43 // POSSIBILITY OF SUCH DAMAGE. 44 // 45 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 46 // 47 //***************************************************************************** 48 49 #ifndef AM_HAL_GPIO_H 50 #define AM_HAL_GPIO_H 51 52 // DEVICE ADDRESS IS 8-bits 53 #define AM_HAL_GPIO_DEV_ADDR_8 (0) 54 55 // DEVICE ADDRESS IS 16-bits 56 #define AM_HAL_GPIO_DEV_ADDR_16 (1) 57 58 // DEVICE OFFSET IS 8-bits 59 #define AM_HAL_GPIO_DEV_OFFSET_8 (0x00000000) 60 61 // DEVICE OFFSET IS 16-bits 62 #define AM_HAL_GPIO_DEV_OFFSET_16 (0x00010000) 63 64 // Maximum number of GPIOs on this device 65 #define AM_HAL_GPIO_MAX_PADS (50) 66 67 //***************************************************************************** 68 // 69 //! @name GPIO Pin defines 70 //! @brief GPIO Pin defines for use with interrupt functions 71 //! 72 //! These macros may be used to with \e am_hal_gpio_int_x(). 73 //! 74 //! @{ 75 // 76 //***************************************************************************** 77 #define AM_HAL_GPIO_BIT(n) (((uint64_t) 0x1) << n) 78 //! @} 79 80 // 81 // Helper macros used for unraveling the GPIO configuration value (configval). 82 // 83 // Note that the configval, which is passed into functions such as 84 // am_hal_gpio_pin_config() as well as various helper macros, is a concatenated 85 // value that contains values used in multiple configuration registers. 86 // 87 // The GPIO configuration value fields are arranged as follows: 88 // [ 7: 0] PADREG configuration. 89 // [11: 8] GPIOCFG 90 // [15:12] Unused. 91 // [23:16] ALTPADREG configuration. 92 // 93 // Define macros describing these configval fields. 94 // 95 #define CFGVAL_PADREG_S 0 96 #define CFGVAL_PADREG_M (0xFF << CFGVAL_PADREG_S) 97 #define CFGVAL_GPIOCFG_S 8 98 #define CFGVAL_GPIOCFG_M (0x0F << CFGVAL_GPIOCFG_S) 99 #define CFGVAL_ALTPAD_S 16 100 #define CFGVAL_ALTPAD_M (0xFF << CFGVAL_ALTPAD_S) 101 102 // 103 // Extraction macros 104 // 105 #define CFGVAL_PADREG_X(x) (((uint32_t)(x) & CFGVAL_PADREG_M) >> \ 106 CFGVAL_PADREG_S) 107 #define CFGVAL_GPIOCFG_X(x) (((uint32_t)(x) & CFGVAL_GPIOCFG_M) >> \ 108 CFGVAL_GPIOCFG_S) 109 #define CFGVAL_ALTPAD_X(x) (((uint32_t)(x) & CFGVAL_ALTPAD_M) >> \ 110 CFGVAL_ALTPAD_S) 111 112 //***************************************************************************** 113 // 114 // Input options. 115 // 116 //***************************************************************************** 117 #define AM_HAL_GPIO_INPEN (0x02 << CFGVAL_PADREG_S) // Enable input transistors. 118 #define AM_HAL_GPIO_INCFG_RDZERO (0x01 << CFGVAL_GPIOCFG_S) // Disable input read registers. 119 120 //***************************************************************************** 121 // 122 // Output options (OUTCFG) 123 // 124 //***************************************************************************** 125 #define AM_HAL_GPIO_OUT_DISABLE ((0x0 << 1) << CFGVAL_GPIOCFG_S) 126 #define AM_HAL_GPIO_OUT_PUSHPULL ((0x1 << 1) << CFGVAL_GPIOCFG_S) 127 #define AM_HAL_GPIO_OUT_OPENDRAIN ((0x2 << 1) << CFGVAL_GPIOCFG_S) 128 #define AM_HAL_GPIO_OUT_3STATE ((0x3 << 1) << CFGVAL_GPIOCFG_S) 129 130 //***************************************************************************** 131 // 132 // Special options for IOM0 and IOM4 clocks. 133 // For 24MHz operation, a special enable must be selected. The 24MHZ select is 134 // selected via bit0 of OUTCFG (which is, in a way,an alias of OUT_PUSHPULL). 135 // 136 //***************************************************************************** 137 #define AM_HAL_GPIO_24MHZ_ENABLE ((0x1 << 1) << CFGVAL_GPIOCFG_S) 138 139 //***************************************************************************** 140 // 141 // Pad configuration options. 142 // (Configuration value bits 7:0.) 143 // 144 //***************************************************************************** 145 #define AM_HAL_GPIO_HIGH_DRIVE (0x04 << CFGVAL_PADREG_S) 146 #define AM_HAL_GPIO_LOW_DRIVE (0x00 << CFGVAL_PADREG_S) 147 #define AM_HAL_GPIO_PULLUP (0x01 << CFGVAL_PADREG_S) 148 #define AM_HAL_GPIO_PULL1_5K ( (0x01 << CFGVAL_PADREG_S) | \ 149 AM_HAL_GPIO_PULLUP ) 150 #define AM_HAL_GPIO_PULL6K ( (0x40 << CFGVAL_PADREG_S) | \ 151 AM_HAL_GPIO_PULLUP ) 152 #define AM_HAL_GPIO_PULL12K ( (0x80 << CFGVAL_PADREG_S) | \ 153 AM_HAL_GPIO_PULLUP ) 154 #define AM_HAL_GPIO_PULL24K ( (0xC0 << CFGVAL_PADREG_S) | \ 155 AM_HAL_GPIO_PULLUP ) 156 157 // POWER SWITCH is available on selected pins 158 #define AM_HAL_GPIO_POWER (0x80 << CFGVAL_PADREG_S) 159 160 //***************************************************************************** 161 // 162 //! ALTPADREG configuration options. 163 //! (Configuration value bits 23:16.) 164 //! 165 //! All Apollo2 GPIO pins can be configured for 2mA or 4mA. 166 //! AM_HAL_GPIO_DRIVE_2MA = 2mA configuration. 167 //! AM_HAL_GPIO_DRIVE_4MA = 4mA configuration. 168 //! 169 //! Certain Apollo2 GPIO pins can be configured to drive up to 12mA. 170 //! AM_HAL_GPIO_DRIVE_8MA = 8mA configuration. 171 //! AM_HAL_GPIO_DRIVE_12MA = 12mA configuration. 172 //! 173 //! Notes: 174 //! - Always consult the Apollo2 data sheet for the latest details. 175 //! - The higher drive GPIOxx pads generally include: 176 //! 0-2,5,7-8,10,12-13,22-23,26-29,38-39,42,44-48. 177 //! - GPIOxx pads that do not support the higher drive: 178 //! 3-4,6,9,11,14-21,24-25,30-37,40-41,43,49. 179 //! - User is responsible for ensuring that the selected pin actually supports 180 //! the higher drive (8mA or 12mA) capabilities. See the Apollo2 data sheet. 181 //! - Attempting to set the higher drive (8mA or 12mA) configuration on a 182 //! non-supporting pad will actually set the pad for 4mA drive strength, 183 //! regardless of the lower bit setting. 184 // 185 //***************************************************************************** 186 #define AM_HAL_GPIO_DRIVE_2MA ( 0 ) 187 #define AM_HAL_GPIO_DRIVE_4MA AM_HAL_GPIO_HIGH_DRIVE 188 #define AM_HAL_GPIO_DRIVE_8MA ( 0x01 << CFGVAL_ALTPAD_S ) 189 #define AM_HAL_GPIO_DRIVE_12MA ( (0x01 << CFGVAL_ALTPAD_S) | \ 190 AM_HAL_GPIO_HIGH_DRIVE ) 191 192 #define AM_HAL_GPIO_SLEWRATE ( 0x10 << CFGVAL_ALTPAD_S ) 193 194 //***************************************************************************** 195 // 196 // Interrupt polarity 197 // These values can be used directly in the configval. 198 // 199 //***************************************************************************** 200 #define AM_HAL_GPIOCFGVAL_FALLING ((1 << 2) << CFGVAL_GPIOCFG_S) 201 #define AM_HAL_GPIOCFGVAL_RISING ((0 << 2) << CFGVAL_GPIOCFG_S) 202 203 //***************************************************************************** 204 // 205 // Pad function select 206 // This macro represents the 3 bit function select field in the PADREG byte. 207 // 208 //***************************************************************************** 209 #define AM_HAL_GPIO_FUNC(x) ((x & 0x7) << 3) 210 211 //***************************************************************************** 212 // 213 //! Interrupt polarity 214 //! 215 //! Important: 216 //! These values are to be used with am_hal_gpio_int_polarity_bit_set(). 217 // They are not intended to be used as part of the GPIO configval. 218 // 219 //***************************************************************************** 220 #define AM_HAL_GPIO_FALLING 0x00000001 221 #define AM_HAL_GPIO_RISING 0x00000000 222 223 //***************************************************************************** 224 // 225 // A few common pin configurations. 226 // 227 //***************************************************************************** 228 #define AM_HAL_GPIO_DISABLE \ 229 (AM_HAL_GPIO_FUNC(3)) 230 231 #define AM_HAL_GPIO_INPUT \ 232 (AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_INPEN) 233 234 #define AM_HAL_GPIO_OUTPUT \ 235 (AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_OUT_PUSHPULL) 236 237 #define AM_HAL_GPIO_OPENDRAIN \ 238 (AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_OUT_OPENDRAIN | AM_HAL_GPIO_INPEN) 239 240 #define AM_HAL_GPIO_3STATE \ 241 (AM_HAL_GPIO_FUNC(3) | AM_HAL_GPIO_OUT_3STATE) 242 243 //***************************************************************************** 244 // 245 // PADREG helper macros. 246 // 247 //***************************************************************************** 248 #define AM_HAL_GPIO_PADREG(n) \ 249 (AM_REG_GPIOn(0) + AM_REG_GPIO_PADREGA_O + (n & 0xFC)) 250 251 #define AM_HAL_GPIO_PADREG_S(n) \ 252 (((uint32_t)(n) % 4) << 3) 253 254 #define AM_HAL_GPIO_PADREG_M(n) \ 255 ((uint32_t) 0xFF << AM_HAL_GPIO_PADREG_S(n)) 256 257 #define AM_HAL_GPIO_PADREG_FIELD(n, configval) \ 258 (((uint32_t)(configval) & CFGVAL_PADREG_M) << AM_HAL_GPIO_PADREG_S(n)) 259 260 #define AM_HAL_GPIO_PADREG_W(n, configval) \ 261 AM_REGVAL(AM_HAL_GPIO_PADREG(n)) = \ 262 (AM_HAL_GPIO_PADREG_FIELD(n, configval) | \ 263 (AM_REGVAL(AM_HAL_GPIO_PADREG(n)) & ~AM_HAL_GPIO_PADREG_M(n))) 264 265 #define AM_HAL_GPIO_PADREG_R(n) \ 266 ((AM_REGVAL(AM_HAL_GPIO_PADREG(n)) & AM_HAL_GPIO_PADREG_M(n)) >> \ 267 AM_HAL_GPIO_PADREG_S(n)) 268 269 270 //***************************************************************************** 271 // 272 // ALTPADCFG helper macros. 273 // The ALTPADCFG bits are located in [23:16] of the configval. 274 // 275 //***************************************************************************** 276 #define AM_HAL_GPIO_ALTPADREG(n) \ 277 (AM_REG_GPIOn(0) + AM_REG_GPIO_ALTPADCFGA_O + (n & 0xFC)) 278 279 #define AM_HAL_GPIO_ALTPADREG_S(n) \ 280 (((uint32_t)(n) % 4) << 3) 281 282 #define AM_HAL_GPIO_ALTPADREG_M(n) \ 283 ((uint32_t) 0xFF << AM_HAL_GPIO_ALTPADREG_S(n)) 284 285 #define AM_HAL_GPIO_ALTPADREG_FIELD(n, configval) \ 286 (CFGVAL_ALTPAD_X(configval) << AM_HAL_GPIO_ALTPADREG_S(n)) 287 288 #define AM_HAL_GPIO_ALTPADREG_W(n, configval) \ 289 AM_REGVAL(AM_HAL_GPIO_ALTPADREG(n)) = \ 290 (AM_HAL_GPIO_ALTPADREG_FIELD(n, configval) | \ 291 (AM_REGVAL(AM_HAL_GPIO_ALTPADREG(n)) & ~AM_HAL_GPIO_ALTPADREG_M(n))) 292 293 #define AM_HAL_GPIO_ALTPADREG_R(n) \ 294 ((AM_REGVAL(AM_HAL_GPIO_ALTPADREG(n)) & AM_HAL_GPIO_ALTPADREG_M(n)) >> \ 295 AM_HAL_GPIO_ALTPADREG_S(n)) 296 297 //***************************************************************************** 298 // 299 // CFG helper macros. 300 // 301 //***************************************************************************** 302 #define AM_HAL_GPIO_CFG(n) \ 303 (AM_REG_GPIOn(0) + AM_REG_GPIO_CFGA_O + ((n & 0xF8) >> 1)) 304 305 #define AM_HAL_GPIO_CFG_S(n) \ 306 (((uint32_t)(n) % 8) << 2) 307 308 #define AM_HAL_GPIO_CFG_M(n) \ 309 ((uint32_t) 0x7 << AM_HAL_GPIO_CFG_S(n)) 310 311 #define AM_HAL_GPIO_CFG_FIELD(n, configval) \ 312 ((((uint32_t)(configval) & 0x700) >> 8) << AM_HAL_GPIO_CFG_S(n)) 313 314 #define AM_HAL_GPIO_CFG_W(n, configval) \ 315 AM_REGVAL(AM_HAL_GPIO_CFG(n)) = \ 316 (AM_HAL_GPIO_CFG_FIELD(n, configval) | \ 317 (AM_REGVAL(AM_HAL_GPIO_CFG(n)) & ~AM_HAL_GPIO_CFG_M(n))) 318 319 #define AM_HAL_GPIO_CFG_R(n) \ 320 ((AM_REGVAL(AM_HAL_GPIO_CFG(n)) & AM_HAL_GPIO_CFG_M(n)) >> \ 321 AM_HAL_GPIO_CFG_S(n)) 322 323 //***************************************************************************** 324 // 325 // Polarity helper macros. 326 // 327 //***************************************************************************** 328 #define AM_HAL_GPIO_POL_S(n) \ 329 ((((uint32_t)(n) % 8) << 2) + 3) 330 331 #define AM_HAL_GPIO_POL_M(n) \ 332 ((uint32_t) 0x1 << AM_HAL_GPIO_POL_S(n)) 333 334 #define AM_HAL_GPIO_POL_FIELD(n, polarity) \ 335 (((uint32_t)(polarity) & 0x1) << AM_HAL_GPIO_POL_S(n)) 336 337 #define AM_HAL_GPIO_POL_W(n, polarity) \ 338 AM_REGVAL(AM_HAL_GPIO_CFG(n)) = \ 339 (AM_HAL_GPIO_POL_FIELD(n, polarity) | \ 340 (AM_REGVAL(AM_HAL_GPIO_CFG(n)) & ~AM_HAL_GPIO_POL_M(n))) 341 342 //***************************************************************************** 343 // 344 // RD helper macros. 345 // 346 //***************************************************************************** 347 #define AM_HAL_GPIO_RD_REG(n) \ 348 (AM_REG_GPIOn(0) + AM_REG_GPIO_RDA_O + (((uint32_t)(n) & 0x20) >> 3)) 349 350 #define AM_HAL_GPIO_RD_S(n) \ 351 ((uint32_t)(n) % 32) 352 353 #define AM_HAL_GPIO_RD_M(n) \ 354 ((uint32_t) 0x1 << AM_HAL_GPIO_RD_S(n)) 355 356 #define AM_HAL_GPIO_RD(n) \ 357 AM_REGVAL(AM_HAL_GPIO_RD_REG(n)) 358 359 //***************************************************************************** 360 // 361 // WT helper macros. 362 // 363 //***************************************************************************** 364 #define AM_HAL_GPIO_WT_REG(n) \ 365 (AM_REG_GPIOn(0) + AM_REG_GPIO_WTA_O + (((uint32_t)(n) & 0x20) >> 3)) 366 367 #define AM_HAL_GPIO_WT_S(n) \ 368 ((uint32_t)(n) % 32) 369 370 #define AM_HAL_GPIO_WT_M(n) \ 371 ((uint32_t) 0x1 << AM_HAL_GPIO_WT_S(n)) 372 373 #define AM_HAL_GPIO_WT(n) \ 374 AM_REGVAL(AM_HAL_GPIO_WT_REG(n)) 375 376 //***************************************************************************** 377 // 378 // WTS helper macros. 379 // 380 //***************************************************************************** 381 #define AM_HAL_GPIO_WTS_REG(n) \ 382 (AM_REG_GPIOn(0) + AM_REG_GPIO_WTSA_O + (((uint32_t)(n) & 0x20) >> 3)) 383 384 #define AM_HAL_GPIO_WTS_S(n) \ 385 ((uint32_t)(n) % 32) 386 387 #define AM_HAL_GPIO_WTS_M(n) \ 388 ((uint32_t) 0x1 << AM_HAL_GPIO_WTS_S(n)) 389 390 #define AM_HAL_GPIO_WTS(n) \ 391 AM_REGVAL(AM_HAL_GPIO_WTS_REG(n)) 392 393 //***************************************************************************** 394 // 395 // WTC helper macros. 396 // 397 //***************************************************************************** 398 #define AM_HAL_GPIO_WTC_REG(n) \ 399 (AM_REG_GPIOn(0) + AM_REG_GPIO_WTCA_O + (((uint32_t)(n) & 0x20) >> 3)) 400 401 #define AM_HAL_GPIO_WTC_S(n) \ 402 ((uint32_t)(n) % 32) 403 404 #define AM_HAL_GPIO_WTC_M(n) \ 405 ((uint32_t) 0x1 << AM_HAL_GPIO_WTC_S(n)) 406 407 #define AM_HAL_GPIO_WTC(n) \ 408 AM_REGVAL(AM_HAL_GPIO_WTC_REG(n)) 409 410 //***************************************************************************** 411 // 412 // EN helper macros. 413 // 414 //***************************************************************************** 415 #define AM_HAL_GPIO_EN_REG(n) \ 416 (AM_REG_GPIOn(0) + AM_REG_GPIO_ENA_O + (((uint32_t)(n) & 0x20) >> 3)) 417 418 #define AM_HAL_GPIO_EN_S(n) \ 419 ((uint32_t)(n) % 32) 420 421 #define AM_HAL_GPIO_EN_M(n) \ 422 ((uint32_t) 0x1 << AM_HAL_GPIO_EN_S(n)) 423 424 #define AM_HAL_GPIO_EN(n) \ 425 AM_REGVAL(AM_HAL_GPIO_EN_REG(n)) 426 427 //***************************************************************************** 428 // 429 // ENS helper macros. 430 // 431 //***************************************************************************** 432 #define AM_HAL_GPIO_ENS_REG(n) \ 433 (AM_REG_GPIOn(0) + AM_REG_GPIO_ENSA_O + (((uint32_t)(n) & 0x20) >> 3)) 434 435 #define AM_HAL_GPIO_ENS_S(n) \ 436 ((uint32_t)(n) % 32) 437 438 #define AM_HAL_GPIO_ENS_M(n) \ 439 ((uint32_t) 0x1 << AM_HAL_GPIO_ENS_S(n)) 440 441 #define AM_HAL_GPIO_ENS(n) \ 442 AM_REGVAL(AM_HAL_GPIO_ENS_REG(n)) 443 444 //***************************************************************************** 445 // 446 // ENC helper macros. 447 // 448 //***************************************************************************** 449 #define AM_HAL_GPIO_ENC_REG(n) \ 450 (AM_REG_GPIOn(0) + AM_REG_GPIO_ENCA_O + (((uint32_t)(n) & 0x20) >> 3)) 451 452 #define AM_HAL_GPIO_ENC_S(n) \ 453 ((uint32_t)(n) % 32) 454 455 #define AM_HAL_GPIO_ENC_M(n) \ 456 ((uint32_t) 0x1 << AM_HAL_GPIO_ENC_S(n)) 457 458 #define AM_HAL_GPIO_ENC(n) \ 459 AM_REGVAL(AM_HAL_GPIO_ENC_REG(n)) 460 461 //***************************************************************************** 462 // 463 //! @brief Configure the GPIO PAD MUX & GPIO PIN Configurations 464 //! 465 //! @param ui32PinNumber - GPIO pin number. 466 //! @param ui32Config - Configuration options. 467 //! 468 //! This function applies the settings for a single GPIO. For a list of valid 469 //! options please see the top of this file (am_hal_gpio.h) and am_hal_pin.h. 470 //! 471 //! Usage examples: 472 //! am_hal_gpio_pin_config(11, AM_HAL_GPIO_INPUT); 473 //! am_hal_gpio_pin_config(10, AM_HAL_GPIO_OUTPUT); 474 //! am_hal_gpio_pin_config(14, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_SLEWRATE); 475 //! am_hal_gpio_pin_config(15, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_HIGHDRIVESTR); 476 // 477 //***************************************************************************** 478 #define am_hal_gpio_pin_config(ui32PinNumber, ui32Config) \ 479 if ( (uint32_t)(ui32PinNumber) < AM_HAL_GPIO_MAX_PADS ) \ 480 { \ 481 AM_CRITICAL_BEGIN_ASM \ 482 \ 483 AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; \ 484 \ 485 AM_HAL_GPIO_CFG_W(ui32PinNumber, ui32Config); \ 486 AM_HAL_GPIO_PADREG_W(ui32PinNumber, ui32Config); \ 487 AM_HAL_GPIO_ALTPADREG_W(ui32PinNumber, ui32Config); \ 488 \ 489 AM_REGn(GPIO, 0, PADKEY) = 0; \ 490 \ 491 AM_CRITICAL_END_ASM \ 492 } 493 494 //***************************************************************************** 495 // 496 //! @brief Set the state of one GPIO polarity bit. 497 //! 498 //! @param ui32BitNum - GPIO number. 499 //! @param ui32Polarity - Desired state. 500 //! 501 //! This function sets the state of one GPIO polarity bit to a supplied value. 502 //! The ui32Polarity parameter should be one of the following values: 503 //! 504 //! AM_HAL_GPIO_FALLING 505 //! AM_HAL_GPIO_RISING 506 //! 507 //! @return None. 508 // 509 //***************************************************************************** 510 #define am_hal_gpio_int_polarity_bit_set(ui32BitNum, ui32Polarity) \ 511 if ( (uint32_t)(ui32BitNum) < AM_HAL_GPIO_MAX_PADS ) \ 512 { \ 513 AM_CRITICAL_BEGIN_ASM \ 514 \ 515 AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; \ 516 AM_HAL_GPIO_POL_W(ui32BitNum, ui32Polarity); \ 517 AM_REGn(GPIO, 0, PADKEY) = 0; \ 518 \ 519 AM_CRITICAL_END_ASM \ 520 } 521 522 //***************************************************************************** 523 // 524 //! @brief Get the state of one GPIO from the INPUT READ REGISTER. 525 //! 526 //! @param ui32BitNum - GPIO number. 527 //! 528 //! This function retrieves the state of one GPIO from the INPUT READ 529 //! REGISTER. 530 //! 531 //! @return the state for the requested GPIO. 532 // 533 //***************************************************************************** 534 #define am_hal_gpio_input_bit_read(ui32BitNum) \ 535 ((AM_HAL_GPIO_RD(ui32BitNum) & AM_HAL_GPIO_RD_M(ui32BitNum)) != 0) 536 537 //***************************************************************************** 538 // 539 //! @brief Get the state of one GPIO in the DATA OUTPUT REGISTER 540 //! 541 //! @param ui32BitNum - GPIO number. 542 //! 543 //! This function retrieves the state of one GPIO in the DATA OUTPUT REGISTER. 544 //! 545 //! @return the state for the requested GPIO or -1 for error. 546 // 547 //***************************************************************************** 548 #define am_hal_gpio_out_bit_read(ui32BitNum) \ 549 ((AM_HAL_GPIO_WT(ui32BitNum) & AM_HAL_GPIO_WT_M(ui32BitNum)) != 0) 550 551 //***************************************************************************** 552 // 553 //! @brief Set the output state high for one GPIO. 554 //! 555 //! @param ui32BitNum - GPIO number. 556 //! 557 //! This function sets the output state to high for one GPIO. 558 //! 559 //! @return None. 560 // 561 //***************************************************************************** 562 #define am_hal_gpio_out_bit_set(ui32BitNum) \ 563 AM_HAL_GPIO_WTS(ui32BitNum) = AM_HAL_GPIO_WTS_M(ui32BitNum) 564 565 //***************************************************************************** 566 // 567 //! @brief Sets the output state to low for one GPIO. 568 //! 569 //! @param ui32BitNum - GPIO number. 570 //! 571 //! This function sets the output state to low for one GPIO. 572 //! 573 //! @return None. 574 // 575 //***************************************************************************** 576 #define am_hal_gpio_out_bit_clear(ui32BitNum) \ 577 AM_HAL_GPIO_WTC(ui32BitNum) = AM_HAL_GPIO_WTC_M(ui32BitNum) 578 579 //***************************************************************************** 580 // 581 //! @brief Sets the output state to ui32Value for one GPIO. 582 //! 583 //! @param ui32BitNum - GPIO number. 584 //! @param ui32Value - Desired output state. 585 //! 586 //! This function sets the output state to ui32Value for one GPIO. 587 //! 588 //! @return None. 589 // 590 //***************************************************************************** 591 #define am_hal_gpio_out_bit_replace(ui32BitNum, ui32Value) \ 592 if ( ui32Value ) \ 593 { \ 594 AM_HAL_GPIO_WTS(ui32BitNum) = AM_HAL_GPIO_WTS_M(ui32BitNum); \ 595 } \ 596 else \ 597 { \ 598 AM_HAL_GPIO_WTC(ui32BitNum) = AM_HAL_GPIO_WTC_M(ui32BitNum); \ 599 } 600 601 //***************************************************************************** 602 // 603 //! @brief Toggle the output state of one GPIO. 604 //! 605 //! @param ui32BitNum - GPIO number. 606 //! 607 //! This function toggles the output state of one GPIO. 608 //! 609 //! @return None. 610 // 611 //***************************************************************************** 612 #define am_hal_gpio_out_bit_toggle(ui32BitNum) \ 613 if ( 1 ) \ 614 { \ 615 AM_CRITICAL_BEGIN_ASM \ 616 AM_HAL_GPIO_WT(ui32BitNum) ^= AM_HAL_GPIO_WT_M(ui32BitNum); \ 617 AM_CRITICAL_END_ASM \ 618 } 619 620 //***************************************************************************** 621 // 622 //! @brief Sets the output enable for one GPIO. 623 //! 624 //! @param ui32BitNum - GPIO number. 625 //! 626 //! This function sets the output enable for one GPIO. 627 //! 628 //! @return None. 629 // 630 //***************************************************************************** 631 #define am_hal_gpio_out_enable_bit_set(ui32BitNum) \ 632 AM_HAL_GPIO_ENS(ui32BitNum) = AM_HAL_GPIO_ENS_M(ui32BitNum) 633 634 //***************************************************************************** 635 // 636 //! @brief Clears the output enable for one GPIO. 637 //! 638 //! @param ui32BitNum - GPIO number. 639 //! 640 //! This function clears the output enable for one GPIO. 641 //! 642 //! @return None. 643 // 644 //***************************************************************************** 645 #define am_hal_gpio_out_enable_bit_clear(ui32BitNum) \ 646 AM_HAL_GPIO_ENC(ui32BitNum) = AM_HAL_GPIO_ENC_M(ui32BitNum) 647 648 //***************************************************************************** 649 // 650 // Function pointer type for GPIO interrupt handlers. 651 // 652 //***************************************************************************** 653 typedef void (*am_hal_gpio_handler_t)(void); 654 655 //***************************************************************************** 656 // 657 // External function prototypes 658 // 659 //***************************************************************************** 660 #ifdef __cplusplus 661 extern "C" 662 { 663 #endif 664 665 extern uint32_t am_hal_gpio_pin_config_read(uint32_t ui32PinNumber); 666 extern uint64_t am_hal_gpio_input_read(void); 667 extern uint64_t am_hal_gpio_out_read(void); 668 extern uint32_t am_hal_gpio_out_enable_bit_get(uint32_t ui32BitNum); 669 extern uint64_t am_hal_gpio_out_enable_get(void); 670 extern void am_hal_gpio_int_enable(uint64_t ui64InterruptMask); 671 extern uint64_t am_hal_gpio_int_enable_get(void); 672 extern void am_hal_gpio_int_disable(uint64_t ui64InterruptMask); 673 extern void am_hal_gpio_int_clear(uint64_t ui64InterruptMask); 674 extern void am_hal_gpio_int_set(uint64_t ui64InterruptMask); 675 extern uint64_t am_hal_gpio_int_status_get(bool bEnabledOnly); 676 extern void am_hal_gpio_int_service(uint64_t ui64Status); 677 extern void am_hal_gpio_int_register(uint32_t ui32GPIONumber, 678 am_hal_gpio_handler_t pfnHandler); 679 680 extern bool am_hal_gpio_int_polarity_bit_get(uint32_t ui32BitNum); 681 682 #ifdef __cplusplus 683 } 684 #endif 685 686 #endif // AM_HAL_GPIO_H 687 688 //***************************************************************************** 689 // 690 // End Doxygen group. 691 //! @} 692 // 693 //***************************************************************************** 694