1 //***************************************************************************** 2 // 3 // am_reg_adc.h 4 //! @file 5 //! 6 //! @brief Register macros for the ADC module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_ADC_H 45 #define AM_REG_ADC_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_ADC_NUM_MODULES 1 53 #define AM_REG_ADCn(n) \ 54 (REG_ADC_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_ADC_CFG_O 0x00000000 62 #define AM_REG_ADC_STAT_O 0x00000004 63 #define AM_REG_ADC_SWT_O 0x00000008 64 #define AM_REG_ADC_SL0CFG_O 0x0000000C 65 #define AM_REG_ADC_SL1CFG_O 0x00000010 66 #define AM_REG_ADC_SL2CFG_O 0x00000014 67 #define AM_REG_ADC_SL3CFG_O 0x00000018 68 #define AM_REG_ADC_SL4CFG_O 0x0000001C 69 #define AM_REG_ADC_SL5CFG_O 0x00000020 70 #define AM_REG_ADC_SL6CFG_O 0x00000024 71 #define AM_REG_ADC_SL7CFG_O 0x00000028 72 #define AM_REG_ADC_WULIM_O 0x0000002C 73 #define AM_REG_ADC_WLLIM_O 0x00000030 74 #define AM_REG_ADC_FIFO_O 0x00000038 75 #define AM_REG_ADC_INTEN_O 0x00000200 76 #define AM_REG_ADC_INTSTAT_O 0x00000204 77 #define AM_REG_ADC_INTCLR_O 0x00000208 78 #define AM_REG_ADC_INTSET_O 0x0000020C 79 80 //***************************************************************************** 81 // 82 // ADC_INTEN - ADC Interrupt registers: Enable 83 // 84 //***************************************************************************** 85 // Window comparator voltage incursion interrupt. 86 #define AM_REG_ADC_INTEN_WCINC_S 5 87 #define AM_REG_ADC_INTEN_WCINC_M 0x00000020 88 #define AM_REG_ADC_INTEN_WCINC(n) (((uint32_t)(n) << 5) & 0x00000020) 89 #define AM_REG_ADC_INTEN_WCINC_WCINCINT 0x00000020 90 91 // Window comparator voltage excursion interrupt. 92 #define AM_REG_ADC_INTEN_WCEXC_S 4 93 #define AM_REG_ADC_INTEN_WCEXC_M 0x00000010 94 #define AM_REG_ADC_INTEN_WCEXC(n) (((uint32_t)(n) << 4) & 0x00000010) 95 #define AM_REG_ADC_INTEN_WCEXC_WCEXCINT 0x00000010 96 97 // FIFO 100 percent full interrupt. 98 #define AM_REG_ADC_INTEN_FIFOOVR2_S 3 99 #define AM_REG_ADC_INTEN_FIFOOVR2_M 0x00000008 100 #define AM_REG_ADC_INTEN_FIFOOVR2(n) (((uint32_t)(n) << 3) & 0x00000008) 101 #define AM_REG_ADC_INTEN_FIFOOVR2_FIFOFULLINT 0x00000008 102 103 // FIFO 75 percent full interrupt. 104 #define AM_REG_ADC_INTEN_FIFOOVR1_S 2 105 #define AM_REG_ADC_INTEN_FIFOOVR1_M 0x00000004 106 #define AM_REG_ADC_INTEN_FIFOOVR1(n) (((uint32_t)(n) << 2) & 0x00000004) 107 #define AM_REG_ADC_INTEN_FIFOOVR1_FIFO75INT 0x00000004 108 109 // ADC scan complete interrupt. 110 #define AM_REG_ADC_INTEN_SCNCMP_S 1 111 #define AM_REG_ADC_INTEN_SCNCMP_M 0x00000002 112 #define AM_REG_ADC_INTEN_SCNCMP(n) (((uint32_t)(n) << 1) & 0x00000002) 113 #define AM_REG_ADC_INTEN_SCNCMP_SCNCMPINT 0x00000002 114 115 // ADC conversion complete interrupt. 116 #define AM_REG_ADC_INTEN_CNVCMP_S 0 117 #define AM_REG_ADC_INTEN_CNVCMP_M 0x00000001 118 #define AM_REG_ADC_INTEN_CNVCMP(n) (((uint32_t)(n) << 0) & 0x00000001) 119 #define AM_REG_ADC_INTEN_CNVCMP_CNVCMPINT 0x00000001 120 121 //***************************************************************************** 122 // 123 // ADC_INTSTAT - ADC Interrupt registers: Status 124 // 125 //***************************************************************************** 126 // Window comparator voltage incursion interrupt. 127 #define AM_REG_ADC_INTSTAT_WCINC_S 5 128 #define AM_REG_ADC_INTSTAT_WCINC_M 0x00000020 129 #define AM_REG_ADC_INTSTAT_WCINC(n) (((uint32_t)(n) << 5) & 0x00000020) 130 #define AM_REG_ADC_INTSTAT_WCINC_WCINCINT 0x00000020 131 132 // Window comparator voltage excursion interrupt. 133 #define AM_REG_ADC_INTSTAT_WCEXC_S 4 134 #define AM_REG_ADC_INTSTAT_WCEXC_M 0x00000010 135 #define AM_REG_ADC_INTSTAT_WCEXC(n) (((uint32_t)(n) << 4) & 0x00000010) 136 #define AM_REG_ADC_INTSTAT_WCEXC_WCEXCINT 0x00000010 137 138 // FIFO 100 percent full interrupt. 139 #define AM_REG_ADC_INTSTAT_FIFOOVR2_S 3 140 #define AM_REG_ADC_INTSTAT_FIFOOVR2_M 0x00000008 141 #define AM_REG_ADC_INTSTAT_FIFOOVR2(n) (((uint32_t)(n) << 3) & 0x00000008) 142 #define AM_REG_ADC_INTSTAT_FIFOOVR2_FIFOFULLINT 0x00000008 143 144 // FIFO 75 percent full interrupt. 145 #define AM_REG_ADC_INTSTAT_FIFOOVR1_S 2 146 #define AM_REG_ADC_INTSTAT_FIFOOVR1_M 0x00000004 147 #define AM_REG_ADC_INTSTAT_FIFOOVR1(n) (((uint32_t)(n) << 2) & 0x00000004) 148 #define AM_REG_ADC_INTSTAT_FIFOOVR1_FIFO75INT 0x00000004 149 150 // ADC scan complete interrupt. 151 #define AM_REG_ADC_INTSTAT_SCNCMP_S 1 152 #define AM_REG_ADC_INTSTAT_SCNCMP_M 0x00000002 153 #define AM_REG_ADC_INTSTAT_SCNCMP(n) (((uint32_t)(n) << 1) & 0x00000002) 154 #define AM_REG_ADC_INTSTAT_SCNCMP_SCNCMPINT 0x00000002 155 156 // ADC conversion complete interrupt. 157 #define AM_REG_ADC_INTSTAT_CNVCMP_S 0 158 #define AM_REG_ADC_INTSTAT_CNVCMP_M 0x00000001 159 #define AM_REG_ADC_INTSTAT_CNVCMP(n) (((uint32_t)(n) << 0) & 0x00000001) 160 #define AM_REG_ADC_INTSTAT_CNVCMP_CNVCMPINT 0x00000001 161 162 //***************************************************************************** 163 // 164 // ADC_INTCLR - ADC Interrupt registers: Clear 165 // 166 //***************************************************************************** 167 // Window comparator voltage incursion interrupt. 168 #define AM_REG_ADC_INTCLR_WCINC_S 5 169 #define AM_REG_ADC_INTCLR_WCINC_M 0x00000020 170 #define AM_REG_ADC_INTCLR_WCINC(n) (((uint32_t)(n) << 5) & 0x00000020) 171 #define AM_REG_ADC_INTCLR_WCINC_WCINCINT 0x00000020 172 173 // Window comparator voltage excursion interrupt. 174 #define AM_REG_ADC_INTCLR_WCEXC_S 4 175 #define AM_REG_ADC_INTCLR_WCEXC_M 0x00000010 176 #define AM_REG_ADC_INTCLR_WCEXC(n) (((uint32_t)(n) << 4) & 0x00000010) 177 #define AM_REG_ADC_INTCLR_WCEXC_WCEXCINT 0x00000010 178 179 // FIFO 100 percent full interrupt. 180 #define AM_REG_ADC_INTCLR_FIFOOVR2_S 3 181 #define AM_REG_ADC_INTCLR_FIFOOVR2_M 0x00000008 182 #define AM_REG_ADC_INTCLR_FIFOOVR2(n) (((uint32_t)(n) << 3) & 0x00000008) 183 #define AM_REG_ADC_INTCLR_FIFOOVR2_FIFOFULLINT 0x00000008 184 185 // FIFO 75 percent full interrupt. 186 #define AM_REG_ADC_INTCLR_FIFOOVR1_S 2 187 #define AM_REG_ADC_INTCLR_FIFOOVR1_M 0x00000004 188 #define AM_REG_ADC_INTCLR_FIFOOVR1(n) (((uint32_t)(n) << 2) & 0x00000004) 189 #define AM_REG_ADC_INTCLR_FIFOOVR1_FIFO75INT 0x00000004 190 191 // ADC scan complete interrupt. 192 #define AM_REG_ADC_INTCLR_SCNCMP_S 1 193 #define AM_REG_ADC_INTCLR_SCNCMP_M 0x00000002 194 #define AM_REG_ADC_INTCLR_SCNCMP(n) (((uint32_t)(n) << 1) & 0x00000002) 195 #define AM_REG_ADC_INTCLR_SCNCMP_SCNCMPINT 0x00000002 196 197 // ADC conversion complete interrupt. 198 #define AM_REG_ADC_INTCLR_CNVCMP_S 0 199 #define AM_REG_ADC_INTCLR_CNVCMP_M 0x00000001 200 #define AM_REG_ADC_INTCLR_CNVCMP(n) (((uint32_t)(n) << 0) & 0x00000001) 201 #define AM_REG_ADC_INTCLR_CNVCMP_CNVCMPINT 0x00000001 202 203 //***************************************************************************** 204 // 205 // ADC_INTSET - ADC Interrupt registers: Set 206 // 207 //***************************************************************************** 208 // Window comparator voltage incursion interrupt. 209 #define AM_REG_ADC_INTSET_WCINC_S 5 210 #define AM_REG_ADC_INTSET_WCINC_M 0x00000020 211 #define AM_REG_ADC_INTSET_WCINC(n) (((uint32_t)(n) << 5) & 0x00000020) 212 #define AM_REG_ADC_INTSET_WCINC_WCINCINT 0x00000020 213 214 // Window comparator voltage excursion interrupt. 215 #define AM_REG_ADC_INTSET_WCEXC_S 4 216 #define AM_REG_ADC_INTSET_WCEXC_M 0x00000010 217 #define AM_REG_ADC_INTSET_WCEXC(n) (((uint32_t)(n) << 4) & 0x00000010) 218 #define AM_REG_ADC_INTSET_WCEXC_WCEXCINT 0x00000010 219 220 // FIFO 100 percent full interrupt. 221 #define AM_REG_ADC_INTSET_FIFOOVR2_S 3 222 #define AM_REG_ADC_INTSET_FIFOOVR2_M 0x00000008 223 #define AM_REG_ADC_INTSET_FIFOOVR2(n) (((uint32_t)(n) << 3) & 0x00000008) 224 #define AM_REG_ADC_INTSET_FIFOOVR2_FIFOFULLINT 0x00000008 225 226 // FIFO 75 percent full interrupt. 227 #define AM_REG_ADC_INTSET_FIFOOVR1_S 2 228 #define AM_REG_ADC_INTSET_FIFOOVR1_M 0x00000004 229 #define AM_REG_ADC_INTSET_FIFOOVR1(n) (((uint32_t)(n) << 2) & 0x00000004) 230 #define AM_REG_ADC_INTSET_FIFOOVR1_FIFO75INT 0x00000004 231 232 // ADC scan complete interrupt. 233 #define AM_REG_ADC_INTSET_SCNCMP_S 1 234 #define AM_REG_ADC_INTSET_SCNCMP_M 0x00000002 235 #define AM_REG_ADC_INTSET_SCNCMP(n) (((uint32_t)(n) << 1) & 0x00000002) 236 #define AM_REG_ADC_INTSET_SCNCMP_SCNCMPINT 0x00000002 237 238 // ADC conversion complete interrupt. 239 #define AM_REG_ADC_INTSET_CNVCMP_S 0 240 #define AM_REG_ADC_INTSET_CNVCMP_M 0x00000001 241 #define AM_REG_ADC_INTSET_CNVCMP(n) (((uint32_t)(n) << 0) & 0x00000001) 242 #define AM_REG_ADC_INTSET_CNVCMP_CNVCMPINT 0x00000001 243 244 //***************************************************************************** 245 // 246 // ADC_CFG - Configuration Register 247 // 248 //***************************************************************************** 249 // Select the source and frequency for the ADC clock. All values not enumerated 250 // below are undefined. 251 #define AM_REG_ADC_CFG_CLKSEL_S 24 252 #define AM_REG_ADC_CFG_CLKSEL_M 0x03000000 253 #define AM_REG_ADC_CFG_CLKSEL(n) (((uint32_t)(n) << 24) & 0x03000000) 254 #define AM_REG_ADC_CFG_CLKSEL_OFF 0x00000000 255 #define AM_REG_ADC_CFG_CLKSEL_HFRC 0x01000000 256 #define AM_REG_ADC_CFG_CLKSEL_HFRC_DIV2 0x02000000 257 258 // This bit selects the ADC trigger polarity for external off chip triggers. 259 #define AM_REG_ADC_CFG_TRIGPOL_S 19 260 #define AM_REG_ADC_CFG_TRIGPOL_M 0x00080000 261 #define AM_REG_ADC_CFG_TRIGPOL(n) (((uint32_t)(n) << 19) & 0x00080000) 262 #define AM_REG_ADC_CFG_TRIGPOL_RISING_EDGE 0x00000000 263 #define AM_REG_ADC_CFG_TRIGPOL_FALLING_EDGE 0x00080000 264 265 // Select the ADC trigger source. 266 #define AM_REG_ADC_CFG_TRIGSEL_S 16 267 #define AM_REG_ADC_CFG_TRIGSEL_M 0x00070000 268 #define AM_REG_ADC_CFG_TRIGSEL(n) (((uint32_t)(n) << 16) & 0x00070000) 269 #define AM_REG_ADC_CFG_TRIGSEL_EXT0 0x00000000 270 #define AM_REG_ADC_CFG_TRIGSEL_EXT1 0x00010000 271 #define AM_REG_ADC_CFG_TRIGSEL_EXT2 0x00020000 272 #define AM_REG_ADC_CFG_TRIGSEL_EXT3 0x00030000 273 #define AM_REG_ADC_CFG_TRIGSEL_VCOMP 0x00040000 274 #define AM_REG_ADC_CFG_TRIGSEL_SWT 0x00070000 275 276 // Select the ADC reference voltage. 277 #define AM_REG_ADC_CFG_REFSEL_S 8 278 #define AM_REG_ADC_CFG_REFSEL_M 0x00000300 279 #define AM_REG_ADC_CFG_REFSEL(n) (((uint32_t)(n) << 8) & 0x00000300) 280 #define AM_REG_ADC_CFG_REFSEL_INT2P0 0x00000000 281 #define AM_REG_ADC_CFG_REFSEL_INT1P5 0x00000100 282 #define AM_REG_ADC_CFG_REFSEL_EXT2P0 0x00000200 283 #define AM_REG_ADC_CFG_REFSEL_EXT1P5 0x00000300 284 285 // Clock mode register 286 #define AM_REG_ADC_CFG_CKMODE_S 4 287 #define AM_REG_ADC_CFG_CKMODE_M 0x00000010 288 #define AM_REG_ADC_CFG_CKMODE(n) (((uint32_t)(n) << 4) & 0x00000010) 289 #define AM_REG_ADC_CFG_CKMODE_LPCKMODE 0x00000000 290 #define AM_REG_ADC_CFG_CKMODE_LLCKMODE 0x00000010 291 292 // Select power mode to enter between active scans. 293 #define AM_REG_ADC_CFG_LPMODE_S 3 294 #define AM_REG_ADC_CFG_LPMODE_M 0x00000008 295 #define AM_REG_ADC_CFG_LPMODE(n) (((uint32_t)(n) << 3) & 0x00000008) 296 #define AM_REG_ADC_CFG_LPMODE_MODE0 0x00000000 297 #define AM_REG_ADC_CFG_LPMODE_MODE1 0x00000008 298 299 // This bit enables Repeating Scan Mode. 300 #define AM_REG_ADC_CFG_RPTEN_S 2 301 #define AM_REG_ADC_CFG_RPTEN_M 0x00000004 302 #define AM_REG_ADC_CFG_RPTEN(n) (((uint32_t)(n) << 2) & 0x00000004) 303 #define AM_REG_ADC_CFG_RPTEN_SINGLE_SCAN 0x00000000 304 #define AM_REG_ADC_CFG_RPTEN_REPEATING_SCAN 0x00000004 305 306 // This bit enables the ADC module. While the ADC is enabled, the ADCCFG and 307 // SLOT Configuration regsiter settings must remain stable and unchanged. All 308 // configuration register settings, slot configuration settings and window 309 // comparison settings should be written prior to setting the ADCEN bit to '1'. 310 #define AM_REG_ADC_CFG_ADCEN_S 0 311 #define AM_REG_ADC_CFG_ADCEN_M 0x00000001 312 #define AM_REG_ADC_CFG_ADCEN(n) (((uint32_t)(n) << 0) & 0x00000001) 313 #define AM_REG_ADC_CFG_ADCEN_DIS 0x00000000 314 #define AM_REG_ADC_CFG_ADCEN_EN 0x00000001 315 316 //***************************************************************************** 317 // 318 // ADC_STAT - ADC Power Status 319 // 320 //***************************************************************************** 321 // Indicates the power-status of the ADC. 322 #define AM_REG_ADC_STAT_PWDSTAT_S 0 323 #define AM_REG_ADC_STAT_PWDSTAT_M 0x00000001 324 #define AM_REG_ADC_STAT_PWDSTAT(n) (((uint32_t)(n) << 0) & 0x00000001) 325 #define AM_REG_ADC_STAT_PWDSTAT_ON 0x00000000 326 #define AM_REG_ADC_STAT_PWDSTAT_POWERED_DOWN 0x00000001 327 328 //***************************************************************************** 329 // 330 // ADC_SWT - Software trigger 331 // 332 //***************************************************************************** 333 // Writing 0x37 to this register generates a software trigger. 334 #define AM_REG_ADC_SWT_SWT_S 0 335 #define AM_REG_ADC_SWT_SWT_M 0x000000FF 336 #define AM_REG_ADC_SWT_SWT(n) (((uint32_t)(n) << 0) & 0x000000FF) 337 #define AM_REG_ADC_SWT_SWT_GEN_SW_TRIGGER 0x00000037 338 339 //***************************************************************************** 340 // 341 // ADC_SL0CFG - Slot 0 Configuration Register 342 // 343 //***************************************************************************** 344 // Select the number of measurements to average in the accumulate divide module 345 // for this slot. 346 #define AM_REG_ADC_SL0CFG_ADSEL0_S 24 347 #define AM_REG_ADC_SL0CFG_ADSEL0_M 0x07000000 348 #define AM_REG_ADC_SL0CFG_ADSEL0(n) (((uint32_t)(n) << 24) & 0x07000000) 349 #define AM_REG_ADC_SL0CFG_ADSEL0_AVG_1_MSRMT 0x00000000 350 #define AM_REG_ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS 0x01000000 351 #define AM_REG_ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS 0x02000000 352 #define AM_REG_ADC_SL0CFG_ADSEL0_AVG_8_MSRMT 0x03000000 353 #define AM_REG_ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS 0x04000000 354 #define AM_REG_ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS 0x05000000 355 #define AM_REG_ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS 0x06000000 356 #define AM_REG_ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS 0x07000000 357 358 // Set the Precision Mode For Slot. 359 #define AM_REG_ADC_SL0CFG_PRMODE0_S 16 360 #define AM_REG_ADC_SL0CFG_PRMODE0_M 0x00030000 361 #define AM_REG_ADC_SL0CFG_PRMODE0(n) (((uint32_t)(n) << 16) & 0x00030000) 362 #define AM_REG_ADC_SL0CFG_PRMODE0_P14B 0x00000000 363 #define AM_REG_ADC_SL0CFG_PRMODE0_P12B 0x00010000 364 #define AM_REG_ADC_SL0CFG_PRMODE0_P10B 0x00020000 365 #define AM_REG_ADC_SL0CFG_PRMODE0_P8B 0x00030000 366 367 // Select one of the 14 channel inputs for this slot. 368 #define AM_REG_ADC_SL0CFG_CHSEL0_S 8 369 #define AM_REG_ADC_SL0CFG_CHSEL0_M 0x00000F00 370 #define AM_REG_ADC_SL0CFG_CHSEL0(n) (((uint32_t)(n) << 8) & 0x00000F00) 371 #define AM_REG_ADC_SL0CFG_CHSEL0_SE0 0x00000000 372 #define AM_REG_ADC_SL0CFG_CHSEL0_SE1 0x00000100 373 #define AM_REG_ADC_SL0CFG_CHSEL0_SE2 0x00000200 374 #define AM_REG_ADC_SL0CFG_CHSEL0_SE3 0x00000300 375 #define AM_REG_ADC_SL0CFG_CHSEL0_SE4 0x00000400 376 #define AM_REG_ADC_SL0CFG_CHSEL0_SE5 0x00000500 377 #define AM_REG_ADC_SL0CFG_CHSEL0_SE6 0x00000600 378 #define AM_REG_ADC_SL0CFG_CHSEL0_SE7 0x00000700 379 #define AM_REG_ADC_SL0CFG_CHSEL0_SE8 0x00000800 380 #define AM_REG_ADC_SL0CFG_CHSEL0_SE9 0x00000900 381 #define AM_REG_ADC_SL0CFG_CHSEL0_DF0 0x00000A00 382 #define AM_REG_ADC_SL0CFG_CHSEL0_DF1 0x00000B00 383 #define AM_REG_ADC_SL0CFG_CHSEL0_TEMP 0x00000C00 384 #define AM_REG_ADC_SL0CFG_CHSEL0_BATT 0x00000D00 385 #define AM_REG_ADC_SL0CFG_CHSEL0_VSS 0x00000E00 386 387 // This bit enables the window compare function for slot 0. 388 #define AM_REG_ADC_SL0CFG_WCEN0_S 1 389 #define AM_REG_ADC_SL0CFG_WCEN0_M 0x00000002 390 #define AM_REG_ADC_SL0CFG_WCEN0(n) (((uint32_t)(n) << 1) & 0x00000002) 391 #define AM_REG_ADC_SL0CFG_WCEN0_WCEN 0x00000002 392 393 // This bit enables slot 0 for ADC conversions. 394 #define AM_REG_ADC_SL0CFG_SLEN0_S 0 395 #define AM_REG_ADC_SL0CFG_SLEN0_M 0x00000001 396 #define AM_REG_ADC_SL0CFG_SLEN0(n) (((uint32_t)(n) << 0) & 0x00000001) 397 #define AM_REG_ADC_SL0CFG_SLEN0_SLEN 0x00000001 398 399 //***************************************************************************** 400 // 401 // ADC_SL1CFG - Slot 1 Configuration Register 402 // 403 //***************************************************************************** 404 // Select the number of measurements to average in the accumulate divide module 405 // for this slot. 406 #define AM_REG_ADC_SL1CFG_ADSEL1_S 24 407 #define AM_REG_ADC_SL1CFG_ADSEL1_M 0x07000000 408 #define AM_REG_ADC_SL1CFG_ADSEL1(n) (((uint32_t)(n) << 24) & 0x07000000) 409 #define AM_REG_ADC_SL1CFG_ADSEL1_AVG_1_MSRMT 0x00000000 410 #define AM_REG_ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS 0x01000000 411 #define AM_REG_ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS 0x02000000 412 #define AM_REG_ADC_SL1CFG_ADSEL1_AVG_8_MSRMT 0x03000000 413 #define AM_REG_ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS 0x04000000 414 #define AM_REG_ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS 0x05000000 415 #define AM_REG_ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS 0x06000000 416 #define AM_REG_ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS 0x07000000 417 418 // Set the Precision Mode For Slot. 419 #define AM_REG_ADC_SL1CFG_PRMODE1_S 16 420 #define AM_REG_ADC_SL1CFG_PRMODE1_M 0x00030000 421 #define AM_REG_ADC_SL1CFG_PRMODE1(n) (((uint32_t)(n) << 16) & 0x00030000) 422 #define AM_REG_ADC_SL1CFG_PRMODE1_P14B 0x00000000 423 #define AM_REG_ADC_SL1CFG_PRMODE1_P12B 0x00010000 424 #define AM_REG_ADC_SL1CFG_PRMODE1_P10B 0x00020000 425 #define AM_REG_ADC_SL1CFG_PRMODE1_P8B 0x00030000 426 427 // Select one of the 14 channel inputs for this slot. 428 #define AM_REG_ADC_SL1CFG_CHSEL1_S 8 429 #define AM_REG_ADC_SL1CFG_CHSEL1_M 0x00000F00 430 #define AM_REG_ADC_SL1CFG_CHSEL1(n) (((uint32_t)(n) << 8) & 0x00000F00) 431 #define AM_REG_ADC_SL1CFG_CHSEL1_SE0 0x00000000 432 #define AM_REG_ADC_SL1CFG_CHSEL1_SE1 0x00000100 433 #define AM_REG_ADC_SL1CFG_CHSEL1_SE2 0x00000200 434 #define AM_REG_ADC_SL1CFG_CHSEL1_SE3 0x00000300 435 #define AM_REG_ADC_SL1CFG_CHSEL1_SE4 0x00000400 436 #define AM_REG_ADC_SL1CFG_CHSEL1_SE5 0x00000500 437 #define AM_REG_ADC_SL1CFG_CHSEL1_SE6 0x00000600 438 #define AM_REG_ADC_SL1CFG_CHSEL1_SE7 0x00000700 439 #define AM_REG_ADC_SL1CFG_CHSEL1_SE8 0x00000800 440 #define AM_REG_ADC_SL1CFG_CHSEL1_SE9 0x00000900 441 #define AM_REG_ADC_SL1CFG_CHSEL1_DF0 0x00000A00 442 #define AM_REG_ADC_SL1CFG_CHSEL1_DF1 0x00000B00 443 #define AM_REG_ADC_SL1CFG_CHSEL1_TEMP 0x00000C00 444 #define AM_REG_ADC_SL1CFG_CHSEL1_BATT 0x00000D00 445 #define AM_REG_ADC_SL1CFG_CHSEL1_VSS 0x00000E00 446 447 // This bit enables the window compare function for slot 1. 448 #define AM_REG_ADC_SL1CFG_WCEN1_S 1 449 #define AM_REG_ADC_SL1CFG_WCEN1_M 0x00000002 450 #define AM_REG_ADC_SL1CFG_WCEN1(n) (((uint32_t)(n) << 1) & 0x00000002) 451 #define AM_REG_ADC_SL1CFG_WCEN1_WCEN 0x00000002 452 453 // This bit enables slot 1 for ADC conversions. 454 #define AM_REG_ADC_SL1CFG_SLEN1_S 0 455 #define AM_REG_ADC_SL1CFG_SLEN1_M 0x00000001 456 #define AM_REG_ADC_SL1CFG_SLEN1(n) (((uint32_t)(n) << 0) & 0x00000001) 457 #define AM_REG_ADC_SL1CFG_SLEN1_SLEN 0x00000001 458 459 //***************************************************************************** 460 // 461 // ADC_SL2CFG - Slot 2 Configuration Register 462 // 463 //***************************************************************************** 464 // Select the number of measurements to average in the accumulate divide module 465 // for this slot. 466 #define AM_REG_ADC_SL2CFG_ADSEL2_S 24 467 #define AM_REG_ADC_SL2CFG_ADSEL2_M 0x07000000 468 #define AM_REG_ADC_SL2CFG_ADSEL2(n) (((uint32_t)(n) << 24) & 0x07000000) 469 #define AM_REG_ADC_SL2CFG_ADSEL2_AVG_1_MSRMT 0x00000000 470 #define AM_REG_ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS 0x01000000 471 #define AM_REG_ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS 0x02000000 472 #define AM_REG_ADC_SL2CFG_ADSEL2_AVG_8_MSRMT 0x03000000 473 #define AM_REG_ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS 0x04000000 474 #define AM_REG_ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS 0x05000000 475 #define AM_REG_ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS 0x06000000 476 #define AM_REG_ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS 0x07000000 477 478 // Set the Precision Mode For Slot. 479 #define AM_REG_ADC_SL2CFG_PRMODE2_S 16 480 #define AM_REG_ADC_SL2CFG_PRMODE2_M 0x00030000 481 #define AM_REG_ADC_SL2CFG_PRMODE2(n) (((uint32_t)(n) << 16) & 0x00030000) 482 #define AM_REG_ADC_SL2CFG_PRMODE2_P14B 0x00000000 483 #define AM_REG_ADC_SL2CFG_PRMODE2_P12B 0x00010000 484 #define AM_REG_ADC_SL2CFG_PRMODE2_P10B 0x00020000 485 #define AM_REG_ADC_SL2CFG_PRMODE2_P8B 0x00030000 486 487 // Select one of the 14 channel inputs for this slot. 488 #define AM_REG_ADC_SL2CFG_CHSEL2_S 8 489 #define AM_REG_ADC_SL2CFG_CHSEL2_M 0x00000F00 490 #define AM_REG_ADC_SL2CFG_CHSEL2(n) (((uint32_t)(n) << 8) & 0x00000F00) 491 #define AM_REG_ADC_SL2CFG_CHSEL2_SE0 0x00000000 492 #define AM_REG_ADC_SL2CFG_CHSEL2_SE1 0x00000100 493 #define AM_REG_ADC_SL2CFG_CHSEL2_SE2 0x00000200 494 #define AM_REG_ADC_SL2CFG_CHSEL2_SE3 0x00000300 495 #define AM_REG_ADC_SL2CFG_CHSEL2_SE4 0x00000400 496 #define AM_REG_ADC_SL2CFG_CHSEL2_SE5 0x00000500 497 #define AM_REG_ADC_SL2CFG_CHSEL2_SE6 0x00000600 498 #define AM_REG_ADC_SL2CFG_CHSEL2_SE7 0x00000700 499 #define AM_REG_ADC_SL2CFG_CHSEL2_SE8 0x00000800 500 #define AM_REG_ADC_SL2CFG_CHSEL2_SE9 0x00000900 501 #define AM_REG_ADC_SL2CFG_CHSEL2_DF0 0x00000A00 502 #define AM_REG_ADC_SL2CFG_CHSEL2_DF1 0x00000B00 503 #define AM_REG_ADC_SL2CFG_CHSEL2_TEMP 0x00000C00 504 #define AM_REG_ADC_SL2CFG_CHSEL2_BATT 0x00000D00 505 #define AM_REG_ADC_SL2CFG_CHSEL2_VSS 0x00000E00 506 507 // This bit enables the window compare function for slot 2. 508 #define AM_REG_ADC_SL2CFG_WCEN2_S 1 509 #define AM_REG_ADC_SL2CFG_WCEN2_M 0x00000002 510 #define AM_REG_ADC_SL2CFG_WCEN2(n) (((uint32_t)(n) << 1) & 0x00000002) 511 #define AM_REG_ADC_SL2CFG_WCEN2_WCEN 0x00000002 512 513 // This bit enables slot 2 for ADC conversions. 514 #define AM_REG_ADC_SL2CFG_SLEN2_S 0 515 #define AM_REG_ADC_SL2CFG_SLEN2_M 0x00000001 516 #define AM_REG_ADC_SL2CFG_SLEN2(n) (((uint32_t)(n) << 0) & 0x00000001) 517 #define AM_REG_ADC_SL2CFG_SLEN2_SLEN 0x00000001 518 519 //***************************************************************************** 520 // 521 // ADC_SL3CFG - Slot 3 Configuration Register 522 // 523 //***************************************************************************** 524 // Select the number of measurements to average in the accumulate divide module 525 // for this slot. 526 #define AM_REG_ADC_SL3CFG_ADSEL3_S 24 527 #define AM_REG_ADC_SL3CFG_ADSEL3_M 0x07000000 528 #define AM_REG_ADC_SL3CFG_ADSEL3(n) (((uint32_t)(n) << 24) & 0x07000000) 529 #define AM_REG_ADC_SL3CFG_ADSEL3_AVG_1_MSRMT 0x00000000 530 #define AM_REG_ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS 0x01000000 531 #define AM_REG_ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS 0x02000000 532 #define AM_REG_ADC_SL3CFG_ADSEL3_AVG_8_MSRMT 0x03000000 533 #define AM_REG_ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS 0x04000000 534 #define AM_REG_ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS 0x05000000 535 #define AM_REG_ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS 0x06000000 536 #define AM_REG_ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS 0x07000000 537 538 // Set the Precision Mode For Slot. 539 #define AM_REG_ADC_SL3CFG_PRMODE3_S 16 540 #define AM_REG_ADC_SL3CFG_PRMODE3_M 0x00030000 541 #define AM_REG_ADC_SL3CFG_PRMODE3(n) (((uint32_t)(n) << 16) & 0x00030000) 542 #define AM_REG_ADC_SL3CFG_PRMODE3_P14B 0x00000000 543 #define AM_REG_ADC_SL3CFG_PRMODE3_P12B 0x00010000 544 #define AM_REG_ADC_SL3CFG_PRMODE3_P10B 0x00020000 545 #define AM_REG_ADC_SL3CFG_PRMODE3_P8B 0x00030000 546 547 // Select one of the 14 channel inputs for this slot. 548 #define AM_REG_ADC_SL3CFG_CHSEL3_S 8 549 #define AM_REG_ADC_SL3CFG_CHSEL3_M 0x00000F00 550 #define AM_REG_ADC_SL3CFG_CHSEL3(n) (((uint32_t)(n) << 8) & 0x00000F00) 551 #define AM_REG_ADC_SL3CFG_CHSEL3_SE0 0x00000000 552 #define AM_REG_ADC_SL3CFG_CHSEL3_SE1 0x00000100 553 #define AM_REG_ADC_SL3CFG_CHSEL3_SE2 0x00000200 554 #define AM_REG_ADC_SL3CFG_CHSEL3_SE3 0x00000300 555 #define AM_REG_ADC_SL3CFG_CHSEL3_SE4 0x00000400 556 #define AM_REG_ADC_SL3CFG_CHSEL3_SE5 0x00000500 557 #define AM_REG_ADC_SL3CFG_CHSEL3_SE6 0x00000600 558 #define AM_REG_ADC_SL3CFG_CHSEL3_SE7 0x00000700 559 #define AM_REG_ADC_SL3CFG_CHSEL3_SE8 0x00000800 560 #define AM_REG_ADC_SL3CFG_CHSEL3_SE9 0x00000900 561 #define AM_REG_ADC_SL3CFG_CHSEL3_DF0 0x00000A00 562 #define AM_REG_ADC_SL3CFG_CHSEL3_DF1 0x00000B00 563 #define AM_REG_ADC_SL3CFG_CHSEL3_TEMP 0x00000C00 564 #define AM_REG_ADC_SL3CFG_CHSEL3_BATT 0x00000D00 565 #define AM_REG_ADC_SL3CFG_CHSEL3_VSS 0x00000E00 566 567 // This bit enables the window compare function for slot 3. 568 #define AM_REG_ADC_SL3CFG_WCEN3_S 1 569 #define AM_REG_ADC_SL3CFG_WCEN3_M 0x00000002 570 #define AM_REG_ADC_SL3CFG_WCEN3(n) (((uint32_t)(n) << 1) & 0x00000002) 571 #define AM_REG_ADC_SL3CFG_WCEN3_WCEN 0x00000002 572 573 // This bit enables slot 3 for ADC conversions. 574 #define AM_REG_ADC_SL3CFG_SLEN3_S 0 575 #define AM_REG_ADC_SL3CFG_SLEN3_M 0x00000001 576 #define AM_REG_ADC_SL3CFG_SLEN3(n) (((uint32_t)(n) << 0) & 0x00000001) 577 #define AM_REG_ADC_SL3CFG_SLEN3_SLEN 0x00000001 578 579 //***************************************************************************** 580 // 581 // ADC_SL4CFG - Slot 4 Configuration Register 582 // 583 //***************************************************************************** 584 // Select the number of measurements to average in the accumulate divide module 585 // for this slot. 586 #define AM_REG_ADC_SL4CFG_ADSEL4_S 24 587 #define AM_REG_ADC_SL4CFG_ADSEL4_M 0x07000000 588 #define AM_REG_ADC_SL4CFG_ADSEL4(n) (((uint32_t)(n) << 24) & 0x07000000) 589 #define AM_REG_ADC_SL4CFG_ADSEL4_AVG_1_MSRMT 0x00000000 590 #define AM_REG_ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS 0x01000000 591 #define AM_REG_ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS 0x02000000 592 #define AM_REG_ADC_SL4CFG_ADSEL4_AVG_8_MSRMT 0x03000000 593 #define AM_REG_ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS 0x04000000 594 #define AM_REG_ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS 0x05000000 595 #define AM_REG_ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS 0x06000000 596 #define AM_REG_ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS 0x07000000 597 598 // Set the Precision Mode For Slot. 599 #define AM_REG_ADC_SL4CFG_PRMODE4_S 16 600 #define AM_REG_ADC_SL4CFG_PRMODE4_M 0x00030000 601 #define AM_REG_ADC_SL4CFG_PRMODE4(n) (((uint32_t)(n) << 16) & 0x00030000) 602 #define AM_REG_ADC_SL4CFG_PRMODE4_P14B 0x00000000 603 #define AM_REG_ADC_SL4CFG_PRMODE4_P12B 0x00010000 604 #define AM_REG_ADC_SL4CFG_PRMODE4_P10B 0x00020000 605 #define AM_REG_ADC_SL4CFG_PRMODE4_P8B 0x00030000 606 607 // Select one of the 14 channel inputs for this slot. 608 #define AM_REG_ADC_SL4CFG_CHSEL4_S 8 609 #define AM_REG_ADC_SL4CFG_CHSEL4_M 0x00000F00 610 #define AM_REG_ADC_SL4CFG_CHSEL4(n) (((uint32_t)(n) << 8) & 0x00000F00) 611 #define AM_REG_ADC_SL4CFG_CHSEL4_SE0 0x00000000 612 #define AM_REG_ADC_SL4CFG_CHSEL4_SE1 0x00000100 613 #define AM_REG_ADC_SL4CFG_CHSEL4_SE2 0x00000200 614 #define AM_REG_ADC_SL4CFG_CHSEL4_SE3 0x00000300 615 #define AM_REG_ADC_SL4CFG_CHSEL4_SE4 0x00000400 616 #define AM_REG_ADC_SL4CFG_CHSEL4_SE5 0x00000500 617 #define AM_REG_ADC_SL4CFG_CHSEL4_SE6 0x00000600 618 #define AM_REG_ADC_SL4CFG_CHSEL4_SE7 0x00000700 619 #define AM_REG_ADC_SL4CFG_CHSEL4_SE8 0x00000800 620 #define AM_REG_ADC_SL4CFG_CHSEL4_SE9 0x00000900 621 #define AM_REG_ADC_SL4CFG_CHSEL4_DF0 0x00000A00 622 #define AM_REG_ADC_SL4CFG_CHSEL4_DF1 0x00000B00 623 #define AM_REG_ADC_SL4CFG_CHSEL4_TEMP 0x00000C00 624 #define AM_REG_ADC_SL4CFG_CHSEL4_BATT 0x00000D00 625 #define AM_REG_ADC_SL4CFG_CHSEL4_VSS 0x00000E00 626 627 // This bit enables the window compare function for slot 4. 628 #define AM_REG_ADC_SL4CFG_WCEN4_S 1 629 #define AM_REG_ADC_SL4CFG_WCEN4_M 0x00000002 630 #define AM_REG_ADC_SL4CFG_WCEN4(n) (((uint32_t)(n) << 1) & 0x00000002) 631 #define AM_REG_ADC_SL4CFG_WCEN4_WCEN 0x00000002 632 633 // This bit enables slot 4 for ADC conversions. 634 #define AM_REG_ADC_SL4CFG_SLEN4_S 0 635 #define AM_REG_ADC_SL4CFG_SLEN4_M 0x00000001 636 #define AM_REG_ADC_SL4CFG_SLEN4(n) (((uint32_t)(n) << 0) & 0x00000001) 637 #define AM_REG_ADC_SL4CFG_SLEN4_SLEN 0x00000001 638 639 //***************************************************************************** 640 // 641 // ADC_SL5CFG - Slot 5 Configuration Register 642 // 643 //***************************************************************************** 644 // Select number of measurements to average in the accumulate divide module for 645 // this slot. 646 #define AM_REG_ADC_SL5CFG_ADSEL5_S 24 647 #define AM_REG_ADC_SL5CFG_ADSEL5_M 0x07000000 648 #define AM_REG_ADC_SL5CFG_ADSEL5(n) (((uint32_t)(n) << 24) & 0x07000000) 649 #define AM_REG_ADC_SL5CFG_ADSEL5_AVG_1_MSRMT 0x00000000 650 #define AM_REG_ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS 0x01000000 651 #define AM_REG_ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS 0x02000000 652 #define AM_REG_ADC_SL5CFG_ADSEL5_AVG_8_MSRMT 0x03000000 653 #define AM_REG_ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS 0x04000000 654 #define AM_REG_ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS 0x05000000 655 #define AM_REG_ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS 0x06000000 656 #define AM_REG_ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS 0x07000000 657 658 // Set the Precision Mode For Slot. 659 #define AM_REG_ADC_SL5CFG_PRMODE5_S 16 660 #define AM_REG_ADC_SL5CFG_PRMODE5_M 0x00030000 661 #define AM_REG_ADC_SL5CFG_PRMODE5(n) (((uint32_t)(n) << 16) & 0x00030000) 662 #define AM_REG_ADC_SL5CFG_PRMODE5_P14B 0x00000000 663 #define AM_REG_ADC_SL5CFG_PRMODE5_P12B 0x00010000 664 #define AM_REG_ADC_SL5CFG_PRMODE5_P10B 0x00020000 665 #define AM_REG_ADC_SL5CFG_PRMODE5_P8B 0x00030000 666 667 // Select one of the 14 channel inputs for this slot. 668 #define AM_REG_ADC_SL5CFG_CHSEL5_S 8 669 #define AM_REG_ADC_SL5CFG_CHSEL5_M 0x00000F00 670 #define AM_REG_ADC_SL5CFG_CHSEL5(n) (((uint32_t)(n) << 8) & 0x00000F00) 671 #define AM_REG_ADC_SL5CFG_CHSEL5_SE0 0x00000000 672 #define AM_REG_ADC_SL5CFG_CHSEL5_SE1 0x00000100 673 #define AM_REG_ADC_SL5CFG_CHSEL5_SE2 0x00000200 674 #define AM_REG_ADC_SL5CFG_CHSEL5_SE3 0x00000300 675 #define AM_REG_ADC_SL5CFG_CHSEL5_SE4 0x00000400 676 #define AM_REG_ADC_SL5CFG_CHSEL5_SE5 0x00000500 677 #define AM_REG_ADC_SL5CFG_CHSEL5_SE6 0x00000600 678 #define AM_REG_ADC_SL5CFG_CHSEL5_SE7 0x00000700 679 #define AM_REG_ADC_SL5CFG_CHSEL5_SE8 0x00000800 680 #define AM_REG_ADC_SL5CFG_CHSEL5_SE9 0x00000900 681 #define AM_REG_ADC_SL5CFG_CHSEL5_DF0 0x00000A00 682 #define AM_REG_ADC_SL5CFG_CHSEL5_DF1 0x00000B00 683 #define AM_REG_ADC_SL5CFG_CHSEL5_TEMP 0x00000C00 684 #define AM_REG_ADC_SL5CFG_CHSEL5_BATT 0x00000D00 685 #define AM_REG_ADC_SL5CFG_CHSEL5_VSS 0x00000E00 686 687 // This bit enables the window compare function for slot 5. 688 #define AM_REG_ADC_SL5CFG_WCEN5_S 1 689 #define AM_REG_ADC_SL5CFG_WCEN5_M 0x00000002 690 #define AM_REG_ADC_SL5CFG_WCEN5(n) (((uint32_t)(n) << 1) & 0x00000002) 691 #define AM_REG_ADC_SL5CFG_WCEN5_WCEN 0x00000002 692 693 // This bit enables slot 5 for ADC conversions. 694 #define AM_REG_ADC_SL5CFG_SLEN5_S 0 695 #define AM_REG_ADC_SL5CFG_SLEN5_M 0x00000001 696 #define AM_REG_ADC_SL5CFG_SLEN5(n) (((uint32_t)(n) << 0) & 0x00000001) 697 #define AM_REG_ADC_SL5CFG_SLEN5_SLEN 0x00000001 698 699 //***************************************************************************** 700 // 701 // ADC_SL6CFG - Slot 6 Configuration Register 702 // 703 //***************************************************************************** 704 // Select the number of measurements to average in the accumulate divide module 705 // for this slot. 706 #define AM_REG_ADC_SL6CFG_ADSEL6_S 24 707 #define AM_REG_ADC_SL6CFG_ADSEL6_M 0x07000000 708 #define AM_REG_ADC_SL6CFG_ADSEL6(n) (((uint32_t)(n) << 24) & 0x07000000) 709 #define AM_REG_ADC_SL6CFG_ADSEL6_AVG_1_MSRMT 0x00000000 710 #define AM_REG_ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS 0x01000000 711 #define AM_REG_ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS 0x02000000 712 #define AM_REG_ADC_SL6CFG_ADSEL6_AVG_8_MSRMT 0x03000000 713 #define AM_REG_ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS 0x04000000 714 #define AM_REG_ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS 0x05000000 715 #define AM_REG_ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS 0x06000000 716 #define AM_REG_ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS 0x07000000 717 718 // Set the Precision Mode For Slot. 719 #define AM_REG_ADC_SL6CFG_PRMODE6_S 16 720 #define AM_REG_ADC_SL6CFG_PRMODE6_M 0x00030000 721 #define AM_REG_ADC_SL6CFG_PRMODE6(n) (((uint32_t)(n) << 16) & 0x00030000) 722 #define AM_REG_ADC_SL6CFG_PRMODE6_P14B 0x00000000 723 #define AM_REG_ADC_SL6CFG_PRMODE6_P12B 0x00010000 724 #define AM_REG_ADC_SL6CFG_PRMODE6_P10B 0x00020000 725 #define AM_REG_ADC_SL6CFG_PRMODE6_P8B 0x00030000 726 727 // Select one of the 14 channel inputs for this slot. 728 #define AM_REG_ADC_SL6CFG_CHSEL6_S 8 729 #define AM_REG_ADC_SL6CFG_CHSEL6_M 0x00000F00 730 #define AM_REG_ADC_SL6CFG_CHSEL6(n) (((uint32_t)(n) << 8) & 0x00000F00) 731 #define AM_REG_ADC_SL6CFG_CHSEL6_SE0 0x00000000 732 #define AM_REG_ADC_SL6CFG_CHSEL6_SE1 0x00000100 733 #define AM_REG_ADC_SL6CFG_CHSEL6_SE2 0x00000200 734 #define AM_REG_ADC_SL6CFG_CHSEL6_SE3 0x00000300 735 #define AM_REG_ADC_SL6CFG_CHSEL6_SE4 0x00000400 736 #define AM_REG_ADC_SL6CFG_CHSEL6_SE5 0x00000500 737 #define AM_REG_ADC_SL6CFG_CHSEL6_SE6 0x00000600 738 #define AM_REG_ADC_SL6CFG_CHSEL6_SE7 0x00000700 739 #define AM_REG_ADC_SL6CFG_CHSEL6_SE8 0x00000800 740 #define AM_REG_ADC_SL6CFG_CHSEL6_SE9 0x00000900 741 #define AM_REG_ADC_SL6CFG_CHSEL6_DF0 0x00000A00 742 #define AM_REG_ADC_SL6CFG_CHSEL6_DF1 0x00000B00 743 #define AM_REG_ADC_SL6CFG_CHSEL6_TEMP 0x00000C00 744 #define AM_REG_ADC_SL6CFG_CHSEL6_BATT 0x00000D00 745 #define AM_REG_ADC_SL6CFG_CHSEL6_VSS 0x00000E00 746 747 // This bit enables the window compare function for slot 6. 748 #define AM_REG_ADC_SL6CFG_WCEN6_S 1 749 #define AM_REG_ADC_SL6CFG_WCEN6_M 0x00000002 750 #define AM_REG_ADC_SL6CFG_WCEN6(n) (((uint32_t)(n) << 1) & 0x00000002) 751 #define AM_REG_ADC_SL6CFG_WCEN6_WCEN 0x00000002 752 753 // This bit enables slot 6 for ADC conversions. 754 #define AM_REG_ADC_SL6CFG_SLEN6_S 0 755 #define AM_REG_ADC_SL6CFG_SLEN6_M 0x00000001 756 #define AM_REG_ADC_SL6CFG_SLEN6(n) (((uint32_t)(n) << 0) & 0x00000001) 757 #define AM_REG_ADC_SL6CFG_SLEN6_SLEN 0x00000001 758 759 //***************************************************************************** 760 // 761 // ADC_SL7CFG - Slot 7 Configuration Register 762 // 763 //***************************************************************************** 764 // Select the number of measurements to average in the accumulate divide module 765 // for this slot. 766 #define AM_REG_ADC_SL7CFG_ADSEL7_S 24 767 #define AM_REG_ADC_SL7CFG_ADSEL7_M 0x07000000 768 #define AM_REG_ADC_SL7CFG_ADSEL7(n) (((uint32_t)(n) << 24) & 0x07000000) 769 #define AM_REG_ADC_SL7CFG_ADSEL7_AVG_1_MSRMT 0x00000000 770 #define AM_REG_ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS 0x01000000 771 #define AM_REG_ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS 0x02000000 772 #define AM_REG_ADC_SL7CFG_ADSEL7_AVG_8_MSRMT 0x03000000 773 #define AM_REG_ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS 0x04000000 774 #define AM_REG_ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS 0x05000000 775 #define AM_REG_ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS 0x06000000 776 #define AM_REG_ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS 0x07000000 777 778 // Set the Precision Mode For Slot. 779 #define AM_REG_ADC_SL7CFG_PRMODE7_S 16 780 #define AM_REG_ADC_SL7CFG_PRMODE7_M 0x00030000 781 #define AM_REG_ADC_SL7CFG_PRMODE7(n) (((uint32_t)(n) << 16) & 0x00030000) 782 #define AM_REG_ADC_SL7CFG_PRMODE7_P14B 0x00000000 783 #define AM_REG_ADC_SL7CFG_PRMODE7_P12B 0x00010000 784 #define AM_REG_ADC_SL7CFG_PRMODE7_P10B 0x00020000 785 #define AM_REG_ADC_SL7CFG_PRMODE7_P8B 0x00030000 786 787 // Select one of the 14 channel inputs for this slot. 788 #define AM_REG_ADC_SL7CFG_CHSEL7_S 8 789 #define AM_REG_ADC_SL7CFG_CHSEL7_M 0x00000F00 790 #define AM_REG_ADC_SL7CFG_CHSEL7(n) (((uint32_t)(n) << 8) & 0x00000F00) 791 #define AM_REG_ADC_SL7CFG_CHSEL7_SE0 0x00000000 792 #define AM_REG_ADC_SL7CFG_CHSEL7_SE1 0x00000100 793 #define AM_REG_ADC_SL7CFG_CHSEL7_SE2 0x00000200 794 #define AM_REG_ADC_SL7CFG_CHSEL7_SE3 0x00000300 795 #define AM_REG_ADC_SL7CFG_CHSEL7_SE4 0x00000400 796 #define AM_REG_ADC_SL7CFG_CHSEL7_SE5 0x00000500 797 #define AM_REG_ADC_SL7CFG_CHSEL7_SE6 0x00000600 798 #define AM_REG_ADC_SL7CFG_CHSEL7_SE7 0x00000700 799 #define AM_REG_ADC_SL7CFG_CHSEL7_SE8 0x00000800 800 #define AM_REG_ADC_SL7CFG_CHSEL7_SE9 0x00000900 801 #define AM_REG_ADC_SL7CFG_CHSEL7_DF0 0x00000A00 802 #define AM_REG_ADC_SL7CFG_CHSEL7_DF1 0x00000B00 803 #define AM_REG_ADC_SL7CFG_CHSEL7_TEMP 0x00000C00 804 #define AM_REG_ADC_SL7CFG_CHSEL7_BATT 0x00000D00 805 #define AM_REG_ADC_SL7CFG_CHSEL7_VSS 0x00000E00 806 807 // This bit enables the window compare function for slot 7. 808 #define AM_REG_ADC_SL7CFG_WCEN7_S 1 809 #define AM_REG_ADC_SL7CFG_WCEN7_M 0x00000002 810 #define AM_REG_ADC_SL7CFG_WCEN7(n) (((uint32_t)(n) << 1) & 0x00000002) 811 #define AM_REG_ADC_SL7CFG_WCEN7_WCEN 0x00000002 812 813 // This bit enables slot 7 for ADC conversions. 814 #define AM_REG_ADC_SL7CFG_SLEN7_S 0 815 #define AM_REG_ADC_SL7CFG_SLEN7_M 0x00000001 816 #define AM_REG_ADC_SL7CFG_SLEN7(n) (((uint32_t)(n) << 0) & 0x00000001) 817 #define AM_REG_ADC_SL7CFG_SLEN7_SLEN 0x00000001 818 819 //***************************************************************************** 820 // 821 // ADC_WULIM - Window Comparator Upper Limits Register 822 // 823 //***************************************************************************** 824 // Sets the upper limit for the wondow comparator. 825 #define AM_REG_ADC_WULIM_ULIM_S 0 826 #define AM_REG_ADC_WULIM_ULIM_M 0x000FFFFF 827 #define AM_REG_ADC_WULIM_ULIM(n) (((uint32_t)(n) << 0) & 0x000FFFFF) 828 829 //***************************************************************************** 830 // 831 // ADC_WLLIM - Window Comparator Lower Limits Register 832 // 833 //***************************************************************************** 834 // Sets the lower limit for the wondow comparator. 835 #define AM_REG_ADC_WLLIM_LLIM_S 0 836 #define AM_REG_ADC_WLLIM_LLIM_M 0x000FFFFF 837 #define AM_REG_ADC_WLLIM_LLIM(n) (((uint32_t)(n) << 0) & 0x000FFFFF) 838 839 //***************************************************************************** 840 // 841 // ADC_FIFO - FIFO Data and Valid Count Register 842 // 843 //***************************************************************************** 844 // RESERVED. 845 #define AM_REG_ADC_FIFO_RSVD_S 31 846 #define AM_REG_ADC_FIFO_RSVD_M 0x80000000 847 #define AM_REG_ADC_FIFO_RSVD(n) (((uint32_t)(n) << 31) & 0x80000000) 848 849 // Slot number associated with this FIFO data. 850 #define AM_REG_ADC_FIFO_SLOTNUM_S 28 851 #define AM_REG_ADC_FIFO_SLOTNUM_M 0x70000000 852 #define AM_REG_ADC_FIFO_SLOTNUM(n) (((uint32_t)(n) << 28) & 0x70000000) 853 854 // Number of valid entries in the ADC FIFO. 855 #define AM_REG_ADC_FIFO_COUNT_S 20 856 #define AM_REG_ADC_FIFO_COUNT_M 0x0FF00000 857 #define AM_REG_ADC_FIFO_COUNT(n) (((uint32_t)(n) << 20) & 0x0FF00000) 858 859 // Oldest data in the FIFO. 860 #define AM_REG_ADC_FIFO_DATA_S 0 861 #define AM_REG_ADC_FIFO_DATA_M 0x000FFFFF 862 #define AM_REG_ADC_FIFO_DATA(n) (((uint32_t)(n) << 0) & 0x000FFFFF) 863 864 #endif // AM_REG_ADC_H 865