1 //***************************************************************************** 2 // 3 // am_reg_clkgen.h 4 //! @file 5 //! 6 //! @brief Register macros for the CLKGEN module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_CLKGEN_H 45 #define AM_REG_CLKGEN_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_CLKGEN_NUM_MODULES 1 53 #define AM_REG_CLKGENn(n) \ 54 (REG_CLKGEN_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_CLKGEN_CALXT_O 0x00000000 62 #define AM_REG_CLKGEN_CALRC_O 0x00000004 63 #define AM_REG_CLKGEN_ACALCTR_O 0x00000008 64 #define AM_REG_CLKGEN_OCTRL_O 0x0000000C 65 #define AM_REG_CLKGEN_CLKOUT_O 0x00000010 66 #define AM_REG_CLKGEN_CCTRL_O 0x00000018 67 #define AM_REG_CLKGEN_STATUS_O 0x0000001C 68 #define AM_REG_CLKGEN_HFADJ_O 0x00000020 69 #define AM_REG_CLKGEN_CLOCKEN_O 0x00000028 70 #define AM_REG_CLKGEN_CLOCKEN2_O 0x0000002C 71 #define AM_REG_CLKGEN_CLOCKEN3_O 0x00000030 72 #define AM_REG_CLKGEN_UARTEN_O 0x00000034 73 #define AM_REG_CLKGEN_CLKKEY_O 0x00000014 74 #define AM_REG_CLKGEN_INTEN_O 0x00000100 75 #define AM_REG_CLKGEN_INTSTAT_O 0x00000104 76 #define AM_REG_CLKGEN_INTCLR_O 0x00000108 77 #define AM_REG_CLKGEN_INTSET_O 0x0000010C 78 79 //***************************************************************************** 80 // 81 // Key values. 82 // 83 //***************************************************************************** 84 #define AM_REG_CLKGEN_CLKKEY_KEYVAL 0x00000047 85 86 //***************************************************************************** 87 // 88 // CLKGEN_INTEN - CLKGEN Interrupt Register: Enable 89 // 90 //***************************************************************************** 91 // RTC Alarm interrupt 92 #define AM_REG_CLKGEN_INTEN_ALM_S 3 93 #define AM_REG_CLKGEN_INTEN_ALM_M 0x00000008 94 #define AM_REG_CLKGEN_INTEN_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) 95 96 // XT Oscillator Fail interrupt 97 #define AM_REG_CLKGEN_INTEN_OF_S 2 98 #define AM_REG_CLKGEN_INTEN_OF_M 0x00000004 99 #define AM_REG_CLKGEN_INTEN_OF(n) (((uint32_t)(n) << 2) & 0x00000004) 100 101 // Autocalibration Complete interrupt 102 #define AM_REG_CLKGEN_INTEN_ACC_S 1 103 #define AM_REG_CLKGEN_INTEN_ACC_M 0x00000002 104 #define AM_REG_CLKGEN_INTEN_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) 105 106 // Autocalibration Fail interrupt 107 #define AM_REG_CLKGEN_INTEN_ACF_S 0 108 #define AM_REG_CLKGEN_INTEN_ACF_M 0x00000001 109 #define AM_REG_CLKGEN_INTEN_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) 110 111 //***************************************************************************** 112 // 113 // CLKGEN_INTSTAT - CLKGEN Interrupt Register: Status 114 // 115 //***************************************************************************** 116 // RTC Alarm interrupt 117 #define AM_REG_CLKGEN_INTSTAT_ALM_S 3 118 #define AM_REG_CLKGEN_INTSTAT_ALM_M 0x00000008 119 #define AM_REG_CLKGEN_INTSTAT_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) 120 121 // XT Oscillator Fail interrupt 122 #define AM_REG_CLKGEN_INTSTAT_OF_S 2 123 #define AM_REG_CLKGEN_INTSTAT_OF_M 0x00000004 124 #define AM_REG_CLKGEN_INTSTAT_OF(n) (((uint32_t)(n) << 2) & 0x00000004) 125 126 // Autocalibration Complete interrupt 127 #define AM_REG_CLKGEN_INTSTAT_ACC_S 1 128 #define AM_REG_CLKGEN_INTSTAT_ACC_M 0x00000002 129 #define AM_REG_CLKGEN_INTSTAT_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) 130 131 // Autocalibration Fail interrupt 132 #define AM_REG_CLKGEN_INTSTAT_ACF_S 0 133 #define AM_REG_CLKGEN_INTSTAT_ACF_M 0x00000001 134 #define AM_REG_CLKGEN_INTSTAT_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) 135 136 //***************************************************************************** 137 // 138 // CLKGEN_INTCLR - CLKGEN Interrupt Register: Clear 139 // 140 //***************************************************************************** 141 // RTC Alarm interrupt 142 #define AM_REG_CLKGEN_INTCLR_ALM_S 3 143 #define AM_REG_CLKGEN_INTCLR_ALM_M 0x00000008 144 #define AM_REG_CLKGEN_INTCLR_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) 145 146 // XT Oscillator Fail interrupt 147 #define AM_REG_CLKGEN_INTCLR_OF_S 2 148 #define AM_REG_CLKGEN_INTCLR_OF_M 0x00000004 149 #define AM_REG_CLKGEN_INTCLR_OF(n) (((uint32_t)(n) << 2) & 0x00000004) 150 151 // Autocalibration Complete interrupt 152 #define AM_REG_CLKGEN_INTCLR_ACC_S 1 153 #define AM_REG_CLKGEN_INTCLR_ACC_M 0x00000002 154 #define AM_REG_CLKGEN_INTCLR_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) 155 156 // Autocalibration Fail interrupt 157 #define AM_REG_CLKGEN_INTCLR_ACF_S 0 158 #define AM_REG_CLKGEN_INTCLR_ACF_M 0x00000001 159 #define AM_REG_CLKGEN_INTCLR_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) 160 161 //***************************************************************************** 162 // 163 // CLKGEN_INTSET - CLKGEN Interrupt Register: Set 164 // 165 //***************************************************************************** 166 // RTC Alarm interrupt 167 #define AM_REG_CLKGEN_INTSET_ALM_S 3 168 #define AM_REG_CLKGEN_INTSET_ALM_M 0x00000008 169 #define AM_REG_CLKGEN_INTSET_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) 170 171 // XT Oscillator Fail interrupt 172 #define AM_REG_CLKGEN_INTSET_OF_S 2 173 #define AM_REG_CLKGEN_INTSET_OF_M 0x00000004 174 #define AM_REG_CLKGEN_INTSET_OF(n) (((uint32_t)(n) << 2) & 0x00000004) 175 176 // Autocalibration Complete interrupt 177 #define AM_REG_CLKGEN_INTSET_ACC_S 1 178 #define AM_REG_CLKGEN_INTSET_ACC_M 0x00000002 179 #define AM_REG_CLKGEN_INTSET_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) 180 181 // Autocalibration Fail interrupt 182 #define AM_REG_CLKGEN_INTSET_ACF_S 0 183 #define AM_REG_CLKGEN_INTSET_ACF_M 0x00000001 184 #define AM_REG_CLKGEN_INTSET_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) 185 186 //***************************************************************************** 187 // 188 // CLKGEN_CALXT - XT Oscillator Control 189 // 190 //***************************************************************************** 191 // XT Oscillator calibration value 192 #define AM_REG_CLKGEN_CALXT_CALXT_S 0 193 #define AM_REG_CLKGEN_CALXT_CALXT_M 0x000007FF 194 #define AM_REG_CLKGEN_CALXT_CALXT(n) (((uint32_t)(n) << 0) & 0x000007FF) 195 196 //***************************************************************************** 197 // 198 // CLKGEN_CALRC - RC Oscillator Control 199 // 200 //***************************************************************************** 201 // LFRC Oscillator calibration value 202 #define AM_REG_CLKGEN_CALRC_CALRC_S 0 203 #define AM_REG_CLKGEN_CALRC_CALRC_M 0x0003FFFF 204 #define AM_REG_CLKGEN_CALRC_CALRC(n) (((uint32_t)(n) << 0) & 0x0003FFFF) 205 206 //***************************************************************************** 207 // 208 // CLKGEN_ACALCTR - Autocalibration Counter 209 // 210 //***************************************************************************** 211 // Autocalibration Counter result. 212 #define AM_REG_CLKGEN_ACALCTR_ACALCTR_S 0 213 #define AM_REG_CLKGEN_ACALCTR_ACALCTR_M 0x00FFFFFF 214 #define AM_REG_CLKGEN_ACALCTR_ACALCTR(n) (((uint32_t)(n) << 0) & 0x00FFFFFF) 215 216 //***************************************************************************** 217 // 218 // CLKGEN_OCTRL - Oscillator Control 219 // 220 //***************************************************************************** 221 // Autocalibration control 222 #define AM_REG_CLKGEN_OCTRL_ACAL_S 8 223 #define AM_REG_CLKGEN_OCTRL_ACAL_M 0x00000700 224 #define AM_REG_CLKGEN_OCTRL_ACAL(n) (((uint32_t)(n) << 8) & 0x00000700) 225 #define AM_REG_CLKGEN_OCTRL_ACAL_DIS 0x00000000 226 #define AM_REG_CLKGEN_OCTRL_ACAL_1024SEC 0x00000200 227 #define AM_REG_CLKGEN_OCTRL_ACAL_512SEC 0x00000300 228 #define AM_REG_CLKGEN_OCTRL_ACAL_XTFREQ 0x00000600 229 #define AM_REG_CLKGEN_OCTRL_ACAL_EXTFREQ 0x00000700 230 231 // Selects the RTC oscillator (1 => LFRC, 0 => XT) 232 #define AM_REG_CLKGEN_OCTRL_OSEL_S 7 233 #define AM_REG_CLKGEN_OCTRL_OSEL_M 0x00000080 234 #define AM_REG_CLKGEN_OCTRL_OSEL(n) (((uint32_t)(n) << 7) & 0x00000080) 235 #define AM_REG_CLKGEN_OCTRL_OSEL_RTC_XT 0x00000000 236 #define AM_REG_CLKGEN_OCTRL_OSEL_RTC_LFRC 0x00000080 237 238 // Oscillator switch on failure function 239 #define AM_REG_CLKGEN_OCTRL_FOS_S 6 240 #define AM_REG_CLKGEN_OCTRL_FOS_M 0x00000040 241 #define AM_REG_CLKGEN_OCTRL_FOS(n) (((uint32_t)(n) << 6) & 0x00000040) 242 #define AM_REG_CLKGEN_OCTRL_FOS_DIS 0x00000000 243 #define AM_REG_CLKGEN_OCTRL_FOS_EN 0x00000040 244 245 // Stop the LFRC Oscillator to the RTC 246 #define AM_REG_CLKGEN_OCTRL_STOPRC_S 1 247 #define AM_REG_CLKGEN_OCTRL_STOPRC_M 0x00000002 248 #define AM_REG_CLKGEN_OCTRL_STOPRC(n) (((uint32_t)(n) << 1) & 0x00000002) 249 #define AM_REG_CLKGEN_OCTRL_STOPRC_EN 0x00000000 250 #define AM_REG_CLKGEN_OCTRL_STOPRC_STOP 0x00000002 251 252 // Stop the XT Oscillator to the RTC 253 #define AM_REG_CLKGEN_OCTRL_STOPXT_S 0 254 #define AM_REG_CLKGEN_OCTRL_STOPXT_M 0x00000001 255 #define AM_REG_CLKGEN_OCTRL_STOPXT(n) (((uint32_t)(n) << 0) & 0x00000001) 256 #define AM_REG_CLKGEN_OCTRL_STOPXT_EN 0x00000000 257 #define AM_REG_CLKGEN_OCTRL_STOPXT_STOP 0x00000001 258 259 //***************************************************************************** 260 // 261 // CLKGEN_CLKOUT - CLKOUT Frequency Select 262 // 263 //***************************************************************************** 264 // Enable the CLKOUT signal 265 #define AM_REG_CLKGEN_CLKOUT_CKEN_S 7 266 #define AM_REG_CLKGEN_CLKOUT_CKEN_M 0x00000080 267 #define AM_REG_CLKGEN_CLKOUT_CKEN(n) (((uint32_t)(n) << 7) & 0x00000080) 268 #define AM_REG_CLKGEN_CLKOUT_CKEN_DIS 0x00000000 269 #define AM_REG_CLKGEN_CLKOUT_CKEN_EN 0x00000080 270 271 // CLKOUT signal select. Note that HIGH_DRIVE should be selected if any high 272 // frequencies (such as from HFRC) are selected for CLKOUT. 273 #define AM_REG_CLKGEN_CLKOUT_CKSEL_S 0 274 #define AM_REG_CLKGEN_CLKOUT_CKSEL_M 0x0000003F 275 #define AM_REG_CLKGEN_CLKOUT_CKSEL(n) (((uint32_t)(n) << 0) & 0x0000003F) 276 #define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC 0x00000000 277 #define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2 0x00000001 278 #define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV4 0x00000002 279 #define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8 0x00000003 280 #define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV16 0x00000004 281 #define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV32 0x00000005 282 #define AM_REG_CLKGEN_CLKOUT_CKSEL_RTC_1Hz 0x00000010 283 #define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2M 0x00000016 284 #define AM_REG_CLKGEN_CLKOUT_CKSEL_XT 0x00000017 285 #define AM_REG_CLKGEN_CLKOUT_CKSEL_CG_100Hz 0x00000018 286 #define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC 0x00000019 287 #define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 0x0000001A 288 #define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 0x0000001B 289 #define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16 0x0000001C 290 #define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 0x0000001D 291 #define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 0x0000001E 292 #define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 0x0000001F 293 #define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV512 0x00000020 294 #define AM_REG_CLKGEN_CLKOUT_CKSEL_FLASH_CLK 0x00000022 295 #define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 0x00000023 296 #define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 0x00000024 297 #define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 0x00000025 298 #define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K 0x00000026 299 #define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV256 0x00000027 300 #define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8K 0x00000028 301 #define AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV64K 0x00000029 302 #define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 0x0000002A 303 #define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 0x0000002B 304 #define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz 0x0000002C 305 #define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K 0x0000002D 306 #define AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M 0x0000002E 307 #define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K 0x0000002F 308 #define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M 0x00000030 309 #define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M 0x00000031 310 #define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE 0x00000032 311 #define AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 0x00000033 312 #define AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE 0x00000035 313 #define AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 0x00000036 314 #define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 0x00000037 315 #define AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE 0x00000039 316 317 //***************************************************************************** 318 // 319 // CLKGEN_CCTRL - HFRC Clock Control 320 // 321 //***************************************************************************** 322 // Core Clock divisor 323 #define AM_REG_CLKGEN_CCTRL_CORESEL_S 0 324 #define AM_REG_CLKGEN_CCTRL_CORESEL_M 0x00000001 325 #define AM_REG_CLKGEN_CCTRL_CORESEL(n) (((uint32_t)(n) << 0) & 0x00000001) 326 #define AM_REG_CLKGEN_CCTRL_CORESEL_HFRC 0x00000000 327 #define AM_REG_CLKGEN_CCTRL_CORESEL_HFRC_DIV2 0x00000001 328 329 //***************************************************************************** 330 // 331 // CLKGEN_STATUS - Clock Generator Status 332 // 333 //***************************************************************************** 334 // XT Oscillator is enabled but not oscillating 335 #define AM_REG_CLKGEN_STATUS_OSCF_S 1 336 #define AM_REG_CLKGEN_STATUS_OSCF_M 0x00000002 337 #define AM_REG_CLKGEN_STATUS_OSCF(n) (((uint32_t)(n) << 1) & 0x00000002) 338 339 // Current RTC oscillator (1 => LFRC, 0 => XT) 340 #define AM_REG_CLKGEN_STATUS_OMODE_S 0 341 #define AM_REG_CLKGEN_STATUS_OMODE_M 0x00000001 342 #define AM_REG_CLKGEN_STATUS_OMODE(n) (((uint32_t)(n) << 0) & 0x00000001) 343 344 //***************************************************************************** 345 // 346 // CLKGEN_HFADJ - HFRC Adjustment 347 // 348 //***************************************************************************** 349 // Gain control for HFRC adjustment 350 #define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_S 21 351 #define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_M 0x00E00000 352 #define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN(n) (((uint32_t)(n) << 21) & 0x00E00000) 353 #define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1 0x00000000 354 #define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_2 0x00200000 355 #define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_4 0x00400000 356 #define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_8 0x00600000 357 #define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_16 0x00800000 358 #define AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_32 0x00A00000 359 360 // XT warmup period for HFRC adjustment 361 #define AM_REG_CLKGEN_HFADJ_HFWARMUP_S 20 362 #define AM_REG_CLKGEN_HFADJ_HFWARMUP_M 0x00100000 363 #define AM_REG_CLKGEN_HFADJ_HFWARMUP(n) (((uint32_t)(n) << 20) & 0x00100000) 364 #define AM_REG_CLKGEN_HFADJ_HFWARMUP_1SEC 0x00000000 365 #define AM_REG_CLKGEN_HFADJ_HFWARMUP_2SEC 0x00100000 366 367 // Target HFRC adjustment value. 368 #define AM_REG_CLKGEN_HFADJ_HFXTADJ_S 8 369 #define AM_REG_CLKGEN_HFADJ_HFXTADJ_M 0x000FFF00 370 #define AM_REG_CLKGEN_HFADJ_HFXTADJ(n) (((uint32_t)(n) << 8) & 0x000FFF00) 371 372 // Repeat period for HFRC adjustment 373 #define AM_REG_CLKGEN_HFADJ_HFADJCK_S 1 374 #define AM_REG_CLKGEN_HFADJ_HFADJCK_M 0x0000000E 375 #define AM_REG_CLKGEN_HFADJ_HFADJCK(n) (((uint32_t)(n) << 1) & 0x0000000E) 376 #define AM_REG_CLKGEN_HFADJ_HFADJCK_4SEC 0x00000000 377 #define AM_REG_CLKGEN_HFADJ_HFADJCK_16SEC 0x00000002 378 #define AM_REG_CLKGEN_HFADJ_HFADJCK_32SEC 0x00000004 379 #define AM_REG_CLKGEN_HFADJ_HFADJCK_64SEC 0x00000006 380 #define AM_REG_CLKGEN_HFADJ_HFADJCK_128SEC 0x00000008 381 #define AM_REG_CLKGEN_HFADJ_HFADJCK_256SEC 0x0000000A 382 #define AM_REG_CLKGEN_HFADJ_HFADJCK_512SEC 0x0000000C 383 #define AM_REG_CLKGEN_HFADJ_HFADJCK_1024SEC 0x0000000E 384 385 // HFRC adjustment control 386 #define AM_REG_CLKGEN_HFADJ_HFADJEN_S 0 387 #define AM_REG_CLKGEN_HFADJ_HFADJEN_M 0x00000001 388 #define AM_REG_CLKGEN_HFADJ_HFADJEN(n) (((uint32_t)(n) << 0) & 0x00000001) 389 #define AM_REG_CLKGEN_HFADJ_HFADJEN_DIS 0x00000000 390 #define AM_REG_CLKGEN_HFADJ_HFADJEN_EN 0x00000001 391 392 //***************************************************************************** 393 // 394 // CLKGEN_CLOCKEN - Clock Enable Status 395 // 396 //***************************************************************************** 397 // Clock enable status 398 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_S 0 399 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_M 0xFFFFFFFF 400 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 401 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_ADC_CLKEN 0x00000001 402 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER_CLKEN 0x00000002 403 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER0A_CLKEN 0x00000004 404 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER0B_CLKEN 0x00000008 405 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER1A_CLKEN 0x00000010 406 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER1B_CLKEN 0x00000020 407 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER2A_CLKEN 0x00000040 408 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER2B_CLKEN 0x00000080 409 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER3A_CLKEN 0x00000100 410 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_CTIMER3B_CLKEN 0x00000200 411 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR0_CLKEN 0x00000400 412 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR1_CLKEN 0x00000800 413 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR2_CLKEN 0x00001000 414 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR3_CLKEN 0x00002000 415 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR4_CLKEN 0x00004000 416 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTR5_CLKEN 0x00008000 417 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC0_CLKEN 0x00010000 418 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC1_CLKEN 0x00020000 419 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC2_CLKEN 0x00040000 420 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC3_CLKEN 0x00080000 421 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC4_CLKEN 0x00100000 422 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOMSTRIFC5_CLKEN 0x00200000 423 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_IOSLAVE_CLKEN 0x00400000 424 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_PDM_CLKEN 0x00800000 425 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_PDMIFC_CLKEN 0x01000000 426 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_RSTGEN_CLKEN 0x02000000 427 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_SRAM_WIPE_CLKEN 0x04000000 428 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_STIMER_CLKEN 0x08000000 429 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_STIMER_CNT_CLKEN 0x10000000 430 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_TPIU_CLKEN 0x20000000 431 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_UART0_HCLK_CLKEN 0x40000000 432 #define AM_REG_CLKGEN_CLOCKEN_CLOCKEN_UART0HF_CLKEN 0x80000000 433 434 //***************************************************************************** 435 // 436 // CLKGEN_CLOCKEN2 - Clock Enable Status 437 // 438 //***************************************************************************** 439 // Clock enable status 2 440 #define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_S 0 441 #define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_M 0xFFFFFFFF 442 #define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 443 #define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_UART1_HCLK_CLKEN 0x00000001 444 #define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_UART1HF_CLKEN 0x00000002 445 #define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_WDT_CLKEN 0x00000004 446 #define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_XT_32KHz_EN 0x40000000 447 #define AM_REG_CLKGEN_CLOCKEN2_CLOCKEN2_FRCHFRC 0x80000000 448 449 //***************************************************************************** 450 // 451 // CLKGEN_CLOCKEN3 - Clock Enable Status 452 // 453 //***************************************************************************** 454 // Clock enable status 3 455 #define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_S 0 456 #define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_M 0xFFFFFFFF 457 #define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 458 #define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_periph_all_xtal_en 0x01000000 459 #define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_periph_all_hfrc_en 0x02000000 460 #define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFADJEN 0x04000000 461 #define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFRC_en_out 0x08000000 462 #define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_RTC_SOURCE 0x10000000 463 #define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_XTAL_EN 0x20000000 464 #define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_HFRC_EN 0x40000000 465 #define AM_REG_CLKGEN_CLOCKEN3_CLOCKEN3_FLASHCLK_EN 0x80000000 466 467 //***************************************************************************** 468 // 469 // CLKGEN_UARTEN - UART Enable 470 // 471 //***************************************************************************** 472 // UART1 system clock control 473 #define AM_REG_CLKGEN_UARTEN_UART1EN_S 8 474 #define AM_REG_CLKGEN_UARTEN_UART1EN_M 0x00000300 475 #define AM_REG_CLKGEN_UARTEN_UART1EN(n) (((uint32_t)(n) << 8) & 0x00000300) 476 #define AM_REG_CLKGEN_UARTEN_UART1EN_DIS 0x00000000 477 #define AM_REG_CLKGEN_UARTEN_UART1EN_EN 0x00000100 478 #define AM_REG_CLKGEN_UARTEN_UART1EN_REDUCE_FREQ 0x00000200 479 #define AM_REG_CLKGEN_UARTEN_UART1EN_EN_POWER_SAV 0x00000300 480 481 // UART0 system clock control 482 #define AM_REG_CLKGEN_UARTEN_UART0EN_S 0 483 #define AM_REG_CLKGEN_UARTEN_UART0EN_M 0x00000003 484 #define AM_REG_CLKGEN_UARTEN_UART0EN(n) (((uint32_t)(n) << 0) & 0x00000003) 485 #define AM_REG_CLKGEN_UARTEN_UART0EN_DIS 0x00000000 486 #define AM_REG_CLKGEN_UARTEN_UART0EN_EN 0x00000001 487 #define AM_REG_CLKGEN_UARTEN_UART0EN_REDUCE_FREQ 0x00000002 488 #define AM_REG_CLKGEN_UARTEN_UART0EN_EN_POWER_SAV 0x00000003 489 490 #endif // AM_REG_CLKGEN_H 491