1 //***************************************************************************** 2 // 3 // am_reg_ctimer.h 4 //! @file 5 //! 6 //! @brief Register macros for the CTIMER module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_CTIMER_H 45 #define AM_REG_CTIMER_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_CTIMER_NUM_MODULES 1 53 #define AM_REG_CTIMERn(n) \ 54 (REG_CTIMER_BASEADDR + 0x00000010 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_CTIMER_TMR0_O 0x00000000 62 #define AM_REG_CTIMER_CMPRA0_O 0x00000004 63 #define AM_REG_CTIMER_CMPRB0_O 0x00000008 64 #define AM_REG_CTIMER_CTRL0_O 0x0000000C 65 #define AM_REG_CTIMER_TMR1_O 0x00000010 66 #define AM_REG_CTIMER_CMPRA1_O 0x00000014 67 #define AM_REG_CTIMER_CMPRB1_O 0x00000018 68 #define AM_REG_CTIMER_CTRL1_O 0x0000001C 69 #define AM_REG_CTIMER_TMR2_O 0x00000020 70 #define AM_REG_CTIMER_CMPRA2_O 0x00000024 71 #define AM_REG_CTIMER_CMPRB2_O 0x00000028 72 #define AM_REG_CTIMER_CTRL2_O 0x0000002C 73 #define AM_REG_CTIMER_TMR3_O 0x00000030 74 #define AM_REG_CTIMER_CMPRA3_O 0x00000034 75 #define AM_REG_CTIMER_CMPRB3_O 0x00000038 76 #define AM_REG_CTIMER_CTRL3_O 0x0000003C 77 #define AM_REG_CTIMER_STCFG_O 0x00000100 78 #define AM_REG_CTIMER_STTMR_O 0x00000104 79 #define AM_REG_CTIMER_CAPTURE_CONTROL_O 0x00000108 80 #define AM_REG_CTIMER_SCMPR0_O 0x00000110 81 #define AM_REG_CTIMER_SCMPR1_O 0x00000114 82 #define AM_REG_CTIMER_SCMPR2_O 0x00000118 83 #define AM_REG_CTIMER_SCMPR3_O 0x0000011C 84 #define AM_REG_CTIMER_SCMPR4_O 0x00000120 85 #define AM_REG_CTIMER_SCMPR5_O 0x00000124 86 #define AM_REG_CTIMER_SCMPR6_O 0x00000128 87 #define AM_REG_CTIMER_SCMPR7_O 0x0000012C 88 #define AM_REG_CTIMER_SCAPT0_O 0x000001E0 89 #define AM_REG_CTIMER_SCAPT1_O 0x000001E4 90 #define AM_REG_CTIMER_SCAPT2_O 0x000001E8 91 #define AM_REG_CTIMER_SCAPT3_O 0x000001EC 92 #define AM_REG_CTIMER_SNVR0_O 0x000001F0 93 #define AM_REG_CTIMER_SNVR1_O 0x000001F4 94 #define AM_REG_CTIMER_SNVR2_O 0x000001F8 95 #define AM_REG_CTIMER_INTEN_O 0x00000200 96 #define AM_REG_CTIMER_INTSTAT_O 0x00000204 97 #define AM_REG_CTIMER_INTCLR_O 0x00000208 98 #define AM_REG_CTIMER_INTSET_O 0x0000020C 99 #define AM_REG_CTIMER_STMINTEN_O 0x00000300 100 #define AM_REG_CTIMER_STMINTSTAT_O 0x00000304 101 #define AM_REG_CTIMER_STMINTCLR_O 0x00000308 102 #define AM_REG_CTIMER_STMINTSET_O 0x0000030C 103 104 //***************************************************************************** 105 // 106 // CTIMER_INTEN - Counter/Timer Interrupts: Enable 107 // 108 //***************************************************************************** 109 // Counter/Timer B3 interrupt based on COMPR1. 110 #define AM_REG_CTIMER_INTEN_CTMRB3C1INT_S 15 111 #define AM_REG_CTIMER_INTEN_CTMRB3C1INT_M 0x00008000 112 #define AM_REG_CTIMER_INTEN_CTMRB3C1INT(n) (((uint32_t)(n) << 15) & 0x00008000) 113 114 // Counter/Timer A3 interrupt based on COMPR1. 115 #define AM_REG_CTIMER_INTEN_CTMRA3C1INT_S 14 116 #define AM_REG_CTIMER_INTEN_CTMRA3C1INT_M 0x00004000 117 #define AM_REG_CTIMER_INTEN_CTMRA3C1INT(n) (((uint32_t)(n) << 14) & 0x00004000) 118 119 // Counter/Timer B2 interrupt based on COMPR1. 120 #define AM_REG_CTIMER_INTEN_CTMRB2C1INT_S 13 121 #define AM_REG_CTIMER_INTEN_CTMRB2C1INT_M 0x00002000 122 #define AM_REG_CTIMER_INTEN_CTMRB2C1INT(n) (((uint32_t)(n) << 13) & 0x00002000) 123 124 // Counter/Timer A2 interrupt based on COMPR1. 125 #define AM_REG_CTIMER_INTEN_CTMRA2C1INT_S 12 126 #define AM_REG_CTIMER_INTEN_CTMRA2C1INT_M 0x00001000 127 #define AM_REG_CTIMER_INTEN_CTMRA2C1INT(n) (((uint32_t)(n) << 12) & 0x00001000) 128 129 // Counter/Timer B1 interrupt based on COMPR1. 130 #define AM_REG_CTIMER_INTEN_CTMRB1C1INT_S 11 131 #define AM_REG_CTIMER_INTEN_CTMRB1C1INT_M 0x00000800 132 #define AM_REG_CTIMER_INTEN_CTMRB1C1INT(n) (((uint32_t)(n) << 11) & 0x00000800) 133 134 // Counter/Timer A1 interrupt based on COMPR1. 135 #define AM_REG_CTIMER_INTEN_CTMRA1C1INT_S 10 136 #define AM_REG_CTIMER_INTEN_CTMRA1C1INT_M 0x00000400 137 #define AM_REG_CTIMER_INTEN_CTMRA1C1INT(n) (((uint32_t)(n) << 10) & 0x00000400) 138 139 // Counter/Timer B0 interrupt based on COMPR1. 140 #define AM_REG_CTIMER_INTEN_CTMRB0C1INT_S 9 141 #define AM_REG_CTIMER_INTEN_CTMRB0C1INT_M 0x00000200 142 #define AM_REG_CTIMER_INTEN_CTMRB0C1INT(n) (((uint32_t)(n) << 9) & 0x00000200) 143 144 // Counter/Timer A0 interrupt based on COMPR1. 145 #define AM_REG_CTIMER_INTEN_CTMRA0C1INT_S 8 146 #define AM_REG_CTIMER_INTEN_CTMRA0C1INT_M 0x00000100 147 #define AM_REG_CTIMER_INTEN_CTMRA0C1INT(n) (((uint32_t)(n) << 8) & 0x00000100) 148 149 // Counter/Timer B3 interrupt based on COMPR0. 150 #define AM_REG_CTIMER_INTEN_CTMRB3C0INT_S 7 151 #define AM_REG_CTIMER_INTEN_CTMRB3C0INT_M 0x00000080 152 #define AM_REG_CTIMER_INTEN_CTMRB3C0INT(n) (((uint32_t)(n) << 7) & 0x00000080) 153 154 // Counter/Timer A3 interrupt based on COMPR0. 155 #define AM_REG_CTIMER_INTEN_CTMRA3C0INT_S 6 156 #define AM_REG_CTIMER_INTEN_CTMRA3C0INT_M 0x00000040 157 #define AM_REG_CTIMER_INTEN_CTMRA3C0INT(n) (((uint32_t)(n) << 6) & 0x00000040) 158 159 // Counter/Timer B2 interrupt based on COMPR0. 160 #define AM_REG_CTIMER_INTEN_CTMRB2C0INT_S 5 161 #define AM_REG_CTIMER_INTEN_CTMRB2C0INT_M 0x00000020 162 #define AM_REG_CTIMER_INTEN_CTMRB2C0INT(n) (((uint32_t)(n) << 5) & 0x00000020) 163 164 // Counter/Timer A2 interrupt based on COMPR0. 165 #define AM_REG_CTIMER_INTEN_CTMRA2C0INT_S 4 166 #define AM_REG_CTIMER_INTEN_CTMRA2C0INT_M 0x00000010 167 #define AM_REG_CTIMER_INTEN_CTMRA2C0INT(n) (((uint32_t)(n) << 4) & 0x00000010) 168 169 // Counter/Timer B1 interrupt based on COMPR0. 170 #define AM_REG_CTIMER_INTEN_CTMRB1C0INT_S 3 171 #define AM_REG_CTIMER_INTEN_CTMRB1C0INT_M 0x00000008 172 #define AM_REG_CTIMER_INTEN_CTMRB1C0INT(n) (((uint32_t)(n) << 3) & 0x00000008) 173 174 // Counter/Timer A1 interrupt based on COMPR0. 175 #define AM_REG_CTIMER_INTEN_CTMRA1C0INT_S 2 176 #define AM_REG_CTIMER_INTEN_CTMRA1C0INT_M 0x00000004 177 #define AM_REG_CTIMER_INTEN_CTMRA1C0INT(n) (((uint32_t)(n) << 2) & 0x00000004) 178 179 // Counter/Timer B0 interrupt based on COMPR0. 180 #define AM_REG_CTIMER_INTEN_CTMRB0C0INT_S 1 181 #define AM_REG_CTIMER_INTEN_CTMRB0C0INT_M 0x00000002 182 #define AM_REG_CTIMER_INTEN_CTMRB0C0INT(n) (((uint32_t)(n) << 1) & 0x00000002) 183 184 // Counter/Timer A0 interrupt based on COMPR0. 185 #define AM_REG_CTIMER_INTEN_CTMRA0C0INT_S 0 186 #define AM_REG_CTIMER_INTEN_CTMRA0C0INT_M 0x00000001 187 #define AM_REG_CTIMER_INTEN_CTMRA0C0INT(n) (((uint32_t)(n) << 0) & 0x00000001) 188 189 //***************************************************************************** 190 // 191 // CTIMER_INTSTAT - Counter/Timer Interrupts: Status 192 // 193 //***************************************************************************** 194 // Counter/Timer B3 interrupt based on COMPR1. 195 #define AM_REG_CTIMER_INTSTAT_CTMRB3C1INT_S 15 196 #define AM_REG_CTIMER_INTSTAT_CTMRB3C1INT_M 0x00008000 197 #define AM_REG_CTIMER_INTSTAT_CTMRB3C1INT(n) (((uint32_t)(n) << 15) & 0x00008000) 198 199 // Counter/Timer A3 interrupt based on COMPR1. 200 #define AM_REG_CTIMER_INTSTAT_CTMRA3C1INT_S 14 201 #define AM_REG_CTIMER_INTSTAT_CTMRA3C1INT_M 0x00004000 202 #define AM_REG_CTIMER_INTSTAT_CTMRA3C1INT(n) (((uint32_t)(n) << 14) & 0x00004000) 203 204 // Counter/Timer B2 interrupt based on COMPR1. 205 #define AM_REG_CTIMER_INTSTAT_CTMRB2C1INT_S 13 206 #define AM_REG_CTIMER_INTSTAT_CTMRB2C1INT_M 0x00002000 207 #define AM_REG_CTIMER_INTSTAT_CTMRB2C1INT(n) (((uint32_t)(n) << 13) & 0x00002000) 208 209 // Counter/Timer A2 interrupt based on COMPR1. 210 #define AM_REG_CTIMER_INTSTAT_CTMRA2C1INT_S 12 211 #define AM_REG_CTIMER_INTSTAT_CTMRA2C1INT_M 0x00001000 212 #define AM_REG_CTIMER_INTSTAT_CTMRA2C1INT(n) (((uint32_t)(n) << 12) & 0x00001000) 213 214 // Counter/Timer B1 interrupt based on COMPR1. 215 #define AM_REG_CTIMER_INTSTAT_CTMRB1C1INT_S 11 216 #define AM_REG_CTIMER_INTSTAT_CTMRB1C1INT_M 0x00000800 217 #define AM_REG_CTIMER_INTSTAT_CTMRB1C1INT(n) (((uint32_t)(n) << 11) & 0x00000800) 218 219 // Counter/Timer A1 interrupt based on COMPR1. 220 #define AM_REG_CTIMER_INTSTAT_CTMRA1C1INT_S 10 221 #define AM_REG_CTIMER_INTSTAT_CTMRA1C1INT_M 0x00000400 222 #define AM_REG_CTIMER_INTSTAT_CTMRA1C1INT(n) (((uint32_t)(n) << 10) & 0x00000400) 223 224 // Counter/Timer B0 interrupt based on COMPR1. 225 #define AM_REG_CTIMER_INTSTAT_CTMRB0C1INT_S 9 226 #define AM_REG_CTIMER_INTSTAT_CTMRB0C1INT_M 0x00000200 227 #define AM_REG_CTIMER_INTSTAT_CTMRB0C1INT(n) (((uint32_t)(n) << 9) & 0x00000200) 228 229 // Counter/Timer A0 interrupt based on COMPR1. 230 #define AM_REG_CTIMER_INTSTAT_CTMRA0C1INT_S 8 231 #define AM_REG_CTIMER_INTSTAT_CTMRA0C1INT_M 0x00000100 232 #define AM_REG_CTIMER_INTSTAT_CTMRA0C1INT(n) (((uint32_t)(n) << 8) & 0x00000100) 233 234 // Counter/Timer B3 interrupt based on COMPR0. 235 #define AM_REG_CTIMER_INTSTAT_CTMRB3C0INT_S 7 236 #define AM_REG_CTIMER_INTSTAT_CTMRB3C0INT_M 0x00000080 237 #define AM_REG_CTIMER_INTSTAT_CTMRB3C0INT(n) (((uint32_t)(n) << 7) & 0x00000080) 238 239 // Counter/Timer A3 interrupt based on COMPR0. 240 #define AM_REG_CTIMER_INTSTAT_CTMRA3C0INT_S 6 241 #define AM_REG_CTIMER_INTSTAT_CTMRA3C0INT_M 0x00000040 242 #define AM_REG_CTIMER_INTSTAT_CTMRA3C0INT(n) (((uint32_t)(n) << 6) & 0x00000040) 243 244 // Counter/Timer B2 interrupt based on COMPR0. 245 #define AM_REG_CTIMER_INTSTAT_CTMRB2C0INT_S 5 246 #define AM_REG_CTIMER_INTSTAT_CTMRB2C0INT_M 0x00000020 247 #define AM_REG_CTIMER_INTSTAT_CTMRB2C0INT(n) (((uint32_t)(n) << 5) & 0x00000020) 248 249 // Counter/Timer A2 interrupt based on COMPR0. 250 #define AM_REG_CTIMER_INTSTAT_CTMRA2C0INT_S 4 251 #define AM_REG_CTIMER_INTSTAT_CTMRA2C0INT_M 0x00000010 252 #define AM_REG_CTIMER_INTSTAT_CTMRA2C0INT(n) (((uint32_t)(n) << 4) & 0x00000010) 253 254 // Counter/Timer B1 interrupt based on COMPR0. 255 #define AM_REG_CTIMER_INTSTAT_CTMRB1C0INT_S 3 256 #define AM_REG_CTIMER_INTSTAT_CTMRB1C0INT_M 0x00000008 257 #define AM_REG_CTIMER_INTSTAT_CTMRB1C0INT(n) (((uint32_t)(n) << 3) & 0x00000008) 258 259 // Counter/Timer A1 interrupt based on COMPR0. 260 #define AM_REG_CTIMER_INTSTAT_CTMRA1C0INT_S 2 261 #define AM_REG_CTIMER_INTSTAT_CTMRA1C0INT_M 0x00000004 262 #define AM_REG_CTIMER_INTSTAT_CTMRA1C0INT(n) (((uint32_t)(n) << 2) & 0x00000004) 263 264 // Counter/Timer B0 interrupt based on COMPR0. 265 #define AM_REG_CTIMER_INTSTAT_CTMRB0C0INT_S 1 266 #define AM_REG_CTIMER_INTSTAT_CTMRB0C0INT_M 0x00000002 267 #define AM_REG_CTIMER_INTSTAT_CTMRB0C0INT(n) (((uint32_t)(n) << 1) & 0x00000002) 268 269 // Counter/Timer A0 interrupt based on COMPR0. 270 #define AM_REG_CTIMER_INTSTAT_CTMRA0C0INT_S 0 271 #define AM_REG_CTIMER_INTSTAT_CTMRA0C0INT_M 0x00000001 272 #define AM_REG_CTIMER_INTSTAT_CTMRA0C0INT(n) (((uint32_t)(n) << 0) & 0x00000001) 273 274 //***************************************************************************** 275 // 276 // CTIMER_INTCLR - Counter/Timer Interrupts: Clear 277 // 278 //***************************************************************************** 279 // Counter/Timer B3 interrupt based on COMPR1. 280 #define AM_REG_CTIMER_INTCLR_CTMRB3C1INT_S 15 281 #define AM_REG_CTIMER_INTCLR_CTMRB3C1INT_M 0x00008000 282 #define AM_REG_CTIMER_INTCLR_CTMRB3C1INT(n) (((uint32_t)(n) << 15) & 0x00008000) 283 284 // Counter/Timer A3 interrupt based on COMPR1. 285 #define AM_REG_CTIMER_INTCLR_CTMRA3C1INT_S 14 286 #define AM_REG_CTIMER_INTCLR_CTMRA3C1INT_M 0x00004000 287 #define AM_REG_CTIMER_INTCLR_CTMRA3C1INT(n) (((uint32_t)(n) << 14) & 0x00004000) 288 289 // Counter/Timer B2 interrupt based on COMPR1. 290 #define AM_REG_CTIMER_INTCLR_CTMRB2C1INT_S 13 291 #define AM_REG_CTIMER_INTCLR_CTMRB2C1INT_M 0x00002000 292 #define AM_REG_CTIMER_INTCLR_CTMRB2C1INT(n) (((uint32_t)(n) << 13) & 0x00002000) 293 294 // Counter/Timer A2 interrupt based on COMPR1. 295 #define AM_REG_CTIMER_INTCLR_CTMRA2C1INT_S 12 296 #define AM_REG_CTIMER_INTCLR_CTMRA2C1INT_M 0x00001000 297 #define AM_REG_CTIMER_INTCLR_CTMRA2C1INT(n) (((uint32_t)(n) << 12) & 0x00001000) 298 299 // Counter/Timer B1 interrupt based on COMPR1. 300 #define AM_REG_CTIMER_INTCLR_CTMRB1C1INT_S 11 301 #define AM_REG_CTIMER_INTCLR_CTMRB1C1INT_M 0x00000800 302 #define AM_REG_CTIMER_INTCLR_CTMRB1C1INT(n) (((uint32_t)(n) << 11) & 0x00000800) 303 304 // Counter/Timer A1 interrupt based on COMPR1. 305 #define AM_REG_CTIMER_INTCLR_CTMRA1C1INT_S 10 306 #define AM_REG_CTIMER_INTCLR_CTMRA1C1INT_M 0x00000400 307 #define AM_REG_CTIMER_INTCLR_CTMRA1C1INT(n) (((uint32_t)(n) << 10) & 0x00000400) 308 309 // Counter/Timer B0 interrupt based on COMPR1. 310 #define AM_REG_CTIMER_INTCLR_CTMRB0C1INT_S 9 311 #define AM_REG_CTIMER_INTCLR_CTMRB0C1INT_M 0x00000200 312 #define AM_REG_CTIMER_INTCLR_CTMRB0C1INT(n) (((uint32_t)(n) << 9) & 0x00000200) 313 314 // Counter/Timer A0 interrupt based on COMPR1. 315 #define AM_REG_CTIMER_INTCLR_CTMRA0C1INT_S 8 316 #define AM_REG_CTIMER_INTCLR_CTMRA0C1INT_M 0x00000100 317 #define AM_REG_CTIMER_INTCLR_CTMRA0C1INT(n) (((uint32_t)(n) << 8) & 0x00000100) 318 319 // Counter/Timer B3 interrupt based on COMPR0. 320 #define AM_REG_CTIMER_INTCLR_CTMRB3C0INT_S 7 321 #define AM_REG_CTIMER_INTCLR_CTMRB3C0INT_M 0x00000080 322 #define AM_REG_CTIMER_INTCLR_CTMRB3C0INT(n) (((uint32_t)(n) << 7) & 0x00000080) 323 324 // Counter/Timer A3 interrupt based on COMPR0. 325 #define AM_REG_CTIMER_INTCLR_CTMRA3C0INT_S 6 326 #define AM_REG_CTIMER_INTCLR_CTMRA3C0INT_M 0x00000040 327 #define AM_REG_CTIMER_INTCLR_CTMRA3C0INT(n) (((uint32_t)(n) << 6) & 0x00000040) 328 329 // Counter/Timer B2 interrupt based on COMPR0. 330 #define AM_REG_CTIMER_INTCLR_CTMRB2C0INT_S 5 331 #define AM_REG_CTIMER_INTCLR_CTMRB2C0INT_M 0x00000020 332 #define AM_REG_CTIMER_INTCLR_CTMRB2C0INT(n) (((uint32_t)(n) << 5) & 0x00000020) 333 334 // Counter/Timer A2 interrupt based on COMPR0. 335 #define AM_REG_CTIMER_INTCLR_CTMRA2C0INT_S 4 336 #define AM_REG_CTIMER_INTCLR_CTMRA2C0INT_M 0x00000010 337 #define AM_REG_CTIMER_INTCLR_CTMRA2C0INT(n) (((uint32_t)(n) << 4) & 0x00000010) 338 339 // Counter/Timer B1 interrupt based on COMPR0. 340 #define AM_REG_CTIMER_INTCLR_CTMRB1C0INT_S 3 341 #define AM_REG_CTIMER_INTCLR_CTMRB1C0INT_M 0x00000008 342 #define AM_REG_CTIMER_INTCLR_CTMRB1C0INT(n) (((uint32_t)(n) << 3) & 0x00000008) 343 344 // Counter/Timer A1 interrupt based on COMPR0. 345 #define AM_REG_CTIMER_INTCLR_CTMRA1C0INT_S 2 346 #define AM_REG_CTIMER_INTCLR_CTMRA1C0INT_M 0x00000004 347 #define AM_REG_CTIMER_INTCLR_CTMRA1C0INT(n) (((uint32_t)(n) << 2) & 0x00000004) 348 349 // Counter/Timer B0 interrupt based on COMPR0. 350 #define AM_REG_CTIMER_INTCLR_CTMRB0C0INT_S 1 351 #define AM_REG_CTIMER_INTCLR_CTMRB0C0INT_M 0x00000002 352 #define AM_REG_CTIMER_INTCLR_CTMRB0C0INT(n) (((uint32_t)(n) << 1) & 0x00000002) 353 354 // Counter/Timer A0 interrupt based on COMPR0. 355 #define AM_REG_CTIMER_INTCLR_CTMRA0C0INT_S 0 356 #define AM_REG_CTIMER_INTCLR_CTMRA0C0INT_M 0x00000001 357 #define AM_REG_CTIMER_INTCLR_CTMRA0C0INT(n) (((uint32_t)(n) << 0) & 0x00000001) 358 359 //***************************************************************************** 360 // 361 // CTIMER_INTSET - Counter/Timer Interrupts: Set 362 // 363 //***************************************************************************** 364 // Counter/Timer B3 interrupt based on COMPR1. 365 #define AM_REG_CTIMER_INTSET_CTMRB3C1INT_S 15 366 #define AM_REG_CTIMER_INTSET_CTMRB3C1INT_M 0x00008000 367 #define AM_REG_CTIMER_INTSET_CTMRB3C1INT(n) (((uint32_t)(n) << 15) & 0x00008000) 368 369 // Counter/Timer A3 interrupt based on COMPR1. 370 #define AM_REG_CTIMER_INTSET_CTMRA3C1INT_S 14 371 #define AM_REG_CTIMER_INTSET_CTMRA3C1INT_M 0x00004000 372 #define AM_REG_CTIMER_INTSET_CTMRA3C1INT(n) (((uint32_t)(n) << 14) & 0x00004000) 373 374 // Counter/Timer B2 interrupt based on COMPR1. 375 #define AM_REG_CTIMER_INTSET_CTMRB2C1INT_S 13 376 #define AM_REG_CTIMER_INTSET_CTMRB2C1INT_M 0x00002000 377 #define AM_REG_CTIMER_INTSET_CTMRB2C1INT(n) (((uint32_t)(n) << 13) & 0x00002000) 378 379 // Counter/Timer A2 interrupt based on COMPR1. 380 #define AM_REG_CTIMER_INTSET_CTMRA2C1INT_S 12 381 #define AM_REG_CTIMER_INTSET_CTMRA2C1INT_M 0x00001000 382 #define AM_REG_CTIMER_INTSET_CTMRA2C1INT(n) (((uint32_t)(n) << 12) & 0x00001000) 383 384 // Counter/Timer B1 interrupt based on COMPR1. 385 #define AM_REG_CTIMER_INTSET_CTMRB1C1INT_S 11 386 #define AM_REG_CTIMER_INTSET_CTMRB1C1INT_M 0x00000800 387 #define AM_REG_CTIMER_INTSET_CTMRB1C1INT(n) (((uint32_t)(n) << 11) & 0x00000800) 388 389 // Counter/Timer A1 interrupt based on COMPR1. 390 #define AM_REG_CTIMER_INTSET_CTMRA1C1INT_S 10 391 #define AM_REG_CTIMER_INTSET_CTMRA1C1INT_M 0x00000400 392 #define AM_REG_CTIMER_INTSET_CTMRA1C1INT(n) (((uint32_t)(n) << 10) & 0x00000400) 393 394 // Counter/Timer B0 interrupt based on COMPR1. 395 #define AM_REG_CTIMER_INTSET_CTMRB0C1INT_S 9 396 #define AM_REG_CTIMER_INTSET_CTMRB0C1INT_M 0x00000200 397 #define AM_REG_CTIMER_INTSET_CTMRB0C1INT(n) (((uint32_t)(n) << 9) & 0x00000200) 398 399 // Counter/Timer A0 interrupt based on COMPR1. 400 #define AM_REG_CTIMER_INTSET_CTMRA0C1INT_S 8 401 #define AM_REG_CTIMER_INTSET_CTMRA0C1INT_M 0x00000100 402 #define AM_REG_CTIMER_INTSET_CTMRA0C1INT(n) (((uint32_t)(n) << 8) & 0x00000100) 403 404 // Counter/Timer B3 interrupt based on COMPR0. 405 #define AM_REG_CTIMER_INTSET_CTMRB3C0INT_S 7 406 #define AM_REG_CTIMER_INTSET_CTMRB3C0INT_M 0x00000080 407 #define AM_REG_CTIMER_INTSET_CTMRB3C0INT(n) (((uint32_t)(n) << 7) & 0x00000080) 408 409 // Counter/Timer A3 interrupt based on COMPR0. 410 #define AM_REG_CTIMER_INTSET_CTMRA3C0INT_S 6 411 #define AM_REG_CTIMER_INTSET_CTMRA3C0INT_M 0x00000040 412 #define AM_REG_CTIMER_INTSET_CTMRA3C0INT(n) (((uint32_t)(n) << 6) & 0x00000040) 413 414 // Counter/Timer B2 interrupt based on COMPR0. 415 #define AM_REG_CTIMER_INTSET_CTMRB2C0INT_S 5 416 #define AM_REG_CTIMER_INTSET_CTMRB2C0INT_M 0x00000020 417 #define AM_REG_CTIMER_INTSET_CTMRB2C0INT(n) (((uint32_t)(n) << 5) & 0x00000020) 418 419 // Counter/Timer A2 interrupt based on COMPR0. 420 #define AM_REG_CTIMER_INTSET_CTMRA2C0INT_S 4 421 #define AM_REG_CTIMER_INTSET_CTMRA2C0INT_M 0x00000010 422 #define AM_REG_CTIMER_INTSET_CTMRA2C0INT(n) (((uint32_t)(n) << 4) & 0x00000010) 423 424 // Counter/Timer B1 interrupt based on COMPR0. 425 #define AM_REG_CTIMER_INTSET_CTMRB1C0INT_S 3 426 #define AM_REG_CTIMER_INTSET_CTMRB1C0INT_M 0x00000008 427 #define AM_REG_CTIMER_INTSET_CTMRB1C0INT(n) (((uint32_t)(n) << 3) & 0x00000008) 428 429 // Counter/Timer A1 interrupt based on COMPR0. 430 #define AM_REG_CTIMER_INTSET_CTMRA1C0INT_S 2 431 #define AM_REG_CTIMER_INTSET_CTMRA1C0INT_M 0x00000004 432 #define AM_REG_CTIMER_INTSET_CTMRA1C0INT(n) (((uint32_t)(n) << 2) & 0x00000004) 433 434 // Counter/Timer B0 interrupt based on COMPR0. 435 #define AM_REG_CTIMER_INTSET_CTMRB0C0INT_S 1 436 #define AM_REG_CTIMER_INTSET_CTMRB0C0INT_M 0x00000002 437 #define AM_REG_CTIMER_INTSET_CTMRB0C0INT(n) (((uint32_t)(n) << 1) & 0x00000002) 438 439 // Counter/Timer A0 interrupt based on COMPR0. 440 #define AM_REG_CTIMER_INTSET_CTMRA0C0INT_S 0 441 #define AM_REG_CTIMER_INTSET_CTMRA0C0INT_M 0x00000001 442 #define AM_REG_CTIMER_INTSET_CTMRA0C0INT(n) (((uint32_t)(n) << 0) & 0x00000001) 443 444 //***************************************************************************** 445 // 446 // CTIMER_STMINTEN - STIMER Interrupt registers: Enable 447 // 448 //***************************************************************************** 449 // CAPTURE register D has grabbed the value in the counter 450 #define AM_REG_CTIMER_STMINTEN_CAPTURED_S 12 451 #define AM_REG_CTIMER_STMINTEN_CAPTURED_M 0x00001000 452 #define AM_REG_CTIMER_STMINTEN_CAPTURED(n) (((uint32_t)(n) << 12) & 0x00001000) 453 #define AM_REG_CTIMER_STMINTEN_CAPTURED_CAPD_INT 0x00001000 454 455 // CAPTURE register C has grabbed the value in the counter 456 #define AM_REG_CTIMER_STMINTEN_CAPTUREC_S 11 457 #define AM_REG_CTIMER_STMINTEN_CAPTUREC_M 0x00000800 458 #define AM_REG_CTIMER_STMINTEN_CAPTUREC(n) (((uint32_t)(n) << 11) & 0x00000800) 459 #define AM_REG_CTIMER_STMINTEN_CAPTUREC_CAPC_INT 0x00000800 460 461 // CAPTURE register B has grabbed the value in the counter 462 #define AM_REG_CTIMER_STMINTEN_CAPTUREB_S 10 463 #define AM_REG_CTIMER_STMINTEN_CAPTUREB_M 0x00000400 464 #define AM_REG_CTIMER_STMINTEN_CAPTUREB(n) (((uint32_t)(n) << 10) & 0x00000400) 465 #define AM_REG_CTIMER_STMINTEN_CAPTUREB_CAPB_INT 0x00000400 466 467 // CAPTURE register A has grabbed the value in the counter 468 #define AM_REG_CTIMER_STMINTEN_CAPTUREA_S 9 469 #define AM_REG_CTIMER_STMINTEN_CAPTUREA_M 0x00000200 470 #define AM_REG_CTIMER_STMINTEN_CAPTUREA(n) (((uint32_t)(n) << 9) & 0x00000200) 471 #define AM_REG_CTIMER_STMINTEN_CAPTUREA_CAPA_INT 0x00000200 472 473 // COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. 474 #define AM_REG_CTIMER_STMINTEN_OVERFLOW_S 8 475 #define AM_REG_CTIMER_STMINTEN_OVERFLOW_M 0x00000100 476 #define AM_REG_CTIMER_STMINTEN_OVERFLOW(n) (((uint32_t)(n) << 8) & 0x00000100) 477 #define AM_REG_CTIMER_STMINTEN_OVERFLOW_OFLOW_INT 0x00000100 478 479 // COUNTER is greater than or equal to COMPARE register H. 480 #define AM_REG_CTIMER_STMINTEN_COMPAREH_S 7 481 #define AM_REG_CTIMER_STMINTEN_COMPAREH_M 0x00000080 482 #define AM_REG_CTIMER_STMINTEN_COMPAREH(n) (((uint32_t)(n) << 7) & 0x00000080) 483 #define AM_REG_CTIMER_STMINTEN_COMPAREH_COMPARED 0x00000080 484 485 // COUNTER is greater than or equal to COMPARE register G. 486 #define AM_REG_CTIMER_STMINTEN_COMPAREG_S 6 487 #define AM_REG_CTIMER_STMINTEN_COMPAREG_M 0x00000040 488 #define AM_REG_CTIMER_STMINTEN_COMPAREG(n) (((uint32_t)(n) << 6) & 0x00000040) 489 #define AM_REG_CTIMER_STMINTEN_COMPAREG_COMPARED 0x00000040 490 491 // COUNTER is greater than or equal to COMPARE register F. 492 #define AM_REG_CTIMER_STMINTEN_COMPAREF_S 5 493 #define AM_REG_CTIMER_STMINTEN_COMPAREF_M 0x00000020 494 #define AM_REG_CTIMER_STMINTEN_COMPAREF(n) (((uint32_t)(n) << 5) & 0x00000020) 495 #define AM_REG_CTIMER_STMINTEN_COMPAREF_COMPARED 0x00000020 496 497 // COUNTER is greater than or equal to COMPARE register E. 498 #define AM_REG_CTIMER_STMINTEN_COMPAREE_S 4 499 #define AM_REG_CTIMER_STMINTEN_COMPAREE_M 0x00000010 500 #define AM_REG_CTIMER_STMINTEN_COMPAREE(n) (((uint32_t)(n) << 4) & 0x00000010) 501 #define AM_REG_CTIMER_STMINTEN_COMPAREE_COMPARED 0x00000010 502 503 // COUNTER is greater than or equal to COMPARE register D. 504 #define AM_REG_CTIMER_STMINTEN_COMPARED_S 3 505 #define AM_REG_CTIMER_STMINTEN_COMPARED_M 0x00000008 506 #define AM_REG_CTIMER_STMINTEN_COMPARED(n) (((uint32_t)(n) << 3) & 0x00000008) 507 #define AM_REG_CTIMER_STMINTEN_COMPARED_COMPARED 0x00000008 508 509 // COUNTER is greater than or equal to COMPARE register C. 510 #define AM_REG_CTIMER_STMINTEN_COMPAREC_S 2 511 #define AM_REG_CTIMER_STMINTEN_COMPAREC_M 0x00000004 512 #define AM_REG_CTIMER_STMINTEN_COMPAREC(n) (((uint32_t)(n) << 2) & 0x00000004) 513 #define AM_REG_CTIMER_STMINTEN_COMPAREC_COMPARED 0x00000004 514 515 // COUNTER is greater than or equal to COMPARE register B. 516 #define AM_REG_CTIMER_STMINTEN_COMPAREB_S 1 517 #define AM_REG_CTIMER_STMINTEN_COMPAREB_M 0x00000002 518 #define AM_REG_CTIMER_STMINTEN_COMPAREB(n) (((uint32_t)(n) << 1) & 0x00000002) 519 #define AM_REG_CTIMER_STMINTEN_COMPAREB_COMPARED 0x00000002 520 521 // COUNTER is greater than or equal to COMPARE register A. 522 #define AM_REG_CTIMER_STMINTEN_COMPAREA_S 0 523 #define AM_REG_CTIMER_STMINTEN_COMPAREA_M 0x00000001 524 #define AM_REG_CTIMER_STMINTEN_COMPAREA(n) (((uint32_t)(n) << 0) & 0x00000001) 525 #define AM_REG_CTIMER_STMINTEN_COMPAREA_COMPARED 0x00000001 526 527 //***************************************************************************** 528 // 529 // CTIMER_STMINTSTAT - STIMER Interrupt registers: Status 530 // 531 //***************************************************************************** 532 // CAPTURE register D has grabbed the value in the counter 533 #define AM_REG_CTIMER_STMINTSTAT_CAPTURED_S 12 534 #define AM_REG_CTIMER_STMINTSTAT_CAPTURED_M 0x00001000 535 #define AM_REG_CTIMER_STMINTSTAT_CAPTURED(n) (((uint32_t)(n) << 12) & 0x00001000) 536 #define AM_REG_CTIMER_STMINTSTAT_CAPTURED_CAPD_INT 0x00001000 537 538 // CAPTURE register C has grabbed the value in the counter 539 #define AM_REG_CTIMER_STMINTSTAT_CAPTUREC_S 11 540 #define AM_REG_CTIMER_STMINTSTAT_CAPTUREC_M 0x00000800 541 #define AM_REG_CTIMER_STMINTSTAT_CAPTUREC(n) (((uint32_t)(n) << 11) & 0x00000800) 542 #define AM_REG_CTIMER_STMINTSTAT_CAPTUREC_CAPC_INT 0x00000800 543 544 // CAPTURE register B has grabbed the value in the counter 545 #define AM_REG_CTIMER_STMINTSTAT_CAPTUREB_S 10 546 #define AM_REG_CTIMER_STMINTSTAT_CAPTUREB_M 0x00000400 547 #define AM_REG_CTIMER_STMINTSTAT_CAPTUREB(n) (((uint32_t)(n) << 10) & 0x00000400) 548 #define AM_REG_CTIMER_STMINTSTAT_CAPTUREB_CAPB_INT 0x00000400 549 550 // CAPTURE register A has grabbed the value in the counter 551 #define AM_REG_CTIMER_STMINTSTAT_CAPTUREA_S 9 552 #define AM_REG_CTIMER_STMINTSTAT_CAPTUREA_M 0x00000200 553 #define AM_REG_CTIMER_STMINTSTAT_CAPTUREA(n) (((uint32_t)(n) << 9) & 0x00000200) 554 #define AM_REG_CTIMER_STMINTSTAT_CAPTUREA_CAPA_INT 0x00000200 555 556 // COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. 557 #define AM_REG_CTIMER_STMINTSTAT_OVERFLOW_S 8 558 #define AM_REG_CTIMER_STMINTSTAT_OVERFLOW_M 0x00000100 559 #define AM_REG_CTIMER_STMINTSTAT_OVERFLOW(n) (((uint32_t)(n) << 8) & 0x00000100) 560 #define AM_REG_CTIMER_STMINTSTAT_OVERFLOW_OFLOW_INT 0x00000100 561 562 // COUNTER is greater than or equal to COMPARE register H. 563 #define AM_REG_CTIMER_STMINTSTAT_COMPAREH_S 7 564 #define AM_REG_CTIMER_STMINTSTAT_COMPAREH_M 0x00000080 565 #define AM_REG_CTIMER_STMINTSTAT_COMPAREH(n) (((uint32_t)(n) << 7) & 0x00000080) 566 #define AM_REG_CTIMER_STMINTSTAT_COMPAREH_COMPARED 0x00000080 567 568 // COUNTER is greater than or equal to COMPARE register G. 569 #define AM_REG_CTIMER_STMINTSTAT_COMPAREG_S 6 570 #define AM_REG_CTIMER_STMINTSTAT_COMPAREG_M 0x00000040 571 #define AM_REG_CTIMER_STMINTSTAT_COMPAREG(n) (((uint32_t)(n) << 6) & 0x00000040) 572 #define AM_REG_CTIMER_STMINTSTAT_COMPAREG_COMPARED 0x00000040 573 574 // COUNTER is greater than or equal to COMPARE register F. 575 #define AM_REG_CTIMER_STMINTSTAT_COMPAREF_S 5 576 #define AM_REG_CTIMER_STMINTSTAT_COMPAREF_M 0x00000020 577 #define AM_REG_CTIMER_STMINTSTAT_COMPAREF(n) (((uint32_t)(n) << 5) & 0x00000020) 578 #define AM_REG_CTIMER_STMINTSTAT_COMPAREF_COMPARED 0x00000020 579 580 // COUNTER is greater than or equal to COMPARE register E. 581 #define AM_REG_CTIMER_STMINTSTAT_COMPAREE_S 4 582 #define AM_REG_CTIMER_STMINTSTAT_COMPAREE_M 0x00000010 583 #define AM_REG_CTIMER_STMINTSTAT_COMPAREE(n) (((uint32_t)(n) << 4) & 0x00000010) 584 #define AM_REG_CTIMER_STMINTSTAT_COMPAREE_COMPARED 0x00000010 585 586 // COUNTER is greater than or equal to COMPARE register D. 587 #define AM_REG_CTIMER_STMINTSTAT_COMPARED_S 3 588 #define AM_REG_CTIMER_STMINTSTAT_COMPARED_M 0x00000008 589 #define AM_REG_CTIMER_STMINTSTAT_COMPARED(n) (((uint32_t)(n) << 3) & 0x00000008) 590 #define AM_REG_CTIMER_STMINTSTAT_COMPARED_COMPARED 0x00000008 591 592 // COUNTER is greater than or equal to COMPARE register C. 593 #define AM_REG_CTIMER_STMINTSTAT_COMPAREC_S 2 594 #define AM_REG_CTIMER_STMINTSTAT_COMPAREC_M 0x00000004 595 #define AM_REG_CTIMER_STMINTSTAT_COMPAREC(n) (((uint32_t)(n) << 2) & 0x00000004) 596 #define AM_REG_CTIMER_STMINTSTAT_COMPAREC_COMPARED 0x00000004 597 598 // COUNTER is greater than or equal to COMPARE register B. 599 #define AM_REG_CTIMER_STMINTSTAT_COMPAREB_S 1 600 #define AM_REG_CTIMER_STMINTSTAT_COMPAREB_M 0x00000002 601 #define AM_REG_CTIMER_STMINTSTAT_COMPAREB(n) (((uint32_t)(n) << 1) & 0x00000002) 602 #define AM_REG_CTIMER_STMINTSTAT_COMPAREB_COMPARED 0x00000002 603 604 // COUNTER is greater than or equal to COMPARE register A. 605 #define AM_REG_CTIMER_STMINTSTAT_COMPAREA_S 0 606 #define AM_REG_CTIMER_STMINTSTAT_COMPAREA_M 0x00000001 607 #define AM_REG_CTIMER_STMINTSTAT_COMPAREA(n) (((uint32_t)(n) << 0) & 0x00000001) 608 #define AM_REG_CTIMER_STMINTSTAT_COMPAREA_COMPARED 0x00000001 609 610 //***************************************************************************** 611 // 612 // CTIMER_STMINTCLR - STIMER Interrupt registers: Clear 613 // 614 //***************************************************************************** 615 // CAPTURE register D has grabbed the value in the counter 616 #define AM_REG_CTIMER_STMINTCLR_CAPTURED_S 12 617 #define AM_REG_CTIMER_STMINTCLR_CAPTURED_M 0x00001000 618 #define AM_REG_CTIMER_STMINTCLR_CAPTURED(n) (((uint32_t)(n) << 12) & 0x00001000) 619 #define AM_REG_CTIMER_STMINTCLR_CAPTURED_CAPD_INT 0x00001000 620 621 // CAPTURE register C has grabbed the value in the counter 622 #define AM_REG_CTIMER_STMINTCLR_CAPTUREC_S 11 623 #define AM_REG_CTIMER_STMINTCLR_CAPTUREC_M 0x00000800 624 #define AM_REG_CTIMER_STMINTCLR_CAPTUREC(n) (((uint32_t)(n) << 11) & 0x00000800) 625 #define AM_REG_CTIMER_STMINTCLR_CAPTUREC_CAPC_INT 0x00000800 626 627 // CAPTURE register B has grabbed the value in the counter 628 #define AM_REG_CTIMER_STMINTCLR_CAPTUREB_S 10 629 #define AM_REG_CTIMER_STMINTCLR_CAPTUREB_M 0x00000400 630 #define AM_REG_CTIMER_STMINTCLR_CAPTUREB(n) (((uint32_t)(n) << 10) & 0x00000400) 631 #define AM_REG_CTIMER_STMINTCLR_CAPTUREB_CAPB_INT 0x00000400 632 633 // CAPTURE register A has grabbed the value in the counter 634 #define AM_REG_CTIMER_STMINTCLR_CAPTUREA_S 9 635 #define AM_REG_CTIMER_STMINTCLR_CAPTUREA_M 0x00000200 636 #define AM_REG_CTIMER_STMINTCLR_CAPTUREA(n) (((uint32_t)(n) << 9) & 0x00000200) 637 #define AM_REG_CTIMER_STMINTCLR_CAPTUREA_CAPA_INT 0x00000200 638 639 // COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. 640 #define AM_REG_CTIMER_STMINTCLR_OVERFLOW_S 8 641 #define AM_REG_CTIMER_STMINTCLR_OVERFLOW_M 0x00000100 642 #define AM_REG_CTIMER_STMINTCLR_OVERFLOW(n) (((uint32_t)(n) << 8) & 0x00000100) 643 #define AM_REG_CTIMER_STMINTCLR_OVERFLOW_OFLOW_INT 0x00000100 644 645 // COUNTER is greater than or equal to COMPARE register H. 646 #define AM_REG_CTIMER_STMINTCLR_COMPAREH_S 7 647 #define AM_REG_CTIMER_STMINTCLR_COMPAREH_M 0x00000080 648 #define AM_REG_CTIMER_STMINTCLR_COMPAREH(n) (((uint32_t)(n) << 7) & 0x00000080) 649 #define AM_REG_CTIMER_STMINTCLR_COMPAREH_COMPARED 0x00000080 650 651 // COUNTER is greater than or equal to COMPARE register G. 652 #define AM_REG_CTIMER_STMINTCLR_COMPAREG_S 6 653 #define AM_REG_CTIMER_STMINTCLR_COMPAREG_M 0x00000040 654 #define AM_REG_CTIMER_STMINTCLR_COMPAREG(n) (((uint32_t)(n) << 6) & 0x00000040) 655 #define AM_REG_CTIMER_STMINTCLR_COMPAREG_COMPARED 0x00000040 656 657 // COUNTER is greater than or equal to COMPARE register F. 658 #define AM_REG_CTIMER_STMINTCLR_COMPAREF_S 5 659 #define AM_REG_CTIMER_STMINTCLR_COMPAREF_M 0x00000020 660 #define AM_REG_CTIMER_STMINTCLR_COMPAREF(n) (((uint32_t)(n) << 5) & 0x00000020) 661 #define AM_REG_CTIMER_STMINTCLR_COMPAREF_COMPARED 0x00000020 662 663 // COUNTER is greater than or equal to COMPARE register E. 664 #define AM_REG_CTIMER_STMINTCLR_COMPAREE_S 4 665 #define AM_REG_CTIMER_STMINTCLR_COMPAREE_M 0x00000010 666 #define AM_REG_CTIMER_STMINTCLR_COMPAREE(n) (((uint32_t)(n) << 4) & 0x00000010) 667 #define AM_REG_CTIMER_STMINTCLR_COMPAREE_COMPARED 0x00000010 668 669 // COUNTER is greater than or equal to COMPARE register D. 670 #define AM_REG_CTIMER_STMINTCLR_COMPARED_S 3 671 #define AM_REG_CTIMER_STMINTCLR_COMPARED_M 0x00000008 672 #define AM_REG_CTIMER_STMINTCLR_COMPARED(n) (((uint32_t)(n) << 3) & 0x00000008) 673 #define AM_REG_CTIMER_STMINTCLR_COMPARED_COMPARED 0x00000008 674 675 // COUNTER is greater than or equal to COMPARE register C. 676 #define AM_REG_CTIMER_STMINTCLR_COMPAREC_S 2 677 #define AM_REG_CTIMER_STMINTCLR_COMPAREC_M 0x00000004 678 #define AM_REG_CTIMER_STMINTCLR_COMPAREC(n) (((uint32_t)(n) << 2) & 0x00000004) 679 #define AM_REG_CTIMER_STMINTCLR_COMPAREC_COMPARED 0x00000004 680 681 // COUNTER is greater than or equal to COMPARE register B. 682 #define AM_REG_CTIMER_STMINTCLR_COMPAREB_S 1 683 #define AM_REG_CTIMER_STMINTCLR_COMPAREB_M 0x00000002 684 #define AM_REG_CTIMER_STMINTCLR_COMPAREB(n) (((uint32_t)(n) << 1) & 0x00000002) 685 #define AM_REG_CTIMER_STMINTCLR_COMPAREB_COMPARED 0x00000002 686 687 // COUNTER is greater than or equal to COMPARE register A. 688 #define AM_REG_CTIMER_STMINTCLR_COMPAREA_S 0 689 #define AM_REG_CTIMER_STMINTCLR_COMPAREA_M 0x00000001 690 #define AM_REG_CTIMER_STMINTCLR_COMPAREA(n) (((uint32_t)(n) << 0) & 0x00000001) 691 #define AM_REG_CTIMER_STMINTCLR_COMPAREA_COMPARED 0x00000001 692 693 //***************************************************************************** 694 // 695 // CTIMER_STMINTSET - STIMER Interrupt registers: Set 696 // 697 //***************************************************************************** 698 // CAPTURE register D has grabbed the value in the counter 699 #define AM_REG_CTIMER_STMINTSET_CAPTURED_S 12 700 #define AM_REG_CTIMER_STMINTSET_CAPTURED_M 0x00001000 701 #define AM_REG_CTIMER_STMINTSET_CAPTURED(n) (((uint32_t)(n) << 12) & 0x00001000) 702 #define AM_REG_CTIMER_STMINTSET_CAPTURED_CAPD_INT 0x00001000 703 704 // CAPTURE register C has grabbed the value in the counter 705 #define AM_REG_CTIMER_STMINTSET_CAPTUREC_S 11 706 #define AM_REG_CTIMER_STMINTSET_CAPTUREC_M 0x00000800 707 #define AM_REG_CTIMER_STMINTSET_CAPTUREC(n) (((uint32_t)(n) << 11) & 0x00000800) 708 #define AM_REG_CTIMER_STMINTSET_CAPTUREC_CAPC_INT 0x00000800 709 710 // CAPTURE register B has grabbed the value in the counter 711 #define AM_REG_CTIMER_STMINTSET_CAPTUREB_S 10 712 #define AM_REG_CTIMER_STMINTSET_CAPTUREB_M 0x00000400 713 #define AM_REG_CTIMER_STMINTSET_CAPTUREB(n) (((uint32_t)(n) << 10) & 0x00000400) 714 #define AM_REG_CTIMER_STMINTSET_CAPTUREB_CAPB_INT 0x00000400 715 716 // CAPTURE register A has grabbed the value in the counter 717 #define AM_REG_CTIMER_STMINTSET_CAPTUREA_S 9 718 #define AM_REG_CTIMER_STMINTSET_CAPTUREA_M 0x00000200 719 #define AM_REG_CTIMER_STMINTSET_CAPTUREA(n) (((uint32_t)(n) << 9) & 0x00000200) 720 #define AM_REG_CTIMER_STMINTSET_CAPTUREA_CAPA_INT 0x00000200 721 722 // COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. 723 #define AM_REG_CTIMER_STMINTSET_OVERFLOW_S 8 724 #define AM_REG_CTIMER_STMINTSET_OVERFLOW_M 0x00000100 725 #define AM_REG_CTIMER_STMINTSET_OVERFLOW(n) (((uint32_t)(n) << 8) & 0x00000100) 726 #define AM_REG_CTIMER_STMINTSET_OVERFLOW_OFLOW_INT 0x00000100 727 728 // COUNTER is greater than or equal to COMPARE register H. 729 #define AM_REG_CTIMER_STMINTSET_COMPAREH_S 7 730 #define AM_REG_CTIMER_STMINTSET_COMPAREH_M 0x00000080 731 #define AM_REG_CTIMER_STMINTSET_COMPAREH(n) (((uint32_t)(n) << 7) & 0x00000080) 732 #define AM_REG_CTIMER_STMINTSET_COMPAREH_COMPARED 0x00000080 733 734 // COUNTER is greater than or equal to COMPARE register G. 735 #define AM_REG_CTIMER_STMINTSET_COMPAREG_S 6 736 #define AM_REG_CTIMER_STMINTSET_COMPAREG_M 0x00000040 737 #define AM_REG_CTIMER_STMINTSET_COMPAREG(n) (((uint32_t)(n) << 6) & 0x00000040) 738 #define AM_REG_CTIMER_STMINTSET_COMPAREG_COMPARED 0x00000040 739 740 // COUNTER is greater than or equal to COMPARE register F. 741 #define AM_REG_CTIMER_STMINTSET_COMPAREF_S 5 742 #define AM_REG_CTIMER_STMINTSET_COMPAREF_M 0x00000020 743 #define AM_REG_CTIMER_STMINTSET_COMPAREF(n) (((uint32_t)(n) << 5) & 0x00000020) 744 #define AM_REG_CTIMER_STMINTSET_COMPAREF_COMPARED 0x00000020 745 746 // COUNTER is greater than or equal to COMPARE register E. 747 #define AM_REG_CTIMER_STMINTSET_COMPAREE_S 4 748 #define AM_REG_CTIMER_STMINTSET_COMPAREE_M 0x00000010 749 #define AM_REG_CTIMER_STMINTSET_COMPAREE(n) (((uint32_t)(n) << 4) & 0x00000010) 750 #define AM_REG_CTIMER_STMINTSET_COMPAREE_COMPARED 0x00000010 751 752 // COUNTER is greater than or equal to COMPARE register D. 753 #define AM_REG_CTIMER_STMINTSET_COMPARED_S 3 754 #define AM_REG_CTIMER_STMINTSET_COMPARED_M 0x00000008 755 #define AM_REG_CTIMER_STMINTSET_COMPARED(n) (((uint32_t)(n) << 3) & 0x00000008) 756 #define AM_REG_CTIMER_STMINTSET_COMPARED_COMPARED 0x00000008 757 758 // COUNTER is greater than or equal to COMPARE register C. 759 #define AM_REG_CTIMER_STMINTSET_COMPAREC_S 2 760 #define AM_REG_CTIMER_STMINTSET_COMPAREC_M 0x00000004 761 #define AM_REG_CTIMER_STMINTSET_COMPAREC(n) (((uint32_t)(n) << 2) & 0x00000004) 762 #define AM_REG_CTIMER_STMINTSET_COMPAREC_COMPARED 0x00000004 763 764 // COUNTER is greater than or equal to COMPARE register B. 765 #define AM_REG_CTIMER_STMINTSET_COMPAREB_S 1 766 #define AM_REG_CTIMER_STMINTSET_COMPAREB_M 0x00000002 767 #define AM_REG_CTIMER_STMINTSET_COMPAREB(n) (((uint32_t)(n) << 1) & 0x00000002) 768 #define AM_REG_CTIMER_STMINTSET_COMPAREB_COMPARED 0x00000002 769 770 // COUNTER is greater than or equal to COMPARE register A. 771 #define AM_REG_CTIMER_STMINTSET_COMPAREA_S 0 772 #define AM_REG_CTIMER_STMINTSET_COMPAREA_M 0x00000001 773 #define AM_REG_CTIMER_STMINTSET_COMPAREA(n) (((uint32_t)(n) << 0) & 0x00000001) 774 #define AM_REG_CTIMER_STMINTSET_COMPAREA_COMPARED 0x00000001 775 776 //***************************************************************************** 777 // 778 // CTIMER_TMR0 - Counter/Timer Register 779 // 780 //***************************************************************************** 781 // Counter/Timer B0. 782 #define AM_REG_CTIMER_TMR0_CTTMRB0_S 16 783 #define AM_REG_CTIMER_TMR0_CTTMRB0_M 0xFFFF0000 784 #define AM_REG_CTIMER_TMR0_CTTMRB0(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 785 786 // Counter/Timer A0. 787 #define AM_REG_CTIMER_TMR0_CTTMRA0_S 0 788 #define AM_REG_CTIMER_TMR0_CTTMRA0_M 0x0000FFFF 789 #define AM_REG_CTIMER_TMR0_CTTMRA0(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 790 791 //***************************************************************************** 792 // 793 // CTIMER_CMPRA0 - Counter/Timer A0 Compare Registers 794 // 795 //***************************************************************************** 796 // Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A. 797 #define AM_REG_CTIMER_CMPRA0_CMPR1A0_S 16 798 #define AM_REG_CTIMER_CMPRA0_CMPR1A0_M 0xFFFF0000 799 #define AM_REG_CTIMER_CMPRA0_CMPR1A0(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 800 801 // Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A. 802 #define AM_REG_CTIMER_CMPRA0_CMPR0A0_S 0 803 #define AM_REG_CTIMER_CMPRA0_CMPR0A0_M 0x0000FFFF 804 #define AM_REG_CTIMER_CMPRA0_CMPR0A0(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 805 806 //***************************************************************************** 807 // 808 // CTIMER_CMPRB0 - Counter/Timer B0 Compare Registers 809 // 810 //***************************************************************************** 811 // Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B. 812 #define AM_REG_CTIMER_CMPRB0_CMPR1B0_S 16 813 #define AM_REG_CTIMER_CMPRB0_CMPR1B0_M 0xFFFF0000 814 #define AM_REG_CTIMER_CMPRB0_CMPR1B0(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 815 816 // Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B. 817 #define AM_REG_CTIMER_CMPRB0_CMPR0B0_S 0 818 #define AM_REG_CTIMER_CMPRB0_CMPR0B0_M 0x0000FFFF 819 #define AM_REG_CTIMER_CMPRB0_CMPR0B0(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 820 821 //***************************************************************************** 822 // 823 // CTIMER_CTRL0 - Counter/Timer Control 824 // 825 //***************************************************************************** 826 // Counter/Timer A0/B0 Link bit. 827 #define AM_REG_CTIMER_CTRL0_CTLINK0_S 31 828 #define AM_REG_CTIMER_CTRL0_CTLINK0_M 0x80000000 829 #define AM_REG_CTIMER_CTRL0_CTLINK0(n) (((uint32_t)(n) << 31) & 0x80000000) 830 #define AM_REG_CTIMER_CTRL0_CTLINK0_TWO_16BIT_TIMERS 0x00000000 831 #define AM_REG_CTIMER_CTRL0_CTLINK0_32BIT_TIMER 0x80000000 832 833 // Counter/Timer B0 Output Enable bit. 834 #define AM_REG_CTIMER_CTRL0_TMRB0PE_S 29 835 #define AM_REG_CTIMER_CTRL0_TMRB0PE_M 0x20000000 836 #define AM_REG_CTIMER_CTRL0_TMRB0PE(n) (((uint32_t)(n) << 29) & 0x20000000) 837 #define AM_REG_CTIMER_CTRL0_TMRB0PE_DIS 0x00000000 838 #define AM_REG_CTIMER_CTRL0_TMRB0PE_EN 0x20000000 839 840 // Counter/Timer B0 output polarity. 841 #define AM_REG_CTIMER_CTRL0_TMRB0POL_S 28 842 #define AM_REG_CTIMER_CTRL0_TMRB0POL_M 0x10000000 843 #define AM_REG_CTIMER_CTRL0_TMRB0POL(n) (((uint32_t)(n) << 28) & 0x10000000) 844 #define AM_REG_CTIMER_CTRL0_TMRB0POL_NORMAL 0x00000000 845 #define AM_REG_CTIMER_CTRL0_TMRB0POL_INVERTED 0x10000000 846 847 // Counter/Timer B0 Clear bit. 848 #define AM_REG_CTIMER_CTRL0_TMRB0CLR_S 27 849 #define AM_REG_CTIMER_CTRL0_TMRB0CLR_M 0x08000000 850 #define AM_REG_CTIMER_CTRL0_TMRB0CLR(n) (((uint32_t)(n) << 27) & 0x08000000) 851 #define AM_REG_CTIMER_CTRL0_TMRB0CLR_RUN 0x00000000 852 #define AM_REG_CTIMER_CTRL0_TMRB0CLR_CLEAR 0x08000000 853 854 // Counter/Timer B0 Interrupt Enable bit for COMPR1. 855 #define AM_REG_CTIMER_CTRL0_TMRB0IE1_S 26 856 #define AM_REG_CTIMER_CTRL0_TMRB0IE1_M 0x04000000 857 #define AM_REG_CTIMER_CTRL0_TMRB0IE1(n) (((uint32_t)(n) << 26) & 0x04000000) 858 #define AM_REG_CTIMER_CTRL0_TMRB0IE1_DIS 0x00000000 859 #define AM_REG_CTIMER_CTRL0_TMRB0IE1_EN 0x04000000 860 861 // Counter/Timer B0 Interrupt Enable bit for COMPR0. 862 #define AM_REG_CTIMER_CTRL0_TMRB0IE0_S 25 863 #define AM_REG_CTIMER_CTRL0_TMRB0IE0_M 0x02000000 864 #define AM_REG_CTIMER_CTRL0_TMRB0IE0(n) (((uint32_t)(n) << 25) & 0x02000000) 865 #define AM_REG_CTIMER_CTRL0_TMRB0IE0_DIS 0x00000000 866 #define AM_REG_CTIMER_CTRL0_TMRB0IE0_EN 0x02000000 867 868 // Counter/Timer B0 Function Select. 869 #define AM_REG_CTIMER_CTRL0_TMRB0FN_S 22 870 #define AM_REG_CTIMER_CTRL0_TMRB0FN_M 0x01C00000 871 #define AM_REG_CTIMER_CTRL0_TMRB0FN(n) (((uint32_t)(n) << 22) & 0x01C00000) 872 #define AM_REG_CTIMER_CTRL0_TMRB0FN_SINGLECOUNT 0x00000000 873 #define AM_REG_CTIMER_CTRL0_TMRB0FN_REPEATEDCOUNT 0x00400000 874 #define AM_REG_CTIMER_CTRL0_TMRB0FN_PULSE_ONCE 0x00800000 875 #define AM_REG_CTIMER_CTRL0_TMRB0FN_PULSE_CONT 0x00C00000 876 #define AM_REG_CTIMER_CTRL0_TMRB0FN_CONTINUOUS 0x01000000 877 878 // Counter/Timer B0 Clock Select. 879 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_S 17 880 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_M 0x003E0000 881 #define AM_REG_CTIMER_CTRL0_TMRB0CLK(n) (((uint32_t)(n) << 17) & 0x003E0000) 882 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_TMRPIN 0x00000000 883 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4 0x00020000 884 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV16 0x00040000 885 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV256 0x00060000 886 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV1024 0x00080000 887 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4K 0x000A0000 888 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_XT 0x000C0000 889 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_XT_DIV2 0x000E0000 890 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_XT_DIV16 0x00100000 891 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_XT_DIV256 0x00120000 892 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_LFRC_DIV2 0x00140000 893 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_LFRC_DIV32 0x00160000 894 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_LFRC_DIV1K 0x00180000 895 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_LFRC 0x001A0000 896 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_RTC_100HZ 0x001C0000 897 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_HCLK 0x001E0000 898 #define AM_REG_CTIMER_CTRL0_TMRB0CLK_BUCKB 0x00200000 899 900 // Counter/Timer B0 Enable bit. 901 #define AM_REG_CTIMER_CTRL0_TMRB0EN_S 16 902 #define AM_REG_CTIMER_CTRL0_TMRB0EN_M 0x00010000 903 #define AM_REG_CTIMER_CTRL0_TMRB0EN(n) (((uint32_t)(n) << 16) & 0x00010000) 904 #define AM_REG_CTIMER_CTRL0_TMRB0EN_DIS 0x00000000 905 #define AM_REG_CTIMER_CTRL0_TMRB0EN_EN 0x00010000 906 907 // Counter/Timer A0 Output Enable bit. 908 #define AM_REG_CTIMER_CTRL0_TMRA0PE_S 13 909 #define AM_REG_CTIMER_CTRL0_TMRA0PE_M 0x00002000 910 #define AM_REG_CTIMER_CTRL0_TMRA0PE(n) (((uint32_t)(n) << 13) & 0x00002000) 911 #define AM_REG_CTIMER_CTRL0_TMRA0PE_DIS 0x00000000 912 #define AM_REG_CTIMER_CTRL0_TMRA0PE_EN 0x00002000 913 914 // Counter/Timer A0 output polarity. 915 #define AM_REG_CTIMER_CTRL0_TMRA0POL_S 12 916 #define AM_REG_CTIMER_CTRL0_TMRA0POL_M 0x00001000 917 #define AM_REG_CTIMER_CTRL0_TMRA0POL(n) (((uint32_t)(n) << 12) & 0x00001000) 918 #define AM_REG_CTIMER_CTRL0_TMRA0POL_NORMAL 0x00000000 919 #define AM_REG_CTIMER_CTRL0_TMRA0POL_INVERTED 0x00001000 920 921 // Counter/Timer A0 Clear bit. 922 #define AM_REG_CTIMER_CTRL0_TMRA0CLR_S 11 923 #define AM_REG_CTIMER_CTRL0_TMRA0CLR_M 0x00000800 924 #define AM_REG_CTIMER_CTRL0_TMRA0CLR(n) (((uint32_t)(n) << 11) & 0x00000800) 925 #define AM_REG_CTIMER_CTRL0_TMRA0CLR_RUN 0x00000000 926 #define AM_REG_CTIMER_CTRL0_TMRA0CLR_CLEAR 0x00000800 927 928 // Counter/Timer A0 Interrupt Enable bit based on COMPR1. 929 #define AM_REG_CTIMER_CTRL0_TMRA0IE1_S 10 930 #define AM_REG_CTIMER_CTRL0_TMRA0IE1_M 0x00000400 931 #define AM_REG_CTIMER_CTRL0_TMRA0IE1(n) (((uint32_t)(n) << 10) & 0x00000400) 932 #define AM_REG_CTIMER_CTRL0_TMRA0IE1_DIS 0x00000000 933 #define AM_REG_CTIMER_CTRL0_TMRA0IE1_EN 0x00000400 934 935 // Counter/Timer A0 Interrupt Enable bit based on COMPR0. 936 #define AM_REG_CTIMER_CTRL0_TMRA0IE0_S 9 937 #define AM_REG_CTIMER_CTRL0_TMRA0IE0_M 0x00000200 938 #define AM_REG_CTIMER_CTRL0_TMRA0IE0(n) (((uint32_t)(n) << 9) & 0x00000200) 939 #define AM_REG_CTIMER_CTRL0_TMRA0IE0_DIS 0x00000000 940 #define AM_REG_CTIMER_CTRL0_TMRA0IE0_EN 0x00000200 941 942 // Counter/Timer A0 Function Select. 943 #define AM_REG_CTIMER_CTRL0_TMRA0FN_S 6 944 #define AM_REG_CTIMER_CTRL0_TMRA0FN_M 0x000001C0 945 #define AM_REG_CTIMER_CTRL0_TMRA0FN(n) (((uint32_t)(n) << 6) & 0x000001C0) 946 #define AM_REG_CTIMER_CTRL0_TMRA0FN_SINGLECOUNT 0x00000000 947 #define AM_REG_CTIMER_CTRL0_TMRA0FN_REPEATEDCOUNT 0x00000040 948 #define AM_REG_CTIMER_CTRL0_TMRA0FN_PULSE_ONCE 0x00000080 949 #define AM_REG_CTIMER_CTRL0_TMRA0FN_PULSE_CONT 0x000000C0 950 #define AM_REG_CTIMER_CTRL0_TMRA0FN_CONTINUOUS 0x00000100 951 952 // Counter/Timer A0 Clock Select. 953 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_S 1 954 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_M 0x0000003E 955 #define AM_REG_CTIMER_CTRL0_TMRA0CLK(n) (((uint32_t)(n) << 1) & 0x0000003E) 956 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_TMRPIN 0x00000000 957 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4 0x00000002 958 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV16 0x00000004 959 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV256 0x00000006 960 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV1024 0x00000008 961 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4K 0x0000000A 962 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_XT 0x0000000C 963 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_XT_DIV2 0x0000000E 964 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_XT_DIV16 0x00000010 965 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_XT_DIV256 0x00000012 966 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2 0x00000014 967 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32 0x00000016 968 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K 0x00000018 969 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_LFRC 0x0000001A 970 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_RTC_100HZ 0x0000001C 971 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_HCLK_DIV4 0x0000001E 972 #define AM_REG_CTIMER_CTRL0_TMRA0CLK_BUCKA 0x00000020 973 974 // Counter/Timer A0 Enable bit. 975 #define AM_REG_CTIMER_CTRL0_TMRA0EN_S 0 976 #define AM_REG_CTIMER_CTRL0_TMRA0EN_M 0x00000001 977 #define AM_REG_CTIMER_CTRL0_TMRA0EN(n) (((uint32_t)(n) << 0) & 0x00000001) 978 #define AM_REG_CTIMER_CTRL0_TMRA0EN_DIS 0x00000000 979 #define AM_REG_CTIMER_CTRL0_TMRA0EN_EN 0x00000001 980 981 //***************************************************************************** 982 // 983 // CTIMER_TMR1 - Counter/Timer Register 984 // 985 //***************************************************************************** 986 // Counter/Timer B1. 987 #define AM_REG_CTIMER_TMR1_CTTMRB1_S 16 988 #define AM_REG_CTIMER_TMR1_CTTMRB1_M 0xFFFF0000 989 #define AM_REG_CTIMER_TMR1_CTTMRB1(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 990 991 // Counter/Timer A1. 992 #define AM_REG_CTIMER_TMR1_CTTMRA1_S 0 993 #define AM_REG_CTIMER_TMR1_CTTMRA1_M 0x0000FFFF 994 #define AM_REG_CTIMER_TMR1_CTTMRA1(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 995 996 //***************************************************************************** 997 // 998 // CTIMER_CMPRA1 - Counter/Timer A1 Compare Registers 999 // 1000 //***************************************************************************** 1001 // Counter/Timer A1 Compare Register 1. 1002 #define AM_REG_CTIMER_CMPRA1_CMPR1A1_S 16 1003 #define AM_REG_CTIMER_CMPRA1_CMPR1A1_M 0xFFFF0000 1004 #define AM_REG_CTIMER_CMPRA1_CMPR1A1(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 1005 1006 // Counter/Timer A1 Compare Register 0. 1007 #define AM_REG_CTIMER_CMPRA1_CMPR0A1_S 0 1008 #define AM_REG_CTIMER_CMPRA1_CMPR0A1_M 0x0000FFFF 1009 #define AM_REG_CTIMER_CMPRA1_CMPR0A1(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 1010 1011 //***************************************************************************** 1012 // 1013 // CTIMER_CMPRB1 - Counter/Timer B1 Compare Registers 1014 // 1015 //***************************************************************************** 1016 // Counter/Timer B1 Compare Register 1. 1017 #define AM_REG_CTIMER_CMPRB1_CMPR1B1_S 16 1018 #define AM_REG_CTIMER_CMPRB1_CMPR1B1_M 0xFFFF0000 1019 #define AM_REG_CTIMER_CMPRB1_CMPR1B1(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 1020 1021 // Counter/Timer B1 Compare Register 0. 1022 #define AM_REG_CTIMER_CMPRB1_CMPR0B1_S 0 1023 #define AM_REG_CTIMER_CMPRB1_CMPR0B1_M 0x0000FFFF 1024 #define AM_REG_CTIMER_CMPRB1_CMPR0B1(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 1025 1026 //***************************************************************************** 1027 // 1028 // CTIMER_CTRL1 - Counter/Timer Control 1029 // 1030 //***************************************************************************** 1031 // Counter/Timer A1/B1 Link bit. 1032 #define AM_REG_CTIMER_CTRL1_CTLINK1_S 31 1033 #define AM_REG_CTIMER_CTRL1_CTLINK1_M 0x80000000 1034 #define AM_REG_CTIMER_CTRL1_CTLINK1(n) (((uint32_t)(n) << 31) & 0x80000000) 1035 #define AM_REG_CTIMER_CTRL1_CTLINK1_TWO_16BIT_TIMERS 0x00000000 1036 #define AM_REG_CTIMER_CTRL1_CTLINK1_32BIT_TIMER 0x80000000 1037 1038 // Counter/Timer B1 Output Enable bit. 1039 #define AM_REG_CTIMER_CTRL1_TMRB1PE_S 29 1040 #define AM_REG_CTIMER_CTRL1_TMRB1PE_M 0x20000000 1041 #define AM_REG_CTIMER_CTRL1_TMRB1PE(n) (((uint32_t)(n) << 29) & 0x20000000) 1042 #define AM_REG_CTIMER_CTRL1_TMRB1PE_DIS 0x00000000 1043 #define AM_REG_CTIMER_CTRL1_TMRB1PE_EN 0x20000000 1044 1045 // Counter/Timer B1 output polarity. 1046 #define AM_REG_CTIMER_CTRL1_TMRB1POL_S 28 1047 #define AM_REG_CTIMER_CTRL1_TMRB1POL_M 0x10000000 1048 #define AM_REG_CTIMER_CTRL1_TMRB1POL(n) (((uint32_t)(n) << 28) & 0x10000000) 1049 #define AM_REG_CTIMER_CTRL1_TMRB1POL_NORMAL 0x00000000 1050 #define AM_REG_CTIMER_CTRL1_TMRB1POL_INVERTED 0x10000000 1051 1052 // Counter/Timer B1 Clear bit. 1053 #define AM_REG_CTIMER_CTRL1_TMRB1CLR_S 27 1054 #define AM_REG_CTIMER_CTRL1_TMRB1CLR_M 0x08000000 1055 #define AM_REG_CTIMER_CTRL1_TMRB1CLR(n) (((uint32_t)(n) << 27) & 0x08000000) 1056 #define AM_REG_CTIMER_CTRL1_TMRB1CLR_RUN 0x00000000 1057 #define AM_REG_CTIMER_CTRL1_TMRB1CLR_CLEAR 0x08000000 1058 1059 // Counter/Timer B1 Interrupt Enable bit for COMPR1. 1060 #define AM_REG_CTIMER_CTRL1_TMRB1IE1_S 26 1061 #define AM_REG_CTIMER_CTRL1_TMRB1IE1_M 0x04000000 1062 #define AM_REG_CTIMER_CTRL1_TMRB1IE1(n) (((uint32_t)(n) << 26) & 0x04000000) 1063 #define AM_REG_CTIMER_CTRL1_TMRB1IE1_DIS 0x00000000 1064 #define AM_REG_CTIMER_CTRL1_TMRB1IE1_EN 0x04000000 1065 1066 // Counter/Timer B1 Interrupt Enable bit for COMPR0. 1067 #define AM_REG_CTIMER_CTRL1_TMRB1IE0_S 25 1068 #define AM_REG_CTIMER_CTRL1_TMRB1IE0_M 0x02000000 1069 #define AM_REG_CTIMER_CTRL1_TMRB1IE0(n) (((uint32_t)(n) << 25) & 0x02000000) 1070 #define AM_REG_CTIMER_CTRL1_TMRB1IE0_DIS 0x00000000 1071 #define AM_REG_CTIMER_CTRL1_TMRB1IE0_EN 0x02000000 1072 1073 // Counter/Timer B1 Function Select. 1074 #define AM_REG_CTIMER_CTRL1_TMRB1FN_S 22 1075 #define AM_REG_CTIMER_CTRL1_TMRB1FN_M 0x01C00000 1076 #define AM_REG_CTIMER_CTRL1_TMRB1FN(n) (((uint32_t)(n) << 22) & 0x01C00000) 1077 #define AM_REG_CTIMER_CTRL1_TMRB1FN_SINGLECOUNT 0x00000000 1078 #define AM_REG_CTIMER_CTRL1_TMRB1FN_REPEATEDCOUNT 0x00400000 1079 #define AM_REG_CTIMER_CTRL1_TMRB1FN_PULSE_ONCE 0x00800000 1080 #define AM_REG_CTIMER_CTRL1_TMRB1FN_PULSE_CONT 0x00C00000 1081 #define AM_REG_CTIMER_CTRL1_TMRB1FN_CONTINUOUS 0x01000000 1082 1083 // Counter/Timer B1 Clock Select. 1084 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_S 17 1085 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_M 0x003E0000 1086 #define AM_REG_CTIMER_CTRL1_TMRB1CLK(n) (((uint32_t)(n) << 17) & 0x003E0000) 1087 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_TMRPIN 0x00000000 1088 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4 0x00020000 1089 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV16 0x00040000 1090 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV256 0x00060000 1091 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV1024 0x00080000 1092 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4K 0x000A0000 1093 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_XT 0x000C0000 1094 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_XT_DIV2 0x000E0000 1095 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_XT_DIV16 0x00100000 1096 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_XT_DIV256 0x00120000 1097 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_LFRC_DIV2 0x00140000 1098 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_LFRC_DIV32 0x00160000 1099 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_LFRC_DIV1K 0x00180000 1100 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_LFRC 0x001A0000 1101 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_RTC_100HZ 0x001C0000 1102 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_HCLK 0x001E0000 1103 #define AM_REG_CTIMER_CTRL1_TMRB1CLK_BUCKB 0x00200000 1104 1105 // Counter/Timer B1 Enable bit. 1106 #define AM_REG_CTIMER_CTRL1_TMRB1EN_S 16 1107 #define AM_REG_CTIMER_CTRL1_TMRB1EN_M 0x00010000 1108 #define AM_REG_CTIMER_CTRL1_TMRB1EN(n) (((uint32_t)(n) << 16) & 0x00010000) 1109 #define AM_REG_CTIMER_CTRL1_TMRB1EN_DIS 0x00000000 1110 #define AM_REG_CTIMER_CTRL1_TMRB1EN_EN 0x00010000 1111 1112 // Counter/Timer A1 Output Enable bit. 1113 #define AM_REG_CTIMER_CTRL1_TMRA1PE_S 13 1114 #define AM_REG_CTIMER_CTRL1_TMRA1PE_M 0x00002000 1115 #define AM_REG_CTIMER_CTRL1_TMRA1PE(n) (((uint32_t)(n) << 13) & 0x00002000) 1116 #define AM_REG_CTIMER_CTRL1_TMRA1PE_DIS 0x00000000 1117 #define AM_REG_CTIMER_CTRL1_TMRA1PE_EN 0x00002000 1118 1119 // Counter/Timer A1 output polarity. 1120 #define AM_REG_CTIMER_CTRL1_TMRA1POL_S 12 1121 #define AM_REG_CTIMER_CTRL1_TMRA1POL_M 0x00001000 1122 #define AM_REG_CTIMER_CTRL1_TMRA1POL(n) (((uint32_t)(n) << 12) & 0x00001000) 1123 #define AM_REG_CTIMER_CTRL1_TMRA1POL_NORMAL 0x00000000 1124 #define AM_REG_CTIMER_CTRL1_TMRA1POL_INVERTED 0x00001000 1125 1126 // Counter/Timer A1 Clear bit. 1127 #define AM_REG_CTIMER_CTRL1_TMRA1CLR_S 11 1128 #define AM_REG_CTIMER_CTRL1_TMRA1CLR_M 0x00000800 1129 #define AM_REG_CTIMER_CTRL1_TMRA1CLR(n) (((uint32_t)(n) << 11) & 0x00000800) 1130 #define AM_REG_CTIMER_CTRL1_TMRA1CLR_RUN 0x00000000 1131 #define AM_REG_CTIMER_CTRL1_TMRA1CLR_CLEAR 0x00000800 1132 1133 // Counter/Timer A1 Interrupt Enable bit based on COMPR1. 1134 #define AM_REG_CTIMER_CTRL1_TMRA1IE1_S 10 1135 #define AM_REG_CTIMER_CTRL1_TMRA1IE1_M 0x00000400 1136 #define AM_REG_CTIMER_CTRL1_TMRA1IE1(n) (((uint32_t)(n) << 10) & 0x00000400) 1137 #define AM_REG_CTIMER_CTRL1_TMRA1IE1_DIS 0x00000000 1138 #define AM_REG_CTIMER_CTRL1_TMRA1IE1_EN 0x00000400 1139 1140 // Counter/Timer A1 Interrupt Enable bit based on COMPR0. 1141 #define AM_REG_CTIMER_CTRL1_TMRA1IE0_S 9 1142 #define AM_REG_CTIMER_CTRL1_TMRA1IE0_M 0x00000200 1143 #define AM_REG_CTIMER_CTRL1_TMRA1IE0(n) (((uint32_t)(n) << 9) & 0x00000200) 1144 #define AM_REG_CTIMER_CTRL1_TMRA1IE0_DIS 0x00000000 1145 #define AM_REG_CTIMER_CTRL1_TMRA1IE0_EN 0x00000200 1146 1147 // Counter/Timer A1 Function Select. 1148 #define AM_REG_CTIMER_CTRL1_TMRA1FN_S 6 1149 #define AM_REG_CTIMER_CTRL1_TMRA1FN_M 0x000001C0 1150 #define AM_REG_CTIMER_CTRL1_TMRA1FN(n) (((uint32_t)(n) << 6) & 0x000001C0) 1151 #define AM_REG_CTIMER_CTRL1_TMRA1FN_SINGLECOUNT 0x00000000 1152 #define AM_REG_CTIMER_CTRL1_TMRA1FN_REPEATEDCOUNT 0x00000040 1153 #define AM_REG_CTIMER_CTRL1_TMRA1FN_PULSE_ONCE 0x00000080 1154 #define AM_REG_CTIMER_CTRL1_TMRA1FN_PULSE_CONT 0x000000C0 1155 #define AM_REG_CTIMER_CTRL1_TMRA1FN_CONTINUOUS 0x00000100 1156 1157 // Counter/Timer A1 Clock Select. 1158 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_S 1 1159 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_M 0x0000003E 1160 #define AM_REG_CTIMER_CTRL1_TMRA1CLK(n) (((uint32_t)(n) << 1) & 0x0000003E) 1161 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_TMRPIN 0x00000000 1162 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4 0x00000002 1163 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV16 0x00000004 1164 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV256 0x00000006 1165 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV1024 0x00000008 1166 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4K 0x0000000A 1167 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_XT 0x0000000C 1168 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_XT_DIV2 0x0000000E 1169 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_XT_DIV16 0x00000010 1170 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_XT_DIV256 0x00000012 1171 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_LFRC_DIV2 0x00000014 1172 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_LFRC_DIV32 0x00000016 1173 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_LFRC_DIV1K 0x00000018 1174 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_LFRC 0x0000001A 1175 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_RTC_100HZ 0x0000001C 1176 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_HCLK 0x0000001E 1177 #define AM_REG_CTIMER_CTRL1_TMRA1CLK_BUCKA 0x00000020 1178 1179 // Counter/Timer A1 Enable bit. 1180 #define AM_REG_CTIMER_CTRL1_TMRA1EN_S 0 1181 #define AM_REG_CTIMER_CTRL1_TMRA1EN_M 0x00000001 1182 #define AM_REG_CTIMER_CTRL1_TMRA1EN(n) (((uint32_t)(n) << 0) & 0x00000001) 1183 #define AM_REG_CTIMER_CTRL1_TMRA1EN_DIS 0x00000000 1184 #define AM_REG_CTIMER_CTRL1_TMRA1EN_EN 0x00000001 1185 1186 //***************************************************************************** 1187 // 1188 // CTIMER_TMR2 - Counter/Timer Register 1189 // 1190 //***************************************************************************** 1191 // Counter/Timer B2. 1192 #define AM_REG_CTIMER_TMR2_CTTMRB2_S 16 1193 #define AM_REG_CTIMER_TMR2_CTTMRB2_M 0xFFFF0000 1194 #define AM_REG_CTIMER_TMR2_CTTMRB2(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 1195 1196 // Counter/Timer A2. 1197 #define AM_REG_CTIMER_TMR2_CTTMRA2_S 0 1198 #define AM_REG_CTIMER_TMR2_CTTMRA2_M 0x0000FFFF 1199 #define AM_REG_CTIMER_TMR2_CTTMRA2(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 1200 1201 //***************************************************************************** 1202 // 1203 // CTIMER_CMPRA2 - Counter/Timer A2 Compare Registers 1204 // 1205 //***************************************************************************** 1206 // Counter/Timer A2 Compare Register 1. 1207 #define AM_REG_CTIMER_CMPRA2_CMPR1A2_S 16 1208 #define AM_REG_CTIMER_CMPRA2_CMPR1A2_M 0xFFFF0000 1209 #define AM_REG_CTIMER_CMPRA2_CMPR1A2(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 1210 1211 // Counter/Timer A2 Compare Register 0. 1212 #define AM_REG_CTIMER_CMPRA2_CMPR0A2_S 0 1213 #define AM_REG_CTIMER_CMPRA2_CMPR0A2_M 0x0000FFFF 1214 #define AM_REG_CTIMER_CMPRA2_CMPR0A2(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 1215 1216 //***************************************************************************** 1217 // 1218 // CTIMER_CMPRB2 - Counter/Timer B2 Compare Registers 1219 // 1220 //***************************************************************************** 1221 // Counter/Timer B2 Compare Register 1. 1222 #define AM_REG_CTIMER_CMPRB2_CMPR1B2_S 16 1223 #define AM_REG_CTIMER_CMPRB2_CMPR1B2_M 0xFFFF0000 1224 #define AM_REG_CTIMER_CMPRB2_CMPR1B2(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 1225 1226 // Counter/Timer B2 Compare Register 0. 1227 #define AM_REG_CTIMER_CMPRB2_CMPR0B2_S 0 1228 #define AM_REG_CTIMER_CMPRB2_CMPR0B2_M 0x0000FFFF 1229 #define AM_REG_CTIMER_CMPRB2_CMPR0B2(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 1230 1231 //***************************************************************************** 1232 // 1233 // CTIMER_CTRL2 - Counter/Timer Control 1234 // 1235 //***************************************************************************** 1236 // Counter/Timer A2/B2 Link bit. 1237 #define AM_REG_CTIMER_CTRL2_CTLINK2_S 31 1238 #define AM_REG_CTIMER_CTRL2_CTLINK2_M 0x80000000 1239 #define AM_REG_CTIMER_CTRL2_CTLINK2(n) (((uint32_t)(n) << 31) & 0x80000000) 1240 #define AM_REG_CTIMER_CTRL2_CTLINK2_TWO_16BIT_TIMERS 0x00000000 1241 #define AM_REG_CTIMER_CTRL2_CTLINK2_32BIT_TIMER 0x80000000 1242 1243 // Counter/Timer B2 Output Enable bit. 1244 #define AM_REG_CTIMER_CTRL2_TMRB2PE_S 29 1245 #define AM_REG_CTIMER_CTRL2_TMRB2PE_M 0x20000000 1246 #define AM_REG_CTIMER_CTRL2_TMRB2PE(n) (((uint32_t)(n) << 29) & 0x20000000) 1247 #define AM_REG_CTIMER_CTRL2_TMRB2PE_DIS 0x00000000 1248 #define AM_REG_CTIMER_CTRL2_TMRB2PE_EN 0x20000000 1249 1250 // Counter/Timer B2 output polarity. 1251 #define AM_REG_CTIMER_CTRL2_TMRB2POL_S 28 1252 #define AM_REG_CTIMER_CTRL2_TMRB2POL_M 0x10000000 1253 #define AM_REG_CTIMER_CTRL2_TMRB2POL(n) (((uint32_t)(n) << 28) & 0x10000000) 1254 #define AM_REG_CTIMER_CTRL2_TMRB2POL_NORMAL 0x00000000 1255 #define AM_REG_CTIMER_CTRL2_TMRB2POL_INVERTED 0x10000000 1256 1257 // Counter/Timer B2 Clear bit. 1258 #define AM_REG_CTIMER_CTRL2_TMRB2CLR_S 27 1259 #define AM_REG_CTIMER_CTRL2_TMRB2CLR_M 0x08000000 1260 #define AM_REG_CTIMER_CTRL2_TMRB2CLR(n) (((uint32_t)(n) << 27) & 0x08000000) 1261 #define AM_REG_CTIMER_CTRL2_TMRB2CLR_RUN 0x00000000 1262 #define AM_REG_CTIMER_CTRL2_TMRB2CLR_CLEAR 0x08000000 1263 1264 // Counter/Timer B2 Interrupt Enable bit for COMPR1. 1265 #define AM_REG_CTIMER_CTRL2_TMRB2IE1_S 26 1266 #define AM_REG_CTIMER_CTRL2_TMRB2IE1_M 0x04000000 1267 #define AM_REG_CTIMER_CTRL2_TMRB2IE1(n) (((uint32_t)(n) << 26) & 0x04000000) 1268 #define AM_REG_CTIMER_CTRL2_TMRB2IE1_DIS 0x00000000 1269 #define AM_REG_CTIMER_CTRL2_TMRB2IE1_EN 0x04000000 1270 1271 // Counter/Timer B2 Interrupt Enable bit for COMPR0. 1272 #define AM_REG_CTIMER_CTRL2_TMRB2IE0_S 25 1273 #define AM_REG_CTIMER_CTRL2_TMRB2IE0_M 0x02000000 1274 #define AM_REG_CTIMER_CTRL2_TMRB2IE0(n) (((uint32_t)(n) << 25) & 0x02000000) 1275 #define AM_REG_CTIMER_CTRL2_TMRB2IE0_DIS 0x00000000 1276 #define AM_REG_CTIMER_CTRL2_TMRB2IE0_EN 0x02000000 1277 1278 // Counter/Timer B2 Function Select. 1279 #define AM_REG_CTIMER_CTRL2_TMRB2FN_S 22 1280 #define AM_REG_CTIMER_CTRL2_TMRB2FN_M 0x01C00000 1281 #define AM_REG_CTIMER_CTRL2_TMRB2FN(n) (((uint32_t)(n) << 22) & 0x01C00000) 1282 #define AM_REG_CTIMER_CTRL2_TMRB2FN_SINGLECOUNT 0x00000000 1283 #define AM_REG_CTIMER_CTRL2_TMRB2FN_REPEATEDCOUNT 0x00400000 1284 #define AM_REG_CTIMER_CTRL2_TMRB2FN_PULSE_ONCE 0x00800000 1285 #define AM_REG_CTIMER_CTRL2_TMRB2FN_PULSE_CONT 0x00C00000 1286 #define AM_REG_CTIMER_CTRL2_TMRB2FN_CONTINUOUS 0x01000000 1287 1288 // Counter/Timer B2 Clock Select. 1289 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_S 17 1290 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_M 0x003E0000 1291 #define AM_REG_CTIMER_CTRL2_TMRB2CLK(n) (((uint32_t)(n) << 17) & 0x003E0000) 1292 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_TMRPIN 0x00000000 1293 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4 0x00020000 1294 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV16 0x00040000 1295 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV256 0x00060000 1296 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV1024 0x00080000 1297 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4K 0x000A0000 1298 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_XT 0x000C0000 1299 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_XT_DIV2 0x000E0000 1300 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_XT_DIV16 0x00100000 1301 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_XT_DIV256 0x00120000 1302 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_LFRC_DIV2 0x00140000 1303 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_LFRC_DIV32 0x00160000 1304 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_LFRC_DIV1K 0x00180000 1305 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_LFRC 0x001A0000 1306 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_RTC_100HZ 0x001C0000 1307 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_HCLK 0x001E0000 1308 #define AM_REG_CTIMER_CTRL2_TMRB2CLK_BUCKA 0x00200000 1309 1310 // Counter/Timer B2 Enable bit. 1311 #define AM_REG_CTIMER_CTRL2_TMRB2EN_S 16 1312 #define AM_REG_CTIMER_CTRL2_TMRB2EN_M 0x00010000 1313 #define AM_REG_CTIMER_CTRL2_TMRB2EN(n) (((uint32_t)(n) << 16) & 0x00010000) 1314 #define AM_REG_CTIMER_CTRL2_TMRB2EN_DIS 0x00000000 1315 #define AM_REG_CTIMER_CTRL2_TMRB2EN_EN 0x00010000 1316 1317 // Counter/Timer A2 Output Enable bit. 1318 #define AM_REG_CTIMER_CTRL2_TMRA2PE_S 13 1319 #define AM_REG_CTIMER_CTRL2_TMRA2PE_M 0x00002000 1320 #define AM_REG_CTIMER_CTRL2_TMRA2PE(n) (((uint32_t)(n) << 13) & 0x00002000) 1321 #define AM_REG_CTIMER_CTRL2_TMRA2PE_DIS 0x00000000 1322 #define AM_REG_CTIMER_CTRL2_TMRA2PE_EN 0x00002000 1323 1324 // Counter/Timer A2 output polarity. 1325 #define AM_REG_CTIMER_CTRL2_TMRA2POL_S 12 1326 #define AM_REG_CTIMER_CTRL2_TMRA2POL_M 0x00001000 1327 #define AM_REG_CTIMER_CTRL2_TMRA2POL(n) (((uint32_t)(n) << 12) & 0x00001000) 1328 #define AM_REG_CTIMER_CTRL2_TMRA2POL_NORMAL 0x00000000 1329 #define AM_REG_CTIMER_CTRL2_TMRA2POL_INVERTED 0x00001000 1330 1331 // Counter/Timer A2 Clear bit. 1332 #define AM_REG_CTIMER_CTRL2_TMRA2CLR_S 11 1333 #define AM_REG_CTIMER_CTRL2_TMRA2CLR_M 0x00000800 1334 #define AM_REG_CTIMER_CTRL2_TMRA2CLR(n) (((uint32_t)(n) << 11) & 0x00000800) 1335 #define AM_REG_CTIMER_CTRL2_TMRA2CLR_RUN 0x00000000 1336 #define AM_REG_CTIMER_CTRL2_TMRA2CLR_CLEAR 0x00000800 1337 1338 // Counter/Timer A2 Interrupt Enable bit based on COMPR1. 1339 #define AM_REG_CTIMER_CTRL2_TMRA2IE1_S 10 1340 #define AM_REG_CTIMER_CTRL2_TMRA2IE1_M 0x00000400 1341 #define AM_REG_CTIMER_CTRL2_TMRA2IE1(n) (((uint32_t)(n) << 10) & 0x00000400) 1342 #define AM_REG_CTIMER_CTRL2_TMRA2IE1_DIS 0x00000000 1343 #define AM_REG_CTIMER_CTRL2_TMRA2IE1_EN 0x00000400 1344 1345 // Counter/Timer A2 Interrupt Enable bit based on COMPR0. 1346 #define AM_REG_CTIMER_CTRL2_TMRA2IE0_S 9 1347 #define AM_REG_CTIMER_CTRL2_TMRA2IE0_M 0x00000200 1348 #define AM_REG_CTIMER_CTRL2_TMRA2IE0(n) (((uint32_t)(n) << 9) & 0x00000200) 1349 #define AM_REG_CTIMER_CTRL2_TMRA2IE0_DIS 0x00000000 1350 #define AM_REG_CTIMER_CTRL2_TMRA2IE0_EN 0x00000200 1351 1352 // Counter/Timer A2 Function Select. 1353 #define AM_REG_CTIMER_CTRL2_TMRA2FN_S 6 1354 #define AM_REG_CTIMER_CTRL2_TMRA2FN_M 0x000001C0 1355 #define AM_REG_CTIMER_CTRL2_TMRA2FN(n) (((uint32_t)(n) << 6) & 0x000001C0) 1356 #define AM_REG_CTIMER_CTRL2_TMRA2FN_SINGLECOUNT 0x00000000 1357 #define AM_REG_CTIMER_CTRL2_TMRA2FN_REPEATEDCOUNT 0x00000040 1358 #define AM_REG_CTIMER_CTRL2_TMRA2FN_PULSE_ONCE 0x00000080 1359 #define AM_REG_CTIMER_CTRL2_TMRA2FN_PULSE_CONT 0x000000C0 1360 #define AM_REG_CTIMER_CTRL2_TMRA2FN_CONTINUOUS 0x00000100 1361 1362 // Counter/Timer A2 Clock Select. 1363 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_S 1 1364 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_M 0x0000003E 1365 #define AM_REG_CTIMER_CTRL2_TMRA2CLK(n) (((uint32_t)(n) << 1) & 0x0000003E) 1366 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_TMRPIN 0x00000000 1367 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4 0x00000002 1368 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV16 0x00000004 1369 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV256 0x00000006 1370 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV1024 0x00000008 1371 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4K 0x0000000A 1372 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_XT 0x0000000C 1373 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_XT_DIV2 0x0000000E 1374 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_XT_DIV16 0x00000010 1375 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_XT_DIV256 0x00000012 1376 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_LFRC_DIV2 0x00000014 1377 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_LFRC_DIV32 0x00000016 1378 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_LFRC_DIV1K 0x00000018 1379 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_LFRC 0x0000001A 1380 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_RTC_100HZ 0x0000001C 1381 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_HCLK 0x0000001E 1382 #define AM_REG_CTIMER_CTRL2_TMRA2CLK_BUCKB 0x00000020 1383 1384 // Counter/Timer A2 Enable bit. 1385 #define AM_REG_CTIMER_CTRL2_TMRA2EN_S 0 1386 #define AM_REG_CTIMER_CTRL2_TMRA2EN_M 0x00000001 1387 #define AM_REG_CTIMER_CTRL2_TMRA2EN(n) (((uint32_t)(n) << 0) & 0x00000001) 1388 #define AM_REG_CTIMER_CTRL2_TMRA2EN_DIS 0x00000000 1389 #define AM_REG_CTIMER_CTRL2_TMRA2EN_EN 0x00000001 1390 1391 //***************************************************************************** 1392 // 1393 // CTIMER_TMR3 - Counter/Timer Register 1394 // 1395 //***************************************************************************** 1396 // Counter/Timer B3. 1397 #define AM_REG_CTIMER_TMR3_CTTMRB3_S 16 1398 #define AM_REG_CTIMER_TMR3_CTTMRB3_M 0xFFFF0000 1399 #define AM_REG_CTIMER_TMR3_CTTMRB3(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 1400 1401 // Counter/Timer A3. 1402 #define AM_REG_CTIMER_TMR3_CTTMRA3_S 0 1403 #define AM_REG_CTIMER_TMR3_CTTMRA3_M 0x0000FFFF 1404 #define AM_REG_CTIMER_TMR3_CTTMRA3(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 1405 1406 //***************************************************************************** 1407 // 1408 // CTIMER_CMPRA3 - Counter/Timer A3 Compare Registers 1409 // 1410 //***************************************************************************** 1411 // Counter/Timer A3 Compare Register 1. 1412 #define AM_REG_CTIMER_CMPRA3_CMPR1A3_S 16 1413 #define AM_REG_CTIMER_CMPRA3_CMPR1A3_M 0xFFFF0000 1414 #define AM_REG_CTIMER_CMPRA3_CMPR1A3(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 1415 1416 // Counter/Timer A3 Compare Register 0. 1417 #define AM_REG_CTIMER_CMPRA3_CMPR0A3_S 0 1418 #define AM_REG_CTIMER_CMPRA3_CMPR0A3_M 0x0000FFFF 1419 #define AM_REG_CTIMER_CMPRA3_CMPR0A3(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 1420 1421 //***************************************************************************** 1422 // 1423 // CTIMER_CMPRB3 - Counter/Timer B3 Compare Registers 1424 // 1425 //***************************************************************************** 1426 // Counter/Timer B3 Compare Register 1. 1427 #define AM_REG_CTIMER_CMPRB3_CMPR1B3_S 16 1428 #define AM_REG_CTIMER_CMPRB3_CMPR1B3_M 0xFFFF0000 1429 #define AM_REG_CTIMER_CMPRB3_CMPR1B3(n) (((uint32_t)(n) << 16) & 0xFFFF0000) 1430 1431 // Counter/Timer B3 Compare Register 0. 1432 #define AM_REG_CTIMER_CMPRB3_CMPR0B3_S 0 1433 #define AM_REG_CTIMER_CMPRB3_CMPR0B3_M 0x0000FFFF 1434 #define AM_REG_CTIMER_CMPRB3_CMPR0B3(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 1435 1436 //***************************************************************************** 1437 // 1438 // CTIMER_CTRL3 - Counter/Timer Control 1439 // 1440 //***************************************************************************** 1441 // Counter/Timer A3/B3 Link bit. 1442 #define AM_REG_CTIMER_CTRL3_CTLINK3_S 31 1443 #define AM_REG_CTIMER_CTRL3_CTLINK3_M 0x80000000 1444 #define AM_REG_CTIMER_CTRL3_CTLINK3(n) (((uint32_t)(n) << 31) & 0x80000000) 1445 #define AM_REG_CTIMER_CTRL3_CTLINK3_TWO_16BIT_TIMERS 0x00000000 1446 #define AM_REG_CTIMER_CTRL3_CTLINK3_32BIT_TIMER 0x80000000 1447 1448 // Counter/Timer B3 Output Enable bit. 1449 #define AM_REG_CTIMER_CTRL3_TMRB3PE_S 29 1450 #define AM_REG_CTIMER_CTRL3_TMRB3PE_M 0x20000000 1451 #define AM_REG_CTIMER_CTRL3_TMRB3PE(n) (((uint32_t)(n) << 29) & 0x20000000) 1452 #define AM_REG_CTIMER_CTRL3_TMRB3PE_DIS 0x00000000 1453 #define AM_REG_CTIMER_CTRL3_TMRB3PE_EN 0x20000000 1454 1455 // Counter/Timer B3 output polarity. 1456 #define AM_REG_CTIMER_CTRL3_TMRB3POL_S 28 1457 #define AM_REG_CTIMER_CTRL3_TMRB3POL_M 0x10000000 1458 #define AM_REG_CTIMER_CTRL3_TMRB3POL(n) (((uint32_t)(n) << 28) & 0x10000000) 1459 #define AM_REG_CTIMER_CTRL3_TMRB3POL_NORMAL 0x00000000 1460 #define AM_REG_CTIMER_CTRL3_TMRB3POL_INVERTED 0x10000000 1461 1462 // Counter/Timer B3 Clear bit. 1463 #define AM_REG_CTIMER_CTRL3_TMRB3CLR_S 27 1464 #define AM_REG_CTIMER_CTRL3_TMRB3CLR_M 0x08000000 1465 #define AM_REG_CTIMER_CTRL3_TMRB3CLR(n) (((uint32_t)(n) << 27) & 0x08000000) 1466 #define AM_REG_CTIMER_CTRL3_TMRB3CLR_RUN 0x00000000 1467 #define AM_REG_CTIMER_CTRL3_TMRB3CLR_CLEAR 0x08000000 1468 1469 // Counter/Timer B3 Interrupt Enable bit for COMPR1. 1470 #define AM_REG_CTIMER_CTRL3_TMRB3IE1_S 26 1471 #define AM_REG_CTIMER_CTRL3_TMRB3IE1_M 0x04000000 1472 #define AM_REG_CTIMER_CTRL3_TMRB3IE1(n) (((uint32_t)(n) << 26) & 0x04000000) 1473 #define AM_REG_CTIMER_CTRL3_TMRB3IE1_DIS 0x00000000 1474 #define AM_REG_CTIMER_CTRL3_TMRB3IE1_EN 0x04000000 1475 1476 // Counter/Timer B3 Interrupt Enable bit for COMPR0. 1477 #define AM_REG_CTIMER_CTRL3_TMRB3IE0_S 25 1478 #define AM_REG_CTIMER_CTRL3_TMRB3IE0_M 0x02000000 1479 #define AM_REG_CTIMER_CTRL3_TMRB3IE0(n) (((uint32_t)(n) << 25) & 0x02000000) 1480 #define AM_REG_CTIMER_CTRL3_TMRB3IE0_DIS 0x00000000 1481 #define AM_REG_CTIMER_CTRL3_TMRB3IE0_EN 0x02000000 1482 1483 // Counter/Timer B3 Function Select. 1484 #define AM_REG_CTIMER_CTRL3_TMRB3FN_S 22 1485 #define AM_REG_CTIMER_CTRL3_TMRB3FN_M 0x01C00000 1486 #define AM_REG_CTIMER_CTRL3_TMRB3FN(n) (((uint32_t)(n) << 22) & 0x01C00000) 1487 #define AM_REG_CTIMER_CTRL3_TMRB3FN_SINGLECOUNT 0x00000000 1488 #define AM_REG_CTIMER_CTRL3_TMRB3FN_REPEATEDCOUNT 0x00400000 1489 #define AM_REG_CTIMER_CTRL3_TMRB3FN_PULSE_ONCE 0x00800000 1490 #define AM_REG_CTIMER_CTRL3_TMRB3FN_PULSE_CONT 0x00C00000 1491 #define AM_REG_CTIMER_CTRL3_TMRB3FN_CONTINUOUS 0x01000000 1492 1493 // Counter/Timer B3 Clock Select. 1494 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_S 17 1495 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_M 0x003E0000 1496 #define AM_REG_CTIMER_CTRL3_TMRB3CLK(n) (((uint32_t)(n) << 17) & 0x003E0000) 1497 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_TMRPIN 0x00000000 1498 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4 0x00020000 1499 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV16 0x00040000 1500 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV256 0x00060000 1501 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV1024 0x00080000 1502 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4K 0x000A0000 1503 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_XT 0x000C0000 1504 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_XT_DIV2 0x000E0000 1505 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_XT_DIV16 0x00100000 1506 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_XT_DIV256 0x00120000 1507 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_LFRC_DIV2 0x00140000 1508 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_LFRC_DIV32 0x00160000 1509 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_LFRC_DIV1K 0x00180000 1510 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_LFRC 0x001A0000 1511 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_RTC_100HZ 0x001C0000 1512 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_HCLK 0x001E0000 1513 #define AM_REG_CTIMER_CTRL3_TMRB3CLK_BUCKA 0x00200000 1514 1515 // Counter/Timer B3 Enable bit. 1516 #define AM_REG_CTIMER_CTRL3_TMRB3EN_S 16 1517 #define AM_REG_CTIMER_CTRL3_TMRB3EN_M 0x00010000 1518 #define AM_REG_CTIMER_CTRL3_TMRB3EN(n) (((uint32_t)(n) << 16) & 0x00010000) 1519 #define AM_REG_CTIMER_CTRL3_TMRB3EN_DIS 0x00000000 1520 #define AM_REG_CTIMER_CTRL3_TMRB3EN_EN 0x00010000 1521 1522 // Special Timer A3 enable for ADC function. 1523 #define AM_REG_CTIMER_CTRL3_ADCEN_S 15 1524 #define AM_REG_CTIMER_CTRL3_ADCEN_M 0x00008000 1525 #define AM_REG_CTIMER_CTRL3_ADCEN(n) (((uint32_t)(n) << 15) & 0x00008000) 1526 1527 // Counter/Timer A3 Output Enable bit. 1528 #define AM_REG_CTIMER_CTRL3_TMRA3PE_S 13 1529 #define AM_REG_CTIMER_CTRL3_TMRA3PE_M 0x00002000 1530 #define AM_REG_CTIMER_CTRL3_TMRA3PE(n) (((uint32_t)(n) << 13) & 0x00002000) 1531 #define AM_REG_CTIMER_CTRL3_TMRA3PE_DIS 0x00000000 1532 #define AM_REG_CTIMER_CTRL3_TMRA3PE_EN 0x00002000 1533 1534 // Counter/Timer A3 output polarity. 1535 #define AM_REG_CTIMER_CTRL3_TMRA3POL_S 12 1536 #define AM_REG_CTIMER_CTRL3_TMRA3POL_M 0x00001000 1537 #define AM_REG_CTIMER_CTRL3_TMRA3POL(n) (((uint32_t)(n) << 12) & 0x00001000) 1538 #define AM_REG_CTIMER_CTRL3_TMRA3POL_NORMAL 0x00000000 1539 #define AM_REG_CTIMER_CTRL3_TMRA3POL_INVERTED 0x00001000 1540 1541 // Counter/Timer A3 Clear bit. 1542 #define AM_REG_CTIMER_CTRL3_TMRA3CLR_S 11 1543 #define AM_REG_CTIMER_CTRL3_TMRA3CLR_M 0x00000800 1544 #define AM_REG_CTIMER_CTRL3_TMRA3CLR(n) (((uint32_t)(n) << 11) & 0x00000800) 1545 #define AM_REG_CTIMER_CTRL3_TMRA3CLR_RUN 0x00000000 1546 #define AM_REG_CTIMER_CTRL3_TMRA3CLR_CLEAR 0x00000800 1547 1548 // Counter/Timer A3 Interrupt Enable bit based on COMPR1. 1549 #define AM_REG_CTIMER_CTRL3_TMRA3IE1_S 10 1550 #define AM_REG_CTIMER_CTRL3_TMRA3IE1_M 0x00000400 1551 #define AM_REG_CTIMER_CTRL3_TMRA3IE1(n) (((uint32_t)(n) << 10) & 0x00000400) 1552 #define AM_REG_CTIMER_CTRL3_TMRA3IE1_DIS 0x00000000 1553 #define AM_REG_CTIMER_CTRL3_TMRA3IE1_EN 0x00000400 1554 1555 // Counter/Timer A3 Interrupt Enable bit based on COMPR0. 1556 #define AM_REG_CTIMER_CTRL3_TMRA3IE0_S 9 1557 #define AM_REG_CTIMER_CTRL3_TMRA3IE0_M 0x00000200 1558 #define AM_REG_CTIMER_CTRL3_TMRA3IE0(n) (((uint32_t)(n) << 9) & 0x00000200) 1559 #define AM_REG_CTIMER_CTRL3_TMRA3IE0_DIS 0x00000000 1560 #define AM_REG_CTIMER_CTRL3_TMRA3IE0_EN 0x00000200 1561 1562 // Counter/Timer A3 Function Select. 1563 #define AM_REG_CTIMER_CTRL3_TMRA3FN_S 6 1564 #define AM_REG_CTIMER_CTRL3_TMRA3FN_M 0x000001C0 1565 #define AM_REG_CTIMER_CTRL3_TMRA3FN(n) (((uint32_t)(n) << 6) & 0x000001C0) 1566 #define AM_REG_CTIMER_CTRL3_TMRA3FN_SINGLECOUNT 0x00000000 1567 #define AM_REG_CTIMER_CTRL3_TMRA3FN_REPEATEDCOUNT 0x00000040 1568 #define AM_REG_CTIMER_CTRL3_TMRA3FN_PULSE_ONCE 0x00000080 1569 #define AM_REG_CTIMER_CTRL3_TMRA3FN_PULSE_CONT 0x000000C0 1570 #define AM_REG_CTIMER_CTRL3_TMRA3FN_CONTINUOUS 0x00000100 1571 1572 // Counter/Timer A3 Clock Select. 1573 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_S 1 1574 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_M 0x0000003E 1575 #define AM_REG_CTIMER_CTRL3_TMRA3CLK(n) (((uint32_t)(n) << 1) & 0x0000003E) 1576 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_TMRPIN 0x00000000 1577 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4 0x00000002 1578 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV16 0x00000004 1579 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV256 0x00000006 1580 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV1024 0x00000008 1581 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4K 0x0000000A 1582 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_XT 0x0000000C 1583 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_XT_DIV2 0x0000000E 1584 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_XT_DIV16 0x00000010 1585 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_XT_DIV256 0x00000012 1586 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_LFRC_DIV2 0x00000014 1587 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_LFRC_DIV32 0x00000016 1588 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_LFRC_DIV1K 0x00000018 1589 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_LFRC 0x0000001A 1590 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_RTC_100HZ 0x0000001C 1591 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_HCLK 0x0000001E 1592 #define AM_REG_CTIMER_CTRL3_TMRA3CLK_BUCKB 0x00000020 1593 1594 // Counter/Timer A3 Enable bit. 1595 #define AM_REG_CTIMER_CTRL3_TMRA3EN_S 0 1596 #define AM_REG_CTIMER_CTRL3_TMRA3EN_M 0x00000001 1597 #define AM_REG_CTIMER_CTRL3_TMRA3EN(n) (((uint32_t)(n) << 0) & 0x00000001) 1598 #define AM_REG_CTIMER_CTRL3_TMRA3EN_DIS 0x00000000 1599 #define AM_REG_CTIMER_CTRL3_TMRA3EN_EN 0x00000001 1600 1601 //***************************************************************************** 1602 // 1603 // CTIMER_STCFG - Configuration Register 1604 // 1605 //***************************************************************************** 1606 // Set this bit to one to freeze the clock input to the COUNTER register. Once 1607 // frozen, the value can be safely written from the MCU. Unfreeze to resume. 1608 #define AM_REG_CTIMER_STCFG_FREEZE_S 31 1609 #define AM_REG_CTIMER_STCFG_FREEZE_M 0x80000000 1610 #define AM_REG_CTIMER_STCFG_FREEZE(n) (((uint32_t)(n) << 31) & 0x80000000) 1611 #define AM_REG_CTIMER_STCFG_FREEZE_THAW 0x00000000 1612 #define AM_REG_CTIMER_STCFG_FREEZE_FREEZE 0x80000000 1613 1614 // Set this bit to one to clear the System Timer register. If this bit is set 1615 // to '1', the system timer register will stay cleared. It needs to be set to 1616 // '0' for the system timer to start running. 1617 #define AM_REG_CTIMER_STCFG_CLEAR_S 30 1618 #define AM_REG_CTIMER_STCFG_CLEAR_M 0x40000000 1619 #define AM_REG_CTIMER_STCFG_CLEAR(n) (((uint32_t)(n) << 30) & 0x40000000) 1620 #define AM_REG_CTIMER_STCFG_CLEAR_RUN 0x00000000 1621 #define AM_REG_CTIMER_STCFG_CLEAR_CLEAR 0x40000000 1622 1623 // Selects whether compare is enabled for the corresponding SCMPR register. If 1624 // compare is enabled, the interrupt status is set once the comparision is met. 1625 #define AM_REG_CTIMER_STCFG_COMPARE_H_EN_S 15 1626 #define AM_REG_CTIMER_STCFG_COMPARE_H_EN_M 0x00008000 1627 #define AM_REG_CTIMER_STCFG_COMPARE_H_EN(n) (((uint32_t)(n) << 15) & 0x00008000) 1628 #define AM_REG_CTIMER_STCFG_COMPARE_H_EN_DISABLE 0x00000000 1629 #define AM_REG_CTIMER_STCFG_COMPARE_H_EN_ENABLE 0x00008000 1630 1631 // Selects whether compare is enabled for the corresponding SCMPR register. If 1632 // compare is enabled, the interrupt status is set once the comparision is met. 1633 #define AM_REG_CTIMER_STCFG_COMPARE_G_EN_S 14 1634 #define AM_REG_CTIMER_STCFG_COMPARE_G_EN_M 0x00004000 1635 #define AM_REG_CTIMER_STCFG_COMPARE_G_EN(n) (((uint32_t)(n) << 14) & 0x00004000) 1636 #define AM_REG_CTIMER_STCFG_COMPARE_G_EN_DISABLE 0x00000000 1637 #define AM_REG_CTIMER_STCFG_COMPARE_G_EN_ENABLE 0x00004000 1638 1639 // Selects whether compare is enabled for the corresponding SCMPR register. If 1640 // compare is enabled, the interrupt status is set once the comparision is met. 1641 #define AM_REG_CTIMER_STCFG_COMPARE_F_EN_S 13 1642 #define AM_REG_CTIMER_STCFG_COMPARE_F_EN_M 0x00002000 1643 #define AM_REG_CTIMER_STCFG_COMPARE_F_EN(n) (((uint32_t)(n) << 13) & 0x00002000) 1644 #define AM_REG_CTIMER_STCFG_COMPARE_F_EN_DISABLE 0x00000000 1645 #define AM_REG_CTIMER_STCFG_COMPARE_F_EN_ENABLE 0x00002000 1646 1647 // Selects whether compare is enabled for the corresponding SCMPR register. If 1648 // compare is enabled, the interrupt status is set once the comparision is met. 1649 #define AM_REG_CTIMER_STCFG_COMPARE_E_EN_S 12 1650 #define AM_REG_CTIMER_STCFG_COMPARE_E_EN_M 0x00001000 1651 #define AM_REG_CTIMER_STCFG_COMPARE_E_EN(n) (((uint32_t)(n) << 12) & 0x00001000) 1652 #define AM_REG_CTIMER_STCFG_COMPARE_E_EN_DISABLE 0x00000000 1653 #define AM_REG_CTIMER_STCFG_COMPARE_E_EN_ENABLE 0x00001000 1654 1655 // Selects whether compare is enabled for the corresponding SCMPR register. If 1656 // compare is enabled, the interrupt status is set once the comparision is met. 1657 #define AM_REG_CTIMER_STCFG_COMPARE_D_EN_S 11 1658 #define AM_REG_CTIMER_STCFG_COMPARE_D_EN_M 0x00000800 1659 #define AM_REG_CTIMER_STCFG_COMPARE_D_EN(n) (((uint32_t)(n) << 11) & 0x00000800) 1660 #define AM_REG_CTIMER_STCFG_COMPARE_D_EN_DISABLE 0x00000000 1661 #define AM_REG_CTIMER_STCFG_COMPARE_D_EN_ENABLE 0x00000800 1662 1663 // Selects whether compare is enabled for the corresponding SCMPR register. If 1664 // compare is enabled, the interrupt status is set once the comparision is met. 1665 #define AM_REG_CTIMER_STCFG_COMPARE_C_EN_S 10 1666 #define AM_REG_CTIMER_STCFG_COMPARE_C_EN_M 0x00000400 1667 #define AM_REG_CTIMER_STCFG_COMPARE_C_EN(n) (((uint32_t)(n) << 10) & 0x00000400) 1668 #define AM_REG_CTIMER_STCFG_COMPARE_C_EN_DISABLE 0x00000000 1669 #define AM_REG_CTIMER_STCFG_COMPARE_C_EN_ENABLE 0x00000400 1670 1671 // Selects whether compare is enabled for the corresponding SCMPR register. If 1672 // compare is enabled, the interrupt status is set once the comparision is met. 1673 #define AM_REG_CTIMER_STCFG_COMPARE_B_EN_S 9 1674 #define AM_REG_CTIMER_STCFG_COMPARE_B_EN_M 0x00000200 1675 #define AM_REG_CTIMER_STCFG_COMPARE_B_EN(n) (((uint32_t)(n) << 9) & 0x00000200) 1676 #define AM_REG_CTIMER_STCFG_COMPARE_B_EN_DISABLE 0x00000000 1677 #define AM_REG_CTIMER_STCFG_COMPARE_B_EN_ENABLE 0x00000200 1678 1679 // Selects whether compare is enabled for the corresponding SCMPR register. If 1680 // compare is enabled, the interrupt status is set once the comparision is met. 1681 #define AM_REG_CTIMER_STCFG_COMPARE_A_EN_S 8 1682 #define AM_REG_CTIMER_STCFG_COMPARE_A_EN_M 0x00000100 1683 #define AM_REG_CTIMER_STCFG_COMPARE_A_EN(n) (((uint32_t)(n) << 8) & 0x00000100) 1684 #define AM_REG_CTIMER_STCFG_COMPARE_A_EN_DISABLE 0x00000000 1685 #define AM_REG_CTIMER_STCFG_COMPARE_A_EN_ENABLE 0x00000100 1686 1687 // Selects an appropriate clock source and divider to use for the System Timer 1688 // clock. 1689 #define AM_REG_CTIMER_STCFG_CLKSEL_S 0 1690 #define AM_REG_CTIMER_STCFG_CLKSEL_M 0x0000000F 1691 #define AM_REG_CTIMER_STCFG_CLKSEL(n) (((uint32_t)(n) << 0) & 0x0000000F) 1692 #define AM_REG_CTIMER_STCFG_CLKSEL_NOCLK 0x00000000 1693 #define AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV16 0x00000001 1694 #define AM_REG_CTIMER_STCFG_CLKSEL_HFRC_DIV256 0x00000002 1695 #define AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV1 0x00000003 1696 #define AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV2 0x00000004 1697 #define AM_REG_CTIMER_STCFG_CLKSEL_XTAL_DIV32 0x00000005 1698 #define AM_REG_CTIMER_STCFG_CLKSEL_LFRC_DIV1 0x00000006 1699 #define AM_REG_CTIMER_STCFG_CLKSEL_CTIMER0A 0x00000007 1700 #define AM_REG_CTIMER_STCFG_CLKSEL_CTIMER0B 0x00000008 1701 1702 //***************************************************************************** 1703 // 1704 // CTIMER_STTMR - System Timer Count Register (Real Time Counter) 1705 // 1706 //***************************************************************************** 1707 // Value of the 32-bit counter as it ticks over. 1708 #define AM_REG_CTIMER_STTMR_VALUE_S 0 1709 #define AM_REG_CTIMER_STTMR_VALUE_M 0xFFFFFFFF 1710 #define AM_REG_CTIMER_STTMR_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1711 1712 //***************************************************************************** 1713 // 1714 // CTIMER_CAPTURE_CONTROL - Capture Control Register 1715 // 1716 //***************************************************************************** 1717 // Selects whether capture is enabled for the specified capture register. 1718 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_S 3 1719 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_M 0x00000008 1720 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D(n) (((uint32_t)(n) << 3) & 0x00000008) 1721 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_DISABLE 0x00000000 1722 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_D_ENABLE 0x00000008 1723 1724 // Selects whether capture is enabled for the specified capture register. 1725 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_S 2 1726 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_M 0x00000004 1727 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C(n) (((uint32_t)(n) << 2) & 0x00000004) 1728 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_DISABLE 0x00000000 1729 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_C_ENABLE 0x00000004 1730 1731 // Selects whether capture is enabled for the specified capture register. 1732 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_S 1 1733 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_M 0x00000002 1734 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B(n) (((uint32_t)(n) << 1) & 0x00000002) 1735 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_DISABLE 0x00000000 1736 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_B_ENABLE 0x00000002 1737 1738 // Selects whether capture is enabled for the specified capture register. 1739 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_S 0 1740 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_M 0x00000001 1741 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A(n) (((uint32_t)(n) << 0) & 0x00000001) 1742 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_DISABLE 0x00000000 1743 #define AM_REG_CTIMER_CAPTURE_CONTROL_CAPTURE_A_ENABLE 0x00000001 1744 1745 //***************************************************************************** 1746 // 1747 // CTIMER_SCMPR0 - Compare Register A 1748 // 1749 //***************************************************************************** 1750 // Compare this value to the value in the COUNTER register according to the 1751 // match criterion, as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF 1752 // register. 1753 #define AM_REG_CTIMER_SCMPR0_VALUE_S 0 1754 #define AM_REG_CTIMER_SCMPR0_VALUE_M 0xFFFFFFFF 1755 #define AM_REG_CTIMER_SCMPR0_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1756 1757 //***************************************************************************** 1758 // 1759 // CTIMER_SCMPR1 - Compare Register B 1760 // 1761 //***************************************************************************** 1762 // Compare this value to the value in the COUNTER register according to the 1763 // match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF 1764 // register. 1765 #define AM_REG_CTIMER_SCMPR1_VALUE_S 0 1766 #define AM_REG_CTIMER_SCMPR1_VALUE_M 0xFFFFFFFF 1767 #define AM_REG_CTIMER_SCMPR1_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1768 1769 //***************************************************************************** 1770 // 1771 // CTIMER_SCMPR2 - Compare Register C 1772 // 1773 //***************************************************************************** 1774 // Compare this value to the value in the COUNTER register according to the 1775 // match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF 1776 // register. 1777 #define AM_REG_CTIMER_SCMPR2_VALUE_S 0 1778 #define AM_REG_CTIMER_SCMPR2_VALUE_M 0xFFFFFFFF 1779 #define AM_REG_CTIMER_SCMPR2_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1780 1781 //***************************************************************************** 1782 // 1783 // CTIMER_SCMPR3 - Compare Register D 1784 // 1785 //***************************************************************************** 1786 // Compare this value to the value in the COUNTER register according to the 1787 // match criterion, as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF 1788 // register. 1789 #define AM_REG_CTIMER_SCMPR3_VALUE_S 0 1790 #define AM_REG_CTIMER_SCMPR3_VALUE_M 0xFFFFFFFF 1791 #define AM_REG_CTIMER_SCMPR3_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1792 1793 //***************************************************************************** 1794 // 1795 // CTIMER_SCMPR4 - Compare Register E 1796 // 1797 //***************************************************************************** 1798 // Compare this value to the value in the COUNTER register according to the 1799 // match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF 1800 // register. 1801 #define AM_REG_CTIMER_SCMPR4_VALUE_S 0 1802 #define AM_REG_CTIMER_SCMPR4_VALUE_M 0xFFFFFFFF 1803 #define AM_REG_CTIMER_SCMPR4_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1804 1805 //***************************************************************************** 1806 // 1807 // CTIMER_SCMPR5 - Compare Register F 1808 // 1809 //***************************************************************************** 1810 // Compare this value to the value in the COUNTER register according to the 1811 // match criterion, as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF 1812 // register. 1813 #define AM_REG_CTIMER_SCMPR5_VALUE_S 0 1814 #define AM_REG_CTIMER_SCMPR5_VALUE_M 0xFFFFFFFF 1815 #define AM_REG_CTIMER_SCMPR5_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1816 1817 //***************************************************************************** 1818 // 1819 // CTIMER_SCMPR6 - Compare Register G 1820 // 1821 //***************************************************************************** 1822 // Compare this value to the value in the COUNTER register according to the 1823 // match criterion, as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF 1824 // register. 1825 #define AM_REG_CTIMER_SCMPR6_VALUE_S 0 1826 #define AM_REG_CTIMER_SCMPR6_VALUE_M 0xFFFFFFFF 1827 #define AM_REG_CTIMER_SCMPR6_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1828 1829 //***************************************************************************** 1830 // 1831 // CTIMER_SCMPR7 - Compare Register H 1832 // 1833 //***************************************************************************** 1834 // Compare this value to the value in the COUNTER register according to the 1835 // match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF 1836 // register. 1837 #define AM_REG_CTIMER_SCMPR7_VALUE_S 0 1838 #define AM_REG_CTIMER_SCMPR7_VALUE_M 0xFFFFFFFF 1839 #define AM_REG_CTIMER_SCMPR7_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1840 1841 //***************************************************************************** 1842 // 1843 // CTIMER_SCAPT0 - Capture Register A 1844 // 1845 //***************************************************************************** 1846 // Whenever the event is detected, the value in the COUNTER is copied into this 1847 // register and the corresponding interrupt status bit is set. 1848 #define AM_REG_CTIMER_SCAPT0_VALUE_S 0 1849 #define AM_REG_CTIMER_SCAPT0_VALUE_M 0xFFFFFFFF 1850 #define AM_REG_CTIMER_SCAPT0_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1851 1852 //***************************************************************************** 1853 // 1854 // CTIMER_SCAPT1 - Capture Register B 1855 // 1856 //***************************************************************************** 1857 // Whenever the event is detected, the value in the COUNTER is copied into this 1858 // register and the corresponding interrupt status bit is set. 1859 #define AM_REG_CTIMER_SCAPT1_VALUE_S 0 1860 #define AM_REG_CTIMER_SCAPT1_VALUE_M 0xFFFFFFFF 1861 #define AM_REG_CTIMER_SCAPT1_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1862 1863 //***************************************************************************** 1864 // 1865 // CTIMER_SCAPT2 - Capture Register C 1866 // 1867 //***************************************************************************** 1868 // Whenever the event is detected, the value in the COUNTER is copied into this 1869 // register and the corresponding interrupt status bit is set. 1870 #define AM_REG_CTIMER_SCAPT2_VALUE_S 0 1871 #define AM_REG_CTIMER_SCAPT2_VALUE_M 0xFFFFFFFF 1872 #define AM_REG_CTIMER_SCAPT2_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1873 1874 //***************************************************************************** 1875 // 1876 // CTIMER_SCAPT3 - Capture Register D 1877 // 1878 //***************************************************************************** 1879 // Whenever the event is detected, the value in the COUNTER is copied into this 1880 // register and the corresponding interrupt status bit is set. 1881 #define AM_REG_CTIMER_SCAPT3_VALUE_S 0 1882 #define AM_REG_CTIMER_SCAPT3_VALUE_M 0xFFFFFFFF 1883 #define AM_REG_CTIMER_SCAPT3_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1884 1885 //***************************************************************************** 1886 // 1887 // CTIMER_SNVR0 - System Timer NVRAM_A Register 1888 // 1889 //***************************************************************************** 1890 // Value of the 32-bit counter as it ticks over. 1891 #define AM_REG_CTIMER_SNVR0_VALUE_S 0 1892 #define AM_REG_CTIMER_SNVR0_VALUE_M 0xFFFFFFFF 1893 #define AM_REG_CTIMER_SNVR0_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1894 1895 //***************************************************************************** 1896 // 1897 // CTIMER_SNVR1 - System Timer NVRAM_B Register 1898 // 1899 //***************************************************************************** 1900 // Value of the 32-bit counter as it ticks over. 1901 #define AM_REG_CTIMER_SNVR1_VALUE_S 0 1902 #define AM_REG_CTIMER_SNVR1_VALUE_M 0xFFFFFFFF 1903 #define AM_REG_CTIMER_SNVR1_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1904 1905 //***************************************************************************** 1906 // 1907 // CTIMER_SNVR2 - System Timer NVRAM_C Register 1908 // 1909 //***************************************************************************** 1910 // Value of the 32-bit counter as it ticks over. 1911 #define AM_REG_CTIMER_SNVR2_VALUE_S 0 1912 #define AM_REG_CTIMER_SNVR2_VALUE_M 0xFFFFFFFF 1913 #define AM_REG_CTIMER_SNVR2_VALUE(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 1914 1915 #endif // AM_REG_CTIMER_H 1916