1 //***************************************************************************** 2 // 3 // am_reg_ioslave.h 4 //! @file 5 //! 6 //! @brief Register macros for the IOSLAVE module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_IOSLAVE_H 45 #define AM_REG_IOSLAVE_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_IOSLAVE_NUM_MODULES 1 53 #define AM_REG_IOSLAVEn(n) \ 54 (REG_IOSLAVE_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_IOSLAVE_FIFOPTR_O 0x00000100 62 #define AM_REG_IOSLAVE_FIFOCFG_O 0x00000104 63 #define AM_REG_IOSLAVE_FIFOTHR_O 0x00000108 64 #define AM_REG_IOSLAVE_FUPD_O 0x0000010C 65 #define AM_REG_IOSLAVE_FIFOCTR_O 0x00000110 66 #define AM_REG_IOSLAVE_FIFOINC_O 0x00000114 67 #define AM_REG_IOSLAVE_CFG_O 0x00000118 68 #define AM_REG_IOSLAVE_PRENC_O 0x0000011C 69 #define AM_REG_IOSLAVE_IOINTCTL_O 0x00000120 70 #define AM_REG_IOSLAVE_GENADD_O 0x00000124 71 #define AM_REG_IOSLAVE_INTEN_O 0x00000200 72 #define AM_REG_IOSLAVE_INTSTAT_O 0x00000204 73 #define AM_REG_IOSLAVE_INTCLR_O 0x00000208 74 #define AM_REG_IOSLAVE_INTSET_O 0x0000020C 75 #define AM_REG_IOSLAVE_REGACCINTEN_O 0x00000210 76 #define AM_REG_IOSLAVE_REGACCINTSTAT_O 0x00000214 77 #define AM_REG_IOSLAVE_REGACCINTCLR_O 0x00000218 78 #define AM_REG_IOSLAVE_REGACCINTSET_O 0x0000021C 79 80 //***************************************************************************** 81 // 82 // IOSLAVE_INTEN - IO Slave Interrupts: Enable 83 // 84 //***************************************************************************** 85 // Transfer complete interrupt, write to register space. 86 #define AM_REG_IOSLAVE_INTEN_XCMPWR_S 9 87 #define AM_REG_IOSLAVE_INTEN_XCMPWR_M 0x00000200 88 #define AM_REG_IOSLAVE_INTEN_XCMPWR(n) (((uint32_t)(n) << 9) & 0x00000200) 89 90 // Transfer complete interrupt, write to FIFO space. 91 #define AM_REG_IOSLAVE_INTEN_XCMPWF_S 8 92 #define AM_REG_IOSLAVE_INTEN_XCMPWF_M 0x00000100 93 #define AM_REG_IOSLAVE_INTEN_XCMPWF(n) (((uint32_t)(n) << 8) & 0x00000100) 94 95 // Transfer complete interrupt, read from register space. 96 #define AM_REG_IOSLAVE_INTEN_XCMPRR_S 7 97 #define AM_REG_IOSLAVE_INTEN_XCMPRR_M 0x00000080 98 #define AM_REG_IOSLAVE_INTEN_XCMPRR(n) (((uint32_t)(n) << 7) & 0x00000080) 99 100 // Transfer complete interrupt, read from FIFO space. 101 #define AM_REG_IOSLAVE_INTEN_XCMPRF_S 6 102 #define AM_REG_IOSLAVE_INTEN_XCMPRF_M 0x00000040 103 #define AM_REG_IOSLAVE_INTEN_XCMPRF(n) (((uint32_t)(n) << 6) & 0x00000040) 104 105 // I2C Interrupt Write interrupt. 106 #define AM_REG_IOSLAVE_INTEN_IOINTW_S 5 107 #define AM_REG_IOSLAVE_INTEN_IOINTW_M 0x00000020 108 #define AM_REG_IOSLAVE_INTEN_IOINTW(n) (((uint32_t)(n) << 5) & 0x00000020) 109 110 // I2C General Address interrupt. 111 #define AM_REG_IOSLAVE_INTEN_GENAD_S 4 112 #define AM_REG_IOSLAVE_INTEN_GENAD_M 0x00000010 113 #define AM_REG_IOSLAVE_INTEN_GENAD(n) (((uint32_t)(n) << 4) & 0x00000010) 114 115 // FIFO Read Error interrupt. 116 #define AM_REG_IOSLAVE_INTEN_FRDERR_S 3 117 #define AM_REG_IOSLAVE_INTEN_FRDERR_M 0x00000008 118 #define AM_REG_IOSLAVE_INTEN_FRDERR(n) (((uint32_t)(n) << 3) & 0x00000008) 119 120 // FIFO Underflow interrupt. 121 #define AM_REG_IOSLAVE_INTEN_FUNDFL_S 2 122 #define AM_REG_IOSLAVE_INTEN_FUNDFL_M 0x00000004 123 #define AM_REG_IOSLAVE_INTEN_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) 124 125 // FIFO Overflow interrupt. 126 #define AM_REG_IOSLAVE_INTEN_FOVFL_S 1 127 #define AM_REG_IOSLAVE_INTEN_FOVFL_M 0x00000002 128 #define AM_REG_IOSLAVE_INTEN_FOVFL(n) (((uint32_t)(n) << 1) & 0x00000002) 129 130 // FIFO Size interrupt. 131 #define AM_REG_IOSLAVE_INTEN_FSIZE_S 0 132 #define AM_REG_IOSLAVE_INTEN_FSIZE_M 0x00000001 133 #define AM_REG_IOSLAVE_INTEN_FSIZE(n) (((uint32_t)(n) << 0) & 0x00000001) 134 135 //***************************************************************************** 136 // 137 // IOSLAVE_INTSTAT - IO Slave Interrupts: Status 138 // 139 //***************************************************************************** 140 // Transfer complete interrupt, write to register space. 141 #define AM_REG_IOSLAVE_INTSTAT_XCMPWR_S 9 142 #define AM_REG_IOSLAVE_INTSTAT_XCMPWR_M 0x00000200 143 #define AM_REG_IOSLAVE_INTSTAT_XCMPWR(n) (((uint32_t)(n) << 9) & 0x00000200) 144 145 // Transfer complete interrupt, write to FIFO space. 146 #define AM_REG_IOSLAVE_INTSTAT_XCMPWF_S 8 147 #define AM_REG_IOSLAVE_INTSTAT_XCMPWF_M 0x00000100 148 #define AM_REG_IOSLAVE_INTSTAT_XCMPWF(n) (((uint32_t)(n) << 8) & 0x00000100) 149 150 // Transfer complete interrupt, read from register space. 151 #define AM_REG_IOSLAVE_INTSTAT_XCMPRR_S 7 152 #define AM_REG_IOSLAVE_INTSTAT_XCMPRR_M 0x00000080 153 #define AM_REG_IOSLAVE_INTSTAT_XCMPRR(n) (((uint32_t)(n) << 7) & 0x00000080) 154 155 // Transfer complete interrupt, read from FIFO space. 156 #define AM_REG_IOSLAVE_INTSTAT_XCMPRF_S 6 157 #define AM_REG_IOSLAVE_INTSTAT_XCMPRF_M 0x00000040 158 #define AM_REG_IOSLAVE_INTSTAT_XCMPRF(n) (((uint32_t)(n) << 6) & 0x00000040) 159 160 // I2C Interrupt Write interrupt. 161 #define AM_REG_IOSLAVE_INTSTAT_IOINTW_S 5 162 #define AM_REG_IOSLAVE_INTSTAT_IOINTW_M 0x00000020 163 #define AM_REG_IOSLAVE_INTSTAT_IOINTW(n) (((uint32_t)(n) << 5) & 0x00000020) 164 165 // I2C General Address interrupt. 166 #define AM_REG_IOSLAVE_INTSTAT_GENAD_S 4 167 #define AM_REG_IOSLAVE_INTSTAT_GENAD_M 0x00000010 168 #define AM_REG_IOSLAVE_INTSTAT_GENAD(n) (((uint32_t)(n) << 4) & 0x00000010) 169 170 // FIFO Read Error interrupt. 171 #define AM_REG_IOSLAVE_INTSTAT_FRDERR_S 3 172 #define AM_REG_IOSLAVE_INTSTAT_FRDERR_M 0x00000008 173 #define AM_REG_IOSLAVE_INTSTAT_FRDERR(n) (((uint32_t)(n) << 3) & 0x00000008) 174 175 // FIFO Underflow interrupt. 176 #define AM_REG_IOSLAVE_INTSTAT_FUNDFL_S 2 177 #define AM_REG_IOSLAVE_INTSTAT_FUNDFL_M 0x00000004 178 #define AM_REG_IOSLAVE_INTSTAT_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) 179 180 // FIFO Overflow interrupt. 181 #define AM_REG_IOSLAVE_INTSTAT_FOVFL_S 1 182 #define AM_REG_IOSLAVE_INTSTAT_FOVFL_M 0x00000002 183 #define AM_REG_IOSLAVE_INTSTAT_FOVFL(n) (((uint32_t)(n) << 1) & 0x00000002) 184 185 // FIFO Size interrupt. 186 #define AM_REG_IOSLAVE_INTSTAT_FSIZE_S 0 187 #define AM_REG_IOSLAVE_INTSTAT_FSIZE_M 0x00000001 188 #define AM_REG_IOSLAVE_INTSTAT_FSIZE(n) (((uint32_t)(n) << 0) & 0x00000001) 189 190 //***************************************************************************** 191 // 192 // IOSLAVE_INTCLR - IO Slave Interrupts: Clear 193 // 194 //***************************************************************************** 195 // Transfer complete interrupt, write to register space. 196 #define AM_REG_IOSLAVE_INTCLR_XCMPWR_S 9 197 #define AM_REG_IOSLAVE_INTCLR_XCMPWR_M 0x00000200 198 #define AM_REG_IOSLAVE_INTCLR_XCMPWR(n) (((uint32_t)(n) << 9) & 0x00000200) 199 200 // Transfer complete interrupt, write to FIFO space. 201 #define AM_REG_IOSLAVE_INTCLR_XCMPWF_S 8 202 #define AM_REG_IOSLAVE_INTCLR_XCMPWF_M 0x00000100 203 #define AM_REG_IOSLAVE_INTCLR_XCMPWF(n) (((uint32_t)(n) << 8) & 0x00000100) 204 205 // Transfer complete interrupt, read from register space. 206 #define AM_REG_IOSLAVE_INTCLR_XCMPRR_S 7 207 #define AM_REG_IOSLAVE_INTCLR_XCMPRR_M 0x00000080 208 #define AM_REG_IOSLAVE_INTCLR_XCMPRR(n) (((uint32_t)(n) << 7) & 0x00000080) 209 210 // Transfer complete interrupt, read from FIFO space. 211 #define AM_REG_IOSLAVE_INTCLR_XCMPRF_S 6 212 #define AM_REG_IOSLAVE_INTCLR_XCMPRF_M 0x00000040 213 #define AM_REG_IOSLAVE_INTCLR_XCMPRF(n) (((uint32_t)(n) << 6) & 0x00000040) 214 215 // I2C Interrupt Write interrupt. 216 #define AM_REG_IOSLAVE_INTCLR_IOINTW_S 5 217 #define AM_REG_IOSLAVE_INTCLR_IOINTW_M 0x00000020 218 #define AM_REG_IOSLAVE_INTCLR_IOINTW(n) (((uint32_t)(n) << 5) & 0x00000020) 219 220 // I2C General Address interrupt. 221 #define AM_REG_IOSLAVE_INTCLR_GENAD_S 4 222 #define AM_REG_IOSLAVE_INTCLR_GENAD_M 0x00000010 223 #define AM_REG_IOSLAVE_INTCLR_GENAD(n) (((uint32_t)(n) << 4) & 0x00000010) 224 225 // FIFO Read Error interrupt. 226 #define AM_REG_IOSLAVE_INTCLR_FRDERR_S 3 227 #define AM_REG_IOSLAVE_INTCLR_FRDERR_M 0x00000008 228 #define AM_REG_IOSLAVE_INTCLR_FRDERR(n) (((uint32_t)(n) << 3) & 0x00000008) 229 230 // FIFO Underflow interrupt. 231 #define AM_REG_IOSLAVE_INTCLR_FUNDFL_S 2 232 #define AM_REG_IOSLAVE_INTCLR_FUNDFL_M 0x00000004 233 #define AM_REG_IOSLAVE_INTCLR_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) 234 235 // FIFO Overflow interrupt. 236 #define AM_REG_IOSLAVE_INTCLR_FOVFL_S 1 237 #define AM_REG_IOSLAVE_INTCLR_FOVFL_M 0x00000002 238 #define AM_REG_IOSLAVE_INTCLR_FOVFL(n) (((uint32_t)(n) << 1) & 0x00000002) 239 240 // FIFO Size interrupt. 241 #define AM_REG_IOSLAVE_INTCLR_FSIZE_S 0 242 #define AM_REG_IOSLAVE_INTCLR_FSIZE_M 0x00000001 243 #define AM_REG_IOSLAVE_INTCLR_FSIZE(n) (((uint32_t)(n) << 0) & 0x00000001) 244 245 //***************************************************************************** 246 // 247 // IOSLAVE_INTSET - IO Slave Interrupts: Set 248 // 249 //***************************************************************************** 250 // Transfer complete interrupt, write to register space. 251 #define AM_REG_IOSLAVE_INTSET_XCMPWR_S 9 252 #define AM_REG_IOSLAVE_INTSET_XCMPWR_M 0x00000200 253 #define AM_REG_IOSLAVE_INTSET_XCMPWR(n) (((uint32_t)(n) << 9) & 0x00000200) 254 255 // Transfer complete interrupt, write to FIFO space. 256 #define AM_REG_IOSLAVE_INTSET_XCMPWF_S 8 257 #define AM_REG_IOSLAVE_INTSET_XCMPWF_M 0x00000100 258 #define AM_REG_IOSLAVE_INTSET_XCMPWF(n) (((uint32_t)(n) << 8) & 0x00000100) 259 260 // Transfer complete interrupt, read from register space. 261 #define AM_REG_IOSLAVE_INTSET_XCMPRR_S 7 262 #define AM_REG_IOSLAVE_INTSET_XCMPRR_M 0x00000080 263 #define AM_REG_IOSLAVE_INTSET_XCMPRR(n) (((uint32_t)(n) << 7) & 0x00000080) 264 265 // Transfer complete interrupt, read from FIFO space. 266 #define AM_REG_IOSLAVE_INTSET_XCMPRF_S 6 267 #define AM_REG_IOSLAVE_INTSET_XCMPRF_M 0x00000040 268 #define AM_REG_IOSLAVE_INTSET_XCMPRF(n) (((uint32_t)(n) << 6) & 0x00000040) 269 270 // I2C Interrupt Write interrupt. 271 #define AM_REG_IOSLAVE_INTSET_IOINTW_S 5 272 #define AM_REG_IOSLAVE_INTSET_IOINTW_M 0x00000020 273 #define AM_REG_IOSLAVE_INTSET_IOINTW(n) (((uint32_t)(n) << 5) & 0x00000020) 274 275 // I2C General Address interrupt. 276 #define AM_REG_IOSLAVE_INTSET_GENAD_S 4 277 #define AM_REG_IOSLAVE_INTSET_GENAD_M 0x00000010 278 #define AM_REG_IOSLAVE_INTSET_GENAD(n) (((uint32_t)(n) << 4) & 0x00000010) 279 280 // FIFO Read Error interrupt. 281 #define AM_REG_IOSLAVE_INTSET_FRDERR_S 3 282 #define AM_REG_IOSLAVE_INTSET_FRDERR_M 0x00000008 283 #define AM_REG_IOSLAVE_INTSET_FRDERR(n) (((uint32_t)(n) << 3) & 0x00000008) 284 285 // FIFO Underflow interrupt. 286 #define AM_REG_IOSLAVE_INTSET_FUNDFL_S 2 287 #define AM_REG_IOSLAVE_INTSET_FUNDFL_M 0x00000004 288 #define AM_REG_IOSLAVE_INTSET_FUNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) 289 290 // FIFO Overflow interrupt. 291 #define AM_REG_IOSLAVE_INTSET_FOVFL_S 1 292 #define AM_REG_IOSLAVE_INTSET_FOVFL_M 0x00000002 293 #define AM_REG_IOSLAVE_INTSET_FOVFL(n) (((uint32_t)(n) << 1) & 0x00000002) 294 295 // FIFO Size interrupt. 296 #define AM_REG_IOSLAVE_INTSET_FSIZE_S 0 297 #define AM_REG_IOSLAVE_INTSET_FSIZE_M 0x00000001 298 #define AM_REG_IOSLAVE_INTSET_FSIZE(n) (((uint32_t)(n) << 0) & 0x00000001) 299 300 //***************************************************************************** 301 // 302 // IOSLAVE_REGACCINTEN - Register Access Interrupts: Enable 303 // 304 //***************************************************************************** 305 // Register access interrupts. 306 #define AM_REG_IOSLAVE_REGACCINTEN_REGACC_S 0 307 #define AM_REG_IOSLAVE_REGACCINTEN_REGACC_M 0xFFFFFFFF 308 #define AM_REG_IOSLAVE_REGACCINTEN_REGACC(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 309 310 //***************************************************************************** 311 // 312 // IOSLAVE_REGACCINTSTAT - Register Access Interrupts: Status 313 // 314 //***************************************************************************** 315 // Register access interrupts. 316 #define AM_REG_IOSLAVE_REGACCINTSTAT_REGACC_S 0 317 #define AM_REG_IOSLAVE_REGACCINTSTAT_REGACC_M 0xFFFFFFFF 318 #define AM_REG_IOSLAVE_REGACCINTSTAT_REGACC(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 319 320 //***************************************************************************** 321 // 322 // IOSLAVE_REGACCINTCLR - Register Access Interrupts: Clear 323 // 324 //***************************************************************************** 325 // Register access interrupts. 326 #define AM_REG_IOSLAVE_REGACCINTCLR_REGACC_S 0 327 #define AM_REG_IOSLAVE_REGACCINTCLR_REGACC_M 0xFFFFFFFF 328 #define AM_REG_IOSLAVE_REGACCINTCLR_REGACC(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 329 330 //***************************************************************************** 331 // 332 // IOSLAVE_REGACCINTSET - Register Access Interrupts: Set 333 // 334 //***************************************************************************** 335 // Register access interrupts. 336 #define AM_REG_IOSLAVE_REGACCINTSET_REGACC_S 0 337 #define AM_REG_IOSLAVE_REGACCINTSET_REGACC_M 0xFFFFFFFF 338 #define AM_REG_IOSLAVE_REGACCINTSET_REGACC(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 339 340 //***************************************************************************** 341 // 342 // IOSLAVE_FIFOPTR - Current FIFO Pointer 343 // 344 //***************************************************************************** 345 // The number of bytes currently in the hardware FIFO. 346 #define AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_S 8 347 #define AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ_M 0x0000FF00 348 #define AM_REG_IOSLAVE_FIFOPTR_FIFOSIZ(n) (((uint32_t)(n) << 8) & 0x0000FF00) 349 350 // Current FIFO pointer. 351 #define AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_S 0 352 #define AM_REG_IOSLAVE_FIFOPTR_FIFOPTR_M 0x000000FF 353 #define AM_REG_IOSLAVE_FIFOPTR_FIFOPTR(n) (((uint32_t)(n) << 0) & 0x000000FF) 354 355 //***************************************************************************** 356 // 357 // IOSLAVE_FIFOCFG - FIFO Configuration 358 // 359 //***************************************************************************** 360 // Defines the read-only area. The IO Slave read-only area is situated in LRAM 361 // at (ROBASE*8) to (FIFOOBASE*8-1) 362 #define AM_REG_IOSLAVE_FIFOCFG_ROBASE_S 24 363 #define AM_REG_IOSLAVE_FIFOCFG_ROBASE_M 0x3F000000 364 #define AM_REG_IOSLAVE_FIFOCFG_ROBASE(n) (((uint32_t)(n) << 24) & 0x3F000000) 365 366 // These bits hold the maximum FIFO address in 8 byte segments. It is also the 367 // beginning of the RAM area of the LRAM. Note that no RAM area is configured 368 // if FIFOMAX is set to 0x1F. 369 #define AM_REG_IOSLAVE_FIFOCFG_FIFOMAX_S 8 370 #define AM_REG_IOSLAVE_FIFOCFG_FIFOMAX_M 0x00003F00 371 #define AM_REG_IOSLAVE_FIFOCFG_FIFOMAX(n) (((uint32_t)(n) << 8) & 0x00003F00) 372 373 // These bits hold the base address of the I/O FIFO in 8 byte segments. The IO 374 // Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1). 375 #define AM_REG_IOSLAVE_FIFOCFG_FIFOBASE_S 0 376 #define AM_REG_IOSLAVE_FIFOCFG_FIFOBASE_M 0x0000001F 377 #define AM_REG_IOSLAVE_FIFOCFG_FIFOBASE(n) (((uint32_t)(n) << 0) & 0x0000001F) 378 379 //***************************************************************************** 380 // 381 // IOSLAVE_FIFOTHR - FIFO Threshold Configuration 382 // 383 //***************************************************************************** 384 // FIFO size interrupt threshold. 385 #define AM_REG_IOSLAVE_FIFOTHR_FIFOTHR_S 0 386 #define AM_REG_IOSLAVE_FIFOTHR_FIFOTHR_M 0x000000FF 387 #define AM_REG_IOSLAVE_FIFOTHR_FIFOTHR(n) (((uint32_t)(n) << 0) & 0x000000FF) 388 389 //***************************************************************************** 390 // 391 // IOSLAVE_FUPD - FIFO Update Status 392 // 393 //***************************************************************************** 394 // This bitfield indicates an IO read is active. 395 #define AM_REG_IOSLAVE_FUPD_IOREAD_S 1 396 #define AM_REG_IOSLAVE_FUPD_IOREAD_M 0x00000002 397 #define AM_REG_IOSLAVE_FUPD_IOREAD(n) (((uint32_t)(n) << 1) & 0x00000002) 398 399 // This bit indicates that a FIFO update is underway. 400 #define AM_REG_IOSLAVE_FUPD_FIFOUPD_S 0 401 #define AM_REG_IOSLAVE_FUPD_FIFOUPD_M 0x00000001 402 #define AM_REG_IOSLAVE_FUPD_FIFOUPD(n) (((uint32_t)(n) << 0) & 0x00000001) 403 404 //***************************************************************************** 405 // 406 // IOSLAVE_FIFOCTR - Overall FIFO Counter 407 // 408 //***************************************************************************** 409 // Virtual FIFO byte count 410 #define AM_REG_IOSLAVE_FIFOCTR_FIFOCTR_S 0 411 #define AM_REG_IOSLAVE_FIFOCTR_FIFOCTR_M 0x000003FF 412 #define AM_REG_IOSLAVE_FIFOCTR_FIFOCTR(n) (((uint32_t)(n) << 0) & 0x000003FF) 413 414 //***************************************************************************** 415 // 416 // IOSLAVE_FIFOINC - Overall FIFO Counter Increment 417 // 418 //***************************************************************************** 419 // Increment the Overall FIFO Counter by this value on a write 420 #define AM_REG_IOSLAVE_FIFOINC_FIFOINC_S 0 421 #define AM_REG_IOSLAVE_FIFOINC_FIFOINC_M 0x000003FF 422 #define AM_REG_IOSLAVE_FIFOINC_FIFOINC(n) (((uint32_t)(n) << 0) & 0x000003FF) 423 424 //***************************************************************************** 425 // 426 // IOSLAVE_CFG - I/O Slave Configuration 427 // 428 //***************************************************************************** 429 // IOSLAVE interface enable. 430 #define AM_REG_IOSLAVE_CFG_IFCEN_S 31 431 #define AM_REG_IOSLAVE_CFG_IFCEN_M 0x80000000 432 #define AM_REG_IOSLAVE_CFG_IFCEN(n) (((uint32_t)(n) << 31) & 0x80000000) 433 #define AM_REG_IOSLAVE_CFG_IFCEN_DIS 0x00000000 434 #define AM_REG_IOSLAVE_CFG_IFCEN_EN 0x80000000 435 436 // 7-bit or 10-bit I2C device address. 437 #define AM_REG_IOSLAVE_CFG_I2CADDR_S 8 438 #define AM_REG_IOSLAVE_CFG_I2CADDR_M 0x000FFF00 439 #define AM_REG_IOSLAVE_CFG_I2CADDR(n) (((uint32_t)(n) << 8) & 0x000FFF00) 440 441 // This bit holds the cycle to initiate an I/O RAM read. 442 #define AM_REG_IOSLAVE_CFG_STARTRD_S 4 443 #define AM_REG_IOSLAVE_CFG_STARTRD_M 0x00000010 444 #define AM_REG_IOSLAVE_CFG_STARTRD(n) (((uint32_t)(n) << 4) & 0x00000010) 445 #define AM_REG_IOSLAVE_CFG_STARTRD_LATE 0x00000000 446 #define AM_REG_IOSLAVE_CFG_STARTRD_EARLY 0x00000010 447 448 // This bit selects the transfer bit ordering. 449 #define AM_REG_IOSLAVE_CFG_LSB_S 2 450 #define AM_REG_IOSLAVE_CFG_LSB_M 0x00000004 451 #define AM_REG_IOSLAVE_CFG_LSB(n) (((uint32_t)(n) << 2) & 0x00000004) 452 #define AM_REG_IOSLAVE_CFG_LSB_MSB_FIRST 0x00000000 453 #define AM_REG_IOSLAVE_CFG_LSB_LSB_FIRST 0x00000004 454 455 // This bit selects SPI polarity. 456 #define AM_REG_IOSLAVE_CFG_SPOL_S 1 457 #define AM_REG_IOSLAVE_CFG_SPOL_M 0x00000002 458 #define AM_REG_IOSLAVE_CFG_SPOL(n) (((uint32_t)(n) << 1) & 0x00000002) 459 #define AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_0_3 0x00000000 460 #define AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_1_2 0x00000002 461 462 // This bit selects the I/O interface. 463 #define AM_REG_IOSLAVE_CFG_IFCSEL_S 0 464 #define AM_REG_IOSLAVE_CFG_IFCSEL_M 0x00000001 465 #define AM_REG_IOSLAVE_CFG_IFCSEL(n) (((uint32_t)(n) << 0) & 0x00000001) 466 #define AM_REG_IOSLAVE_CFG_IFCSEL_I2C 0x00000000 467 #define AM_REG_IOSLAVE_CFG_IFCSEL_SPI 0x00000001 468 469 //***************************************************************************** 470 // 471 // IOSLAVE_PRENC - I/O Slave Interrupt Priority Encode 472 // 473 //***************************************************************************** 474 // These bits hold the priority encode of the REGACC interrupts. 475 #define AM_REG_IOSLAVE_PRENC_PRENC_S 0 476 #define AM_REG_IOSLAVE_PRENC_PRENC_M 0x0000001F 477 #define AM_REG_IOSLAVE_PRENC_PRENC(n) (((uint32_t)(n) << 0) & 0x0000001F) 478 479 //***************************************************************************** 480 // 481 // IOSLAVE_IOINTCTL - I/O Interrupt Control 482 // 483 //***************************************************************************** 484 // These bits set the IOINT interrupts when written with a 1. 485 #define AM_REG_IOSLAVE_IOINTCTL_IOINTSET_S 24 486 #define AM_REG_IOSLAVE_IOINTCTL_IOINTSET_M 0xFF000000 487 #define AM_REG_IOSLAVE_IOINTCTL_IOINTSET(n) (((uint32_t)(n) << 24) & 0xFF000000) 488 489 // This bit clears all of the IOINT interrupts when written with a 1. 490 #define AM_REG_IOSLAVE_IOINTCTL_IOINTCLR_S 16 491 #define AM_REG_IOSLAVE_IOINTCTL_IOINTCLR_M 0x00010000 492 #define AM_REG_IOSLAVE_IOINTCTL_IOINTCLR(n) (((uint32_t)(n) << 16) & 0x00010000) 493 494 // These bits read the IOINT interrupts. 495 #define AM_REG_IOSLAVE_IOINTCTL_IOINT_S 8 496 #define AM_REG_IOSLAVE_IOINTCTL_IOINT_M 0x0000FF00 497 #define AM_REG_IOSLAVE_IOINTCTL_IOINT(n) (((uint32_t)(n) << 8) & 0x0000FF00) 498 499 // These read-only bits indicate whether the IOINT interrupts are enabled. 500 #define AM_REG_IOSLAVE_IOINTCTL_IOINTEN_S 0 501 #define AM_REG_IOSLAVE_IOINTCTL_IOINTEN_M 0x000000FF 502 #define AM_REG_IOSLAVE_IOINTCTL_IOINTEN(n) (((uint32_t)(n) << 0) & 0x000000FF) 503 504 //***************************************************************************** 505 // 506 // IOSLAVE_GENADD - General Address Data 507 // 508 //***************************************************************************** 509 // The data supplied on the last General Address reference. 510 #define AM_REG_IOSLAVE_GENADD_GADATA_S 0 511 #define AM_REG_IOSLAVE_GENADD_GADATA_M 0x000000FF 512 #define AM_REG_IOSLAVE_GENADD_GADATA(n) (((uint32_t)(n) << 0) & 0x000000FF) 513 514 #endif // AM_REG_IOSLAVE_H 515