1 //***************************************************************************** 2 // 3 // am_reg_nvic.h 4 //! @file 5 //! 6 //! @brief Register macros for the NVIC module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_NVIC_H 45 #define AM_REG_NVIC_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_NVIC_NUM_MODULES 1 53 #define AM_REG_NVICn(n) \ 54 (REG_NVIC_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_NVIC_ISER0_O 0xE000E100 62 #define AM_REG_NVIC_ICER0_O 0xE000E180 63 #define AM_REG_NVIC_ISPR0_O 0xE000E200 64 #define AM_REG_NVIC_ICPR0_O 0xE000E280 65 #define AM_REG_NVIC_IABR0_O 0xE000E300 66 #define AM_REG_NVIC_IPR0_O 0xE000E400 67 #define AM_REG_NVIC_IPR1_O 0xE000E404 68 #define AM_REG_NVIC_IPR2_O 0xE000E408 69 #define AM_REG_NVIC_IPR3_O 0xE000E40C 70 #define AM_REG_NVIC_IPR4_O 0xE000E410 71 #define AM_REG_NVIC_IPR5_O 0xE000E414 72 #define AM_REG_NVIC_IPR6_O 0xE000E418 73 #define AM_REG_NVIC_IPR7_O 0xE000E41C 74 75 //***************************************************************************** 76 // 77 // NVIC_ISER0 - Interrupt Set-Enable Register 0 78 // 79 //***************************************************************************** 80 // NVIC_ISERn[31:0] are the set-enable bits for interrupts 31 through 0. 81 #define AM_REG_NVIC_ISER0_BITS_S 0 82 #define AM_REG_NVIC_ISER0_BITS_M 0xFFFFFFFF 83 #define AM_REG_NVIC_ISER0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 84 85 //***************************************************************************** 86 // 87 // NVIC_ICER0 - Interrupt Clear-Enable Register 0 88 // 89 //***************************************************************************** 90 // NVIC_ISERn[31:0] are the clear-enable bits for interrupts 31 through 0. 91 #define AM_REG_NVIC_ICER0_BITS_S 0 92 #define AM_REG_NVIC_ICER0_BITS_M 0xFFFFFFFF 93 #define AM_REG_NVIC_ICER0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 94 95 //***************************************************************************** 96 // 97 // NVIC_ISPR0 - Interrupt Set-Pending Register 0 98 // 99 //***************************************************************************** 100 // NVIC_ISERn[31:0] are the set-pending bits for interrupts 31 through 0. 101 #define AM_REG_NVIC_ISPR0_BITS_S 0 102 #define AM_REG_NVIC_ISPR0_BITS_M 0xFFFFFFFF 103 #define AM_REG_NVIC_ISPR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 104 105 //***************************************************************************** 106 // 107 // NVIC_ICPR0 - Interrupt Clear-Pending Register 0 108 // 109 //***************************************************************************** 110 // NVIC_ISERn[31:0] are the clear-pending bits for interrupts 31 through 0. 111 #define AM_REG_NVIC_ICPR0_BITS_S 0 112 #define AM_REG_NVIC_ICPR0_BITS_M 0xFFFFFFFF 113 #define AM_REG_NVIC_ICPR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 114 115 //***************************************************************************** 116 // 117 // NVIC_IABR0 - Interrupt Active Bit Register 0 118 // 119 //***************************************************************************** 120 // NVIC_ISERn[31:0] are the interrupt active bits for interrupts 31 through 0. 121 #define AM_REG_NVIC_IABR0_BITS_S 0 122 #define AM_REG_NVIC_IABR0_BITS_M 0xFFFFFFFF 123 #define AM_REG_NVIC_IABR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 124 125 //***************************************************************************** 126 // 127 // NVIC_IPR0 - Interrupt Priority Register 0 128 // 129 //***************************************************************************** 130 // Priority assignment for interrupt vector 3. 131 #define AM_REG_NVIC_IPR0_PRI_N3_S 24 132 #define AM_REG_NVIC_IPR0_PRI_N3_M 0xFF000000 133 #define AM_REG_NVIC_IPR0_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) 134 135 // Priority assignment for interrupt vector 2. 136 #define AM_REG_NVIC_IPR0_PRI_N2_S 16 137 #define AM_REG_NVIC_IPR0_PRI_N2_M 0x00FF0000 138 #define AM_REG_NVIC_IPR0_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) 139 140 // Priority assignment for interrupt vector 1. 141 #define AM_REG_NVIC_IPR0_PRI_N1_S 8 142 #define AM_REG_NVIC_IPR0_PRI_N1_M 0x0000FF00 143 #define AM_REG_NVIC_IPR0_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) 144 145 // Priority assignment for interrupt vector 0. 146 #define AM_REG_NVIC_IPR0_PRI_N0_S 0 147 #define AM_REG_NVIC_IPR0_PRI_N0_M 0x000000FF 148 #define AM_REG_NVIC_IPR0_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) 149 150 //***************************************************************************** 151 // 152 // NVIC_IPR1 - Interrupt Priority Register 1 153 // 154 //***************************************************************************** 155 // Priority assignment for interrupt vector 7. 156 #define AM_REG_NVIC_IPR1_PRI_N3_S 24 157 #define AM_REG_NVIC_IPR1_PRI_N3_M 0xFF000000 158 #define AM_REG_NVIC_IPR1_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) 159 160 // Priority assignment for interrupt vector 6. 161 #define AM_REG_NVIC_IPR1_PRI_N2_S 16 162 #define AM_REG_NVIC_IPR1_PRI_N2_M 0x00FF0000 163 #define AM_REG_NVIC_IPR1_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) 164 165 // Priority assignment for interrupt vector 5. 166 #define AM_REG_NVIC_IPR1_PRI_N1_S 8 167 #define AM_REG_NVIC_IPR1_PRI_N1_M 0x0000FF00 168 #define AM_REG_NVIC_IPR1_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) 169 170 // Priority assignment for interrupt vector 4. 171 #define AM_REG_NVIC_IPR1_PRI_N0_S 0 172 #define AM_REG_NVIC_IPR1_PRI_N0_M 0x000000FF 173 #define AM_REG_NVIC_IPR1_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) 174 175 //***************************************************************************** 176 // 177 // NVIC_IPR2 - Interrupt Priority Register 2 178 // 179 //***************************************************************************** 180 // Priority assignment for interrupt vector 11. 181 #define AM_REG_NVIC_IPR2_PRI_N3_S 24 182 #define AM_REG_NVIC_IPR2_PRI_N3_M 0xFF000000 183 #define AM_REG_NVIC_IPR2_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) 184 185 // Priority assignment for interrupt vector 10. 186 #define AM_REG_NVIC_IPR2_PRI_N2_S 16 187 #define AM_REG_NVIC_IPR2_PRI_N2_M 0x00FF0000 188 #define AM_REG_NVIC_IPR2_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) 189 190 // Priority assignment for interrupt vector 9. 191 #define AM_REG_NVIC_IPR2_PRI_N1_S 8 192 #define AM_REG_NVIC_IPR2_PRI_N1_M 0x0000FF00 193 #define AM_REG_NVIC_IPR2_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) 194 195 // Priority assignment for interrupt vector 8. 196 #define AM_REG_NVIC_IPR2_PRI_N0_S 0 197 #define AM_REG_NVIC_IPR2_PRI_N0_M 0x000000FF 198 #define AM_REG_NVIC_IPR2_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) 199 200 //***************************************************************************** 201 // 202 // NVIC_IPR3 - Interrupt Priority Register 3 203 // 204 //***************************************************************************** 205 // Priority assignment for interrupt vector 15. 206 #define AM_REG_NVIC_IPR3_PRI_N3_S 24 207 #define AM_REG_NVIC_IPR3_PRI_N3_M 0xFF000000 208 #define AM_REG_NVIC_IPR3_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) 209 210 // Priority assignment for interrupt vector 14. 211 #define AM_REG_NVIC_IPR3_PRI_N2_S 16 212 #define AM_REG_NVIC_IPR3_PRI_N2_M 0x00FF0000 213 #define AM_REG_NVIC_IPR3_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) 214 215 // Priority assignment for interrupt vector 13. 216 #define AM_REG_NVIC_IPR3_PRI_N1_S 8 217 #define AM_REG_NVIC_IPR3_PRI_N1_M 0x0000FF00 218 #define AM_REG_NVIC_IPR3_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) 219 220 // Priority assignment for interrupt vector 12. 221 #define AM_REG_NVIC_IPR3_PRI_N0_S 0 222 #define AM_REG_NVIC_IPR3_PRI_N0_M 0x000000FF 223 #define AM_REG_NVIC_IPR3_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) 224 225 //***************************************************************************** 226 // 227 // NVIC_IPR4 - Interrupt Priority Register 4 228 // 229 //***************************************************************************** 230 // Priority assignment for interrupt vector 19. 231 #define AM_REG_NVIC_IPR4_PRI_N3_S 24 232 #define AM_REG_NVIC_IPR4_PRI_N3_M 0xFF000000 233 #define AM_REG_NVIC_IPR4_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) 234 235 // Priority assignment for interrupt vector 18. 236 #define AM_REG_NVIC_IPR4_PRI_N2_S 16 237 #define AM_REG_NVIC_IPR4_PRI_N2_M 0x00FF0000 238 #define AM_REG_NVIC_IPR4_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) 239 240 // Priority assignment for interrupt vector 17. 241 #define AM_REG_NVIC_IPR4_PRI_N1_S 8 242 #define AM_REG_NVIC_IPR4_PRI_N1_M 0x0000FF00 243 #define AM_REG_NVIC_IPR4_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) 244 245 // Priority assignment for interrupt vector 16. 246 #define AM_REG_NVIC_IPR4_PRI_N0_S 0 247 #define AM_REG_NVIC_IPR4_PRI_N0_M 0x000000FF 248 #define AM_REG_NVIC_IPR4_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) 249 250 //***************************************************************************** 251 // 252 // NVIC_IPR5 - Interrupt Priority Register 5 253 // 254 //***************************************************************************** 255 // Priority assignment for interrupt vector 23. 256 #define AM_REG_NVIC_IPR5_PRI_N3_S 24 257 #define AM_REG_NVIC_IPR5_PRI_N3_M 0xFF000000 258 #define AM_REG_NVIC_IPR5_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) 259 260 // Priority assignment for interrupt vector 22. 261 #define AM_REG_NVIC_IPR5_PRI_N2_S 16 262 #define AM_REG_NVIC_IPR5_PRI_N2_M 0x00FF0000 263 #define AM_REG_NVIC_IPR5_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) 264 265 // Priority assignment for interrupt vector 21. 266 #define AM_REG_NVIC_IPR5_PRI_N1_S 8 267 #define AM_REG_NVIC_IPR5_PRI_N1_M 0x0000FF00 268 #define AM_REG_NVIC_IPR5_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) 269 270 // Priority assignment for interrupt vector 20. 271 #define AM_REG_NVIC_IPR5_PRI_N0_S 0 272 #define AM_REG_NVIC_IPR5_PRI_N0_M 0x000000FF 273 #define AM_REG_NVIC_IPR5_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) 274 275 //***************************************************************************** 276 // 277 // NVIC_IPR6 - Interrupt Priority Register 6 278 // 279 //***************************************************************************** 280 // Priority assignment for interrupt vector 27. 281 #define AM_REG_NVIC_IPR6_PRI_N3_S 24 282 #define AM_REG_NVIC_IPR6_PRI_N3_M 0xFF000000 283 #define AM_REG_NVIC_IPR6_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) 284 285 // Priority assignment for interrupt vector 26. 286 #define AM_REG_NVIC_IPR6_PRI_N2_S 16 287 #define AM_REG_NVIC_IPR6_PRI_N2_M 0x00FF0000 288 #define AM_REG_NVIC_IPR6_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) 289 290 // Priority assignment for interrupt vector 25. 291 #define AM_REG_NVIC_IPR6_PRI_N1_S 8 292 #define AM_REG_NVIC_IPR6_PRI_N1_M 0x0000FF00 293 #define AM_REG_NVIC_IPR6_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) 294 295 // Priority assignment for interrupt vector 24. 296 #define AM_REG_NVIC_IPR6_PRI_N0_S 0 297 #define AM_REG_NVIC_IPR6_PRI_N0_M 0x000000FF 298 #define AM_REG_NVIC_IPR6_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) 299 300 //***************************************************************************** 301 // 302 // NVIC_IPR7 - Interrupt Priority Register 7 303 // 304 //***************************************************************************** 305 // Priority assignment for interrupt vector 31. 306 #define AM_REG_NVIC_IPR7_PRI_N3_S 24 307 #define AM_REG_NVIC_IPR7_PRI_N3_M 0xFF000000 308 #define AM_REG_NVIC_IPR7_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000) 309 310 // Priority assignment for interrupt vector 30. 311 #define AM_REG_NVIC_IPR7_PRI_N2_S 16 312 #define AM_REG_NVIC_IPR7_PRI_N2_M 0x00FF0000 313 #define AM_REG_NVIC_IPR7_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000) 314 315 // Priority assignment for interrupt vector 29. 316 #define AM_REG_NVIC_IPR7_PRI_N1_S 8 317 #define AM_REG_NVIC_IPR7_PRI_N1_M 0x0000FF00 318 #define AM_REG_NVIC_IPR7_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00) 319 320 // Priority assignment for interrupt vector 28. 321 #define AM_REG_NVIC_IPR7_PRI_N0_S 0 322 #define AM_REG_NVIC_IPR7_PRI_N0_M 0x000000FF 323 #define AM_REG_NVIC_IPR7_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF) 324 325 #endif // AM_REG_NVIC_H 326