1 //***************************************************************************** 2 // 3 // am_reg_pdm.h 4 //! @file 5 //! 6 //! @brief Register macros for the PDM module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_PDM_H 45 #define AM_REG_PDM_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_PDM_NUM_MODULES 1 53 #define AM_REG_PDMn(n) \ 54 (REG_PDM_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_PDM_PCFG_O 0x00000000 62 #define AM_REG_PDM_VCFG_O 0x00000004 63 #define AM_REG_PDM_FR_O 0x00000008 64 #define AM_REG_PDM_FRD_O 0x0000000C 65 #define AM_REG_PDM_FLUSH_O 0x00000010 66 #define AM_REG_PDM_FTHR_O 0x00000014 67 #define AM_REG_PDM_INTEN_O 0x00000200 68 #define AM_REG_PDM_INTSTAT_O 0x00000204 69 #define AM_REG_PDM_INTCLR_O 0x00000208 70 #define AM_REG_PDM_INTSET_O 0x0000020C 71 72 //***************************************************************************** 73 // 74 // PDM_INTEN - IO Master Interrupts: Enable 75 // 76 //***************************************************************************** 77 // This is the FIFO underflow interrupt. 78 #define AM_REG_PDM_INTEN_UNDFL_S 2 79 #define AM_REG_PDM_INTEN_UNDFL_M 0x00000004 80 #define AM_REG_PDM_INTEN_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) 81 82 // This is the FIFO overflow interrupt. 83 #define AM_REG_PDM_INTEN_OVF_S 1 84 #define AM_REG_PDM_INTEN_OVF_M 0x00000002 85 #define AM_REG_PDM_INTEN_OVF(n) (((uint32_t)(n) << 1) & 0x00000002) 86 87 // This is the FIFO threshold interrupt. 88 #define AM_REG_PDM_INTEN_THR_S 0 89 #define AM_REG_PDM_INTEN_THR_M 0x00000001 90 #define AM_REG_PDM_INTEN_THR(n) (((uint32_t)(n) << 0) & 0x00000001) 91 92 //***************************************************************************** 93 // 94 // PDM_INTSTAT - IO Master Interrupts: Status 95 // 96 //***************************************************************************** 97 // This is the FIFO underflow interrupt. 98 #define AM_REG_PDM_INTSTAT_UNDFL_S 2 99 #define AM_REG_PDM_INTSTAT_UNDFL_M 0x00000004 100 #define AM_REG_PDM_INTSTAT_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) 101 102 // This is the FIFO overflow interrupt. 103 #define AM_REG_PDM_INTSTAT_OVF_S 1 104 #define AM_REG_PDM_INTSTAT_OVF_M 0x00000002 105 #define AM_REG_PDM_INTSTAT_OVF(n) (((uint32_t)(n) << 1) & 0x00000002) 106 107 // This is the FIFO threshold interrupt. 108 #define AM_REG_PDM_INTSTAT_THR_S 0 109 #define AM_REG_PDM_INTSTAT_THR_M 0x00000001 110 #define AM_REG_PDM_INTSTAT_THR(n) (((uint32_t)(n) << 0) & 0x00000001) 111 112 //***************************************************************************** 113 // 114 // PDM_INTCLR - IO Master Interrupts: Clear 115 // 116 //***************************************************************************** 117 // This is the FIFO underflow interrupt. 118 #define AM_REG_PDM_INTCLR_UNDFL_S 2 119 #define AM_REG_PDM_INTCLR_UNDFL_M 0x00000004 120 #define AM_REG_PDM_INTCLR_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) 121 122 // This is the FIFO overflow interrupt. 123 #define AM_REG_PDM_INTCLR_OVF_S 1 124 #define AM_REG_PDM_INTCLR_OVF_M 0x00000002 125 #define AM_REG_PDM_INTCLR_OVF(n) (((uint32_t)(n) << 1) & 0x00000002) 126 127 // This is the FIFO threshold interrupt. 128 #define AM_REG_PDM_INTCLR_THR_S 0 129 #define AM_REG_PDM_INTCLR_THR_M 0x00000001 130 #define AM_REG_PDM_INTCLR_THR(n) (((uint32_t)(n) << 0) & 0x00000001) 131 132 //***************************************************************************** 133 // 134 // PDM_INTSET - IO Master Interrupts: Set 135 // 136 //***************************************************************************** 137 // This is the FIFO underflow interrupt. 138 #define AM_REG_PDM_INTSET_UNDFL_S 2 139 #define AM_REG_PDM_INTSET_UNDFL_M 0x00000004 140 #define AM_REG_PDM_INTSET_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004) 141 142 // This is the FIFO overflow interrupt. 143 #define AM_REG_PDM_INTSET_OVF_S 1 144 #define AM_REG_PDM_INTSET_OVF_M 0x00000002 145 #define AM_REG_PDM_INTSET_OVF(n) (((uint32_t)(n) << 1) & 0x00000002) 146 147 // This is the FIFO threshold interrupt. 148 #define AM_REG_PDM_INTSET_THR_S 0 149 #define AM_REG_PDM_INTSET_THR_M 0x00000001 150 #define AM_REG_PDM_INTSET_THR(n) (((uint32_t)(n) << 0) & 0x00000001) 151 152 //***************************************************************************** 153 // 154 // PDM_PCFG - PDM Configuration Register 155 // 156 //***************************************************************************** 157 // Left/right channel swap. 158 #define AM_REG_PDM_PCFG_LRSWAP_S 31 159 #define AM_REG_PDM_PCFG_LRSWAP_M 0x80000000 160 #define AM_REG_PDM_PCFG_LRSWAP(n) (((uint32_t)(n) << 31) & 0x80000000) 161 #define AM_REG_PDM_PCFG_LRSWAP_EN 0x80000000 162 #define AM_REG_PDM_PCFG_LRSWAP_NOSWAP 0x00000000 163 164 // Right channel PGA gain. 165 #define AM_REG_PDM_PCFG_PGARIGHT_S 27 166 #define AM_REG_PDM_PCFG_PGARIGHT_M 0x78000000 167 #define AM_REG_PDM_PCFG_PGARIGHT(n) (((uint32_t)(n) << 27) & 0x78000000) 168 #define AM_REG_PDM_PCFG_PGARIGHT_M15DB 0x78000000 169 #define AM_REG_PDM_PCFG_PGARIGHT_M300DB 0x70000000 170 #define AM_REG_PDM_PCFG_PGARIGHT_M45DB 0x68000000 171 #define AM_REG_PDM_PCFG_PGARIGHT_M60DB 0x60000000 172 #define AM_REG_PDM_PCFG_PGARIGHT_M75DB 0x58000000 173 #define AM_REG_PDM_PCFG_PGARIGHT_M90DB 0x50000000 174 #define AM_REG_PDM_PCFG_PGARIGHT_M105DB 0x48000000 175 #define AM_REG_PDM_PCFG_PGARIGHT_M120DB 0x40000000 176 #define AM_REG_PDM_PCFG_PGARIGHT_P105DB 0x38000000 177 #define AM_REG_PDM_PCFG_PGARIGHT_P90DB 0x30000000 178 #define AM_REG_PDM_PCFG_PGARIGHT_P75DB 0x28000000 179 #define AM_REG_PDM_PCFG_PGARIGHT_P60DB 0x20000000 180 #define AM_REG_PDM_PCFG_PGARIGHT_P45DB 0x18000000 181 #define AM_REG_PDM_PCFG_PGARIGHT_P30DB 0x10000000 182 #define AM_REG_PDM_PCFG_PGARIGHT_P15DB 0x08000000 183 #define AM_REG_PDM_PCFG_PGARIGHT_0DB 0x00000000 184 185 // Left channel PGA gain. 186 #define AM_REG_PDM_PCFG_PGALEFT_S 23 187 #define AM_REG_PDM_PCFG_PGALEFT_M 0x07800000 188 #define AM_REG_PDM_PCFG_PGALEFT(n) (((uint32_t)(n) << 23) & 0x07800000) 189 #define AM_REG_PDM_PCFG_PGALEFT_M15DB 0x07800000 190 #define AM_REG_PDM_PCFG_PGALEFT_M300DB 0x07000000 191 #define AM_REG_PDM_PCFG_PGALEFT_M45DB 0x06800000 192 #define AM_REG_PDM_PCFG_PGALEFT_M60DB 0x06000000 193 #define AM_REG_PDM_PCFG_PGALEFT_M75DB 0x05800000 194 #define AM_REG_PDM_PCFG_PGALEFT_M90DB 0x05000000 195 #define AM_REG_PDM_PCFG_PGALEFT_M105DB 0x04800000 196 #define AM_REG_PDM_PCFG_PGALEFT_M120DB 0x04000000 197 #define AM_REG_PDM_PCFG_PGALEFT_P105DB 0x03800000 198 #define AM_REG_PDM_PCFG_PGALEFT_P90DB 0x03000000 199 #define AM_REG_PDM_PCFG_PGALEFT_P75DB 0x02800000 200 #define AM_REG_PDM_PCFG_PGALEFT_P60DB 0x02000000 201 #define AM_REG_PDM_PCFG_PGALEFT_P45DB 0x01800000 202 #define AM_REG_PDM_PCFG_PGALEFT_P30DB 0x01000000 203 #define AM_REG_PDM_PCFG_PGALEFT_P15DB 0x00800000 204 #define AM_REG_PDM_PCFG_PGALEFT_0DB 0x00000000 205 206 // PDM_CLK frequency divisor. 207 #define AM_REG_PDM_PCFG_MCLKDIV_S 17 208 #define AM_REG_PDM_PCFG_MCLKDIV_M 0x00060000 209 #define AM_REG_PDM_PCFG_MCLKDIV(n) (((uint32_t)(n) << 17) & 0x00060000) 210 #define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV4 0x00060000 211 #define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV3 0x00040000 212 #define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV2 0x00020000 213 #define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV1 0x00000000 214 215 // SINC decimation rate. 216 #define AM_REG_PDM_PCFG_SINCRATE_S 10 217 #define AM_REG_PDM_PCFG_SINCRATE_M 0x0001FC00 218 #define AM_REG_PDM_PCFG_SINCRATE(n) (((uint32_t)(n) << 10) & 0x0001FC00) 219 220 // High pass filter control. 221 #define AM_REG_PDM_PCFG_ADCHPD_S 9 222 #define AM_REG_PDM_PCFG_ADCHPD_M 0x00000200 223 #define AM_REG_PDM_PCFG_ADCHPD(n) (((uint32_t)(n) << 9) & 0x00000200) 224 #define AM_REG_PDM_PCFG_ADCHPD_EN 0x00000200 225 #define AM_REG_PDM_PCFG_ADCHPD_DIS 0x00000000 226 227 // High pass filter coefficients. 228 #define AM_REG_PDM_PCFG_HPCUTOFF_S 5 229 #define AM_REG_PDM_PCFG_HPCUTOFF_M 0x000001E0 230 #define AM_REG_PDM_PCFG_HPCUTOFF(n) (((uint32_t)(n) << 5) & 0x000001E0) 231 232 // Number of clocks during gain-setting changes. 233 #define AM_REG_PDM_PCFG_CYCLES_S 2 234 #define AM_REG_PDM_PCFG_CYCLES_M 0x0000001C 235 #define AM_REG_PDM_PCFG_CYCLES(n) (((uint32_t)(n) << 2) & 0x0000001C) 236 237 // Soft mute control. 238 #define AM_REG_PDM_PCFG_SOFTMUTE_S 1 239 #define AM_REG_PDM_PCFG_SOFTMUTE_M 0x00000002 240 #define AM_REG_PDM_PCFG_SOFTMUTE(n) (((uint32_t)(n) << 1) & 0x00000002) 241 #define AM_REG_PDM_PCFG_SOFTMUTE_EN 0x00000002 242 #define AM_REG_PDM_PCFG_SOFTMUTE_DIS 0x00000000 243 244 // Data Streaming Control. 245 #define AM_REG_PDM_PCFG_PDMCORE_S 0 246 #define AM_REG_PDM_PCFG_PDMCORE_M 0x00000001 247 #define AM_REG_PDM_PCFG_PDMCORE(n) (((uint32_t)(n) << 0) & 0x00000001) 248 #define AM_REG_PDM_PCFG_PDMCORE_EN 0x00000001 249 #define AM_REG_PDM_PCFG_PDMCORE_DIS 0x00000000 250 251 //***************************************************************************** 252 // 253 // PDM_VCFG - Voice Configuration Register 254 // 255 //***************************************************************************** 256 // Enable the IO clock. 257 #define AM_REG_PDM_VCFG_IOCLKEN_S 31 258 #define AM_REG_PDM_VCFG_IOCLKEN_M 0x80000000 259 #define AM_REG_PDM_VCFG_IOCLKEN(n) (((uint32_t)(n) << 31) & 0x80000000) 260 #define AM_REG_PDM_VCFG_IOCLKEN_DIS 0x00000000 261 #define AM_REG_PDM_VCFG_IOCLKEN_EN 0x80000000 262 263 // Reset the IP core. 264 #define AM_REG_PDM_VCFG_RSTB_S 30 265 #define AM_REG_PDM_VCFG_RSTB_M 0x40000000 266 #define AM_REG_PDM_VCFG_RSTB(n) (((uint32_t)(n) << 30) & 0x40000000) 267 #define AM_REG_PDM_VCFG_RSTB_RESET 0x00000000 268 #define AM_REG_PDM_VCFG_RSTB_NORM 0x40000000 269 270 // Select the PDM input clock. 271 #define AM_REG_PDM_VCFG_PDMCLKSEL_S 27 272 #define AM_REG_PDM_VCFG_PDMCLKSEL_M 0x38000000 273 #define AM_REG_PDM_VCFG_PDMCLKSEL(n) (((uint32_t)(n) << 27) & 0x38000000) 274 #define AM_REG_PDM_VCFG_PDMCLKSEL_DISABLE 0x00000000 275 #define AM_REG_PDM_VCFG_PDMCLKSEL_12MHz 0x08000000 276 #define AM_REG_PDM_VCFG_PDMCLKSEL_6MHz 0x10000000 277 #define AM_REG_PDM_VCFG_PDMCLKSEL_3MHz 0x18000000 278 #define AM_REG_PDM_VCFG_PDMCLKSEL_1_5MHz 0x20000000 279 #define AM_REG_PDM_VCFG_PDMCLKSEL_750KHz 0x28000000 280 #define AM_REG_PDM_VCFG_PDMCLKSEL_375KHz 0x30000000 281 #define AM_REG_PDM_VCFG_PDMCLKSEL_187KHz 0x38000000 282 283 // Enable the serial clock. 284 #define AM_REG_PDM_VCFG_PDMCLK_S 26 285 #define AM_REG_PDM_VCFG_PDMCLK_M 0x04000000 286 #define AM_REG_PDM_VCFG_PDMCLK(n) (((uint32_t)(n) << 26) & 0x04000000) 287 #define AM_REG_PDM_VCFG_PDMCLK_DIS 0x00000000 288 #define AM_REG_PDM_VCFG_PDMCLK_EN 0x04000000 289 290 // I2S interface enable. 291 #define AM_REG_PDM_VCFG_I2SMODE_S 20 292 #define AM_REG_PDM_VCFG_I2SMODE_M 0x00100000 293 #define AM_REG_PDM_VCFG_I2SMODE(n) (((uint32_t)(n) << 20) & 0x00100000) 294 #define AM_REG_PDM_VCFG_I2SMODE_DIS 0x00000000 295 #define AM_REG_PDM_VCFG_I2SMODE_EN 0x00100000 296 297 // I2S BCLK input inversion. 298 #define AM_REG_PDM_VCFG_BCLKINV_S 19 299 #define AM_REG_PDM_VCFG_BCLKINV_M 0x00080000 300 #define AM_REG_PDM_VCFG_BCLKINV(n) (((uint32_t)(n) << 19) & 0x00080000) 301 #define AM_REG_PDM_VCFG_BCLKINV_INV 0x00000000 302 #define AM_REG_PDM_VCFG_BCLKINV_NORM 0x00080000 303 304 // PDM clock sampling delay. 305 #define AM_REG_PDM_VCFG_DMICKDEL_S 17 306 #define AM_REG_PDM_VCFG_DMICKDEL_M 0x00020000 307 #define AM_REG_PDM_VCFG_DMICKDEL(n) (((uint32_t)(n) << 17) & 0x00020000) 308 #define AM_REG_PDM_VCFG_DMICKDEL_0CYC 0x00000000 309 #define AM_REG_PDM_VCFG_DMICKDEL_1CYC 0x00020000 310 311 // Select PDM input clock source. 312 #define AM_REG_PDM_VCFG_SELAP_S 16 313 #define AM_REG_PDM_VCFG_SELAP_M 0x00010000 314 #define AM_REG_PDM_VCFG_SELAP(n) (((uint32_t)(n) << 16) & 0x00010000) 315 #define AM_REG_PDM_VCFG_SELAP_I2S 0x00010000 316 #define AM_REG_PDM_VCFG_SELAP_INTERNAL 0x00000000 317 318 // PCM data packing enable. 319 #define AM_REG_PDM_VCFG_PCMPACK_S 8 320 #define AM_REG_PDM_VCFG_PCMPACK_M 0x00000100 321 #define AM_REG_PDM_VCFG_PCMPACK(n) (((uint32_t)(n) << 8) & 0x00000100) 322 #define AM_REG_PDM_VCFG_PCMPACK_DIS 0x00000000 323 #define AM_REG_PDM_VCFG_PCMPACK_EN 0x00000100 324 325 // Set PCM channels. 326 #define AM_REG_PDM_VCFG_CHSET_S 3 327 #define AM_REG_PDM_VCFG_CHSET_M 0x00000018 328 #define AM_REG_PDM_VCFG_CHSET(n) (((uint32_t)(n) << 3) & 0x00000018) 329 #define AM_REG_PDM_VCFG_CHSET_DIS 0x00000000 330 #define AM_REG_PDM_VCFG_CHSET_LEFT 0x00000008 331 #define AM_REG_PDM_VCFG_CHSET_RIGHT 0x00000010 332 #define AM_REG_PDM_VCFG_CHSET_STEREO 0x00000018 333 334 //***************************************************************************** 335 // 336 // PDM_FR - Voice Status Register 337 // 338 //***************************************************************************** 339 // Valid 32-bit entries currently in the FIFO. 340 #define AM_REG_PDM_FR_FIFOCNT_S 0 341 #define AM_REG_PDM_FR_FIFOCNT_M 0x000001FF 342 #define AM_REG_PDM_FR_FIFOCNT(n) (((uint32_t)(n) << 0) & 0x000001FF) 343 344 //***************************************************************************** 345 // 346 // PDM_FRD - FIFO Read 347 // 348 //***************************************************************************** 349 // FIFO read data. 350 #define AM_REG_PDM_FRD_FIFOREAD_S 0 351 #define AM_REG_PDM_FRD_FIFOREAD_M 0xFFFFFFFF 352 #define AM_REG_PDM_FRD_FIFOREAD(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 353 354 //***************************************************************************** 355 // 356 // PDM_FLUSH - FIFO Flush 357 // 358 //***************************************************************************** 359 // FIFO FLUSH. 360 #define AM_REG_PDM_FLUSH_FIFOFLUSH_S 0 361 #define AM_REG_PDM_FLUSH_FIFOFLUSH_M 0x00000001 362 #define AM_REG_PDM_FLUSH_FIFOFLUSH(n) (((uint32_t)(n) << 0) & 0x00000001) 363 364 //***************************************************************************** 365 // 366 // PDM_FTHR - FIFO Threshold 367 // 368 //***************************************************************************** 369 // FIFO interrupt threshold. 370 #define AM_REG_PDM_FTHR_FIFOTHR_S 0 371 #define AM_REG_PDM_FTHR_FIFOTHR_M 0x000000FF 372 #define AM_REG_PDM_FTHR_FIFOTHR(n) (((uint32_t)(n) << 0) & 0x000000FF) 373 374 #endif // AM_REG_PDM_H 375