1 //***************************************************************************** 2 // 3 // am_reg_rstgen.h 4 //! @file 5 //! 6 //! @brief Register macros for the RSTGEN module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_RSTGEN_H 45 #define AM_REG_RSTGEN_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_RSTGEN_NUM_MODULES 1 53 #define AM_REG_RSTGENn(n) \ 54 (REG_RSTGEN_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_RSTGEN_CFG_O 0x00000000 62 #define AM_REG_RSTGEN_SWPOI_O 0x00000004 63 #define AM_REG_RSTGEN_SWPOR_O 0x00000008 64 #define AM_REG_RSTGEN_STAT_O 0x0000000C 65 #define AM_REG_RSTGEN_CLRSTAT_O 0x00000010 66 #define AM_REG_RSTGEN_TPIU_RST_O 0x00000014 67 #define AM_REG_RSTGEN_INTEN_O 0x00000200 68 #define AM_REG_RSTGEN_INTSTAT_O 0x00000204 69 #define AM_REG_RSTGEN_INTCLR_O 0x00000208 70 #define AM_REG_RSTGEN_INTSET_O 0x0000020C 71 72 //***************************************************************************** 73 // 74 // RSTGEN_INTEN - Reset Interrupt register: Enable 75 // 76 //***************************************************************************** 77 // Enables an interrupt that triggers when VCC is below BODH level. 78 #define AM_REG_RSTGEN_INTEN_BODH_S 0 79 #define AM_REG_RSTGEN_INTEN_BODH_M 0x00000001 80 #define AM_REG_RSTGEN_INTEN_BODH(n) (((uint32_t)(n) << 0) & 0x00000001) 81 82 //***************************************************************************** 83 // 84 // RSTGEN_INTSTAT - Reset Interrupt register: Status 85 // 86 //***************************************************************************** 87 // Enables an interrupt that triggers when VCC is below BODH level. 88 #define AM_REG_RSTGEN_INTSTAT_BODH_S 0 89 #define AM_REG_RSTGEN_INTSTAT_BODH_M 0x00000001 90 #define AM_REG_RSTGEN_INTSTAT_BODH(n) (((uint32_t)(n) << 0) & 0x00000001) 91 92 //***************************************************************************** 93 // 94 // RSTGEN_INTCLR - Reset Interrupt register: Clear 95 // 96 //***************************************************************************** 97 // Enables an interrupt that triggers when VCC is below BODH level. 98 #define AM_REG_RSTGEN_INTCLR_BODH_S 0 99 #define AM_REG_RSTGEN_INTCLR_BODH_M 0x00000001 100 #define AM_REG_RSTGEN_INTCLR_BODH(n) (((uint32_t)(n) << 0) & 0x00000001) 101 102 //***************************************************************************** 103 // 104 // RSTGEN_INTSET - Reset Interrupt register: Set 105 // 106 //***************************************************************************** 107 // Enables an interrupt that triggers when VCC is below BODH level. 108 #define AM_REG_RSTGEN_INTSET_BODH_S 0 109 #define AM_REG_RSTGEN_INTSET_BODH_M 0x00000001 110 #define AM_REG_RSTGEN_INTSET_BODH(n) (((uint32_t)(n) << 0) & 0x00000001) 111 112 //***************************************************************************** 113 // 114 // RSTGEN_CFG - Configuration Register 115 // 116 //***************************************************************************** 117 // Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured 118 // for WDT reset. 119 #define AM_REG_RSTGEN_CFG_WDREN_S 1 120 #define AM_REG_RSTGEN_CFG_WDREN_M 0x00000002 121 #define AM_REG_RSTGEN_CFG_WDREN(n) (((uint32_t)(n) << 1) & 0x00000002) 122 123 // Brown out high (2.1v) reset enable. 124 #define AM_REG_RSTGEN_CFG_BODHREN_S 0 125 #define AM_REG_RSTGEN_CFG_BODHREN_M 0x00000001 126 #define AM_REG_RSTGEN_CFG_BODHREN(n) (((uint32_t)(n) << 0) & 0x00000001) 127 128 //***************************************************************************** 129 // 130 // RSTGEN_SWPOI - Software POI Reset 131 // 132 //***************************************************************************** 133 // 0x1B generates a software POI reset. 134 #define AM_REG_RSTGEN_SWPOI_SWPOIKEY_S 0 135 #define AM_REG_RSTGEN_SWPOI_SWPOIKEY_M 0x000000FF 136 #define AM_REG_RSTGEN_SWPOI_SWPOIKEY(n) (((uint32_t)(n) << 0) & 0x000000FF) 137 #define AM_REG_RSTGEN_SWPOI_SWPOIKEY_KEYVALUE 0x0000001B 138 139 //***************************************************************************** 140 // 141 // RSTGEN_SWPOR - Software POR Reset 142 // 143 //***************************************************************************** 144 // 0xD4 generates a software POR reset. 145 #define AM_REG_RSTGEN_SWPOR_SWPORKEY_S 0 146 #define AM_REG_RSTGEN_SWPOR_SWPORKEY_M 0x000000FF 147 #define AM_REG_RSTGEN_SWPOR_SWPORKEY(n) (((uint32_t)(n) << 0) & 0x000000FF) 148 #define AM_REG_RSTGEN_SWPOR_SWPORKEY_KEYVALUE 0x000000D4 149 150 //***************************************************************************** 151 // 152 // RSTGEN_STAT - Status Register 153 // 154 //***************************************************************************** 155 // Reset was initiated by a Watchdog Timer Reset. 156 #define AM_REG_RSTGEN_STAT_WDRSTAT_S 6 157 #define AM_REG_RSTGEN_STAT_WDRSTAT_M 0x00000040 158 #define AM_REG_RSTGEN_STAT_WDRSTAT(n) (((uint32_t)(n) << 6) & 0x00000040) 159 160 // Reset was a initiated by Debugger Reset. 161 #define AM_REG_RSTGEN_STAT_DBGRSTAT_S 5 162 #define AM_REG_RSTGEN_STAT_DBGRSTAT_M 0x00000020 163 #define AM_REG_RSTGEN_STAT_DBGRSTAT(n) (((uint32_t)(n) << 5) & 0x00000020) 164 165 // Reset was a initiated by Software POI Reset. 166 #define AM_REG_RSTGEN_STAT_POIRSTAT_S 4 167 #define AM_REG_RSTGEN_STAT_POIRSTAT_M 0x00000010 168 #define AM_REG_RSTGEN_STAT_POIRSTAT(n) (((uint32_t)(n) << 4) & 0x00000010) 169 170 // Reset was a initiated by SW POR or AIRCR Reset. 171 #define AM_REG_RSTGEN_STAT_SWRSTAT_S 3 172 #define AM_REG_RSTGEN_STAT_SWRSTAT_M 0x00000008 173 #define AM_REG_RSTGEN_STAT_SWRSTAT(n) (((uint32_t)(n) << 3) & 0x00000008) 174 175 // Reset was initiated by a Brown-Out Reset. 176 #define AM_REG_RSTGEN_STAT_BORSTAT_S 2 177 #define AM_REG_RSTGEN_STAT_BORSTAT_M 0x00000004 178 #define AM_REG_RSTGEN_STAT_BORSTAT(n) (((uint32_t)(n) << 2) & 0x00000004) 179 180 // Reset was initiated by a Power-On Reset. 181 #define AM_REG_RSTGEN_STAT_PORSTAT_S 1 182 #define AM_REG_RSTGEN_STAT_PORSTAT_M 0x00000002 183 #define AM_REG_RSTGEN_STAT_PORSTAT(n) (((uint32_t)(n) << 1) & 0x00000002) 184 185 // Reset was initiated by an External Reset. 186 #define AM_REG_RSTGEN_STAT_EXRSTAT_S 0 187 #define AM_REG_RSTGEN_STAT_EXRSTAT_M 0x00000001 188 #define AM_REG_RSTGEN_STAT_EXRSTAT(n) (((uint32_t)(n) << 0) & 0x00000001) 189 190 //***************************************************************************** 191 // 192 // RSTGEN_CLRSTAT - Clear the status register 193 // 194 //***************************************************************************** 195 // Writing a 1 to this bit clears all bits in the RST_STAT. 196 #define AM_REG_RSTGEN_CLRSTAT_CLRSTAT_S 0 197 #define AM_REG_RSTGEN_CLRSTAT_CLRSTAT_M 0x00000001 198 #define AM_REG_RSTGEN_CLRSTAT_CLRSTAT(n) (((uint32_t)(n) << 0) & 0x00000001) 199 200 //***************************************************************************** 201 // 202 // RSTGEN_TPIU_RST - TPIU reset 203 // 204 //***************************************************************************** 205 // Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' 206 // to clear the reset. 207 #define AM_REG_RSTGEN_TPIU_RST_TPIURST_S 0 208 #define AM_REG_RSTGEN_TPIU_RST_TPIURST_M 0x00000001 209 #define AM_REG_RSTGEN_TPIU_RST_TPIURST(n) (((uint32_t)(n) << 0) & 0x00000001) 210 211 #endif // AM_REG_RSTGEN_H 212