1 //***************************************************************************** 2 // 3 // am_reg_rtc.h 4 //! @file 5 //! 6 //! @brief Register macros for the RTC module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_RTC_H 45 #define AM_REG_RTC_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_RTC_NUM_MODULES 1 53 #define AM_REG_RTCn(n) \ 54 (REG_RTC_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_RTC_CTRLOW_O 0x00000040 62 #define AM_REG_RTC_CTRUP_O 0x00000044 63 #define AM_REG_RTC_ALMLOW_O 0x00000048 64 #define AM_REG_RTC_ALMUP_O 0x0000004C 65 #define AM_REG_RTC_RTCCTL_O 0x00000050 66 #define AM_REG_RTC_INTEN_O 0x00000100 67 #define AM_REG_RTC_INTSTAT_O 0x00000104 68 #define AM_REG_RTC_INTCLR_O 0x00000108 69 #define AM_REG_RTC_INTSET_O 0x0000010C 70 71 //***************************************************************************** 72 // 73 // RTC_INTEN - RTC Interrupt Register: Enable 74 // 75 //***************************************************************************** 76 // RTC Alarm interrupt 77 #define AM_REG_RTC_INTEN_ALM_S 3 78 #define AM_REG_RTC_INTEN_ALM_M 0x00000008 79 #define AM_REG_RTC_INTEN_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) 80 81 // XT Oscillator Fail interrupt 82 #define AM_REG_RTC_INTEN_OF_S 2 83 #define AM_REG_RTC_INTEN_OF_M 0x00000004 84 #define AM_REG_RTC_INTEN_OF(n) (((uint32_t)(n) << 2) & 0x00000004) 85 86 // Autocalibration Complete interrupt 87 #define AM_REG_RTC_INTEN_ACC_S 1 88 #define AM_REG_RTC_INTEN_ACC_M 0x00000002 89 #define AM_REG_RTC_INTEN_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) 90 91 // Autocalibration Fail interrupt 92 #define AM_REG_RTC_INTEN_ACF_S 0 93 #define AM_REG_RTC_INTEN_ACF_M 0x00000001 94 #define AM_REG_RTC_INTEN_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) 95 96 //***************************************************************************** 97 // 98 // RTC_INTSTAT - RTC Interrupt Register: Status 99 // 100 //***************************************************************************** 101 // RTC Alarm interrupt 102 #define AM_REG_RTC_INTSTAT_ALM_S 3 103 #define AM_REG_RTC_INTSTAT_ALM_M 0x00000008 104 #define AM_REG_RTC_INTSTAT_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) 105 106 // XT Oscillator Fail interrupt 107 #define AM_REG_RTC_INTSTAT_OF_S 2 108 #define AM_REG_RTC_INTSTAT_OF_M 0x00000004 109 #define AM_REG_RTC_INTSTAT_OF(n) (((uint32_t)(n) << 2) & 0x00000004) 110 111 // Autocalibration Complete interrupt 112 #define AM_REG_RTC_INTSTAT_ACC_S 1 113 #define AM_REG_RTC_INTSTAT_ACC_M 0x00000002 114 #define AM_REG_RTC_INTSTAT_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) 115 116 // Autocalibration Fail interrupt 117 #define AM_REG_RTC_INTSTAT_ACF_S 0 118 #define AM_REG_RTC_INTSTAT_ACF_M 0x00000001 119 #define AM_REG_RTC_INTSTAT_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) 120 121 //***************************************************************************** 122 // 123 // RTC_INTCLR - RTC Interrupt Register: Clear 124 // 125 //***************************************************************************** 126 // RTC Alarm interrupt 127 #define AM_REG_RTC_INTCLR_ALM_S 3 128 #define AM_REG_RTC_INTCLR_ALM_M 0x00000008 129 #define AM_REG_RTC_INTCLR_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) 130 131 // XT Oscillator Fail interrupt 132 #define AM_REG_RTC_INTCLR_OF_S 2 133 #define AM_REG_RTC_INTCLR_OF_M 0x00000004 134 #define AM_REG_RTC_INTCLR_OF(n) (((uint32_t)(n) << 2) & 0x00000004) 135 136 // Autocalibration Complete interrupt 137 #define AM_REG_RTC_INTCLR_ACC_S 1 138 #define AM_REG_RTC_INTCLR_ACC_M 0x00000002 139 #define AM_REG_RTC_INTCLR_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) 140 141 // Autocalibration Fail interrupt 142 #define AM_REG_RTC_INTCLR_ACF_S 0 143 #define AM_REG_RTC_INTCLR_ACF_M 0x00000001 144 #define AM_REG_RTC_INTCLR_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) 145 146 //***************************************************************************** 147 // 148 // RTC_INTSET - RTC Interrupt Register: Set 149 // 150 //***************************************************************************** 151 // RTC Alarm interrupt 152 #define AM_REG_RTC_INTSET_ALM_S 3 153 #define AM_REG_RTC_INTSET_ALM_M 0x00000008 154 #define AM_REG_RTC_INTSET_ALM(n) (((uint32_t)(n) << 3) & 0x00000008) 155 156 // XT Oscillator Fail interrupt 157 #define AM_REG_RTC_INTSET_OF_S 2 158 #define AM_REG_RTC_INTSET_OF_M 0x00000004 159 #define AM_REG_RTC_INTSET_OF(n) (((uint32_t)(n) << 2) & 0x00000004) 160 161 // Autocalibration Complete interrupt 162 #define AM_REG_RTC_INTSET_ACC_S 1 163 #define AM_REG_RTC_INTSET_ACC_M 0x00000002 164 #define AM_REG_RTC_INTSET_ACC(n) (((uint32_t)(n) << 1) & 0x00000002) 165 166 // Autocalibration Fail interrupt 167 #define AM_REG_RTC_INTSET_ACF_S 0 168 #define AM_REG_RTC_INTSET_ACF_M 0x00000001 169 #define AM_REG_RTC_INTSET_ACF(n) (((uint32_t)(n) << 0) & 0x00000001) 170 171 //***************************************************************************** 172 // 173 // RTC_CTRLOW - RTC Counters Lower 174 // 175 //***************************************************************************** 176 // Hours Counter 177 #define AM_REG_RTC_CTRLOW_CTRHR_S 24 178 #define AM_REG_RTC_CTRLOW_CTRHR_M 0x3F000000 179 #define AM_REG_RTC_CTRLOW_CTRHR(n) (((uint32_t)(n) << 24) & 0x3F000000) 180 181 // Minutes Counter 182 #define AM_REG_RTC_CTRLOW_CTRMIN_S 16 183 #define AM_REG_RTC_CTRLOW_CTRMIN_M 0x007F0000 184 #define AM_REG_RTC_CTRLOW_CTRMIN(n) (((uint32_t)(n) << 16) & 0x007F0000) 185 186 // Seconds Counter 187 #define AM_REG_RTC_CTRLOW_CTRSEC_S 8 188 #define AM_REG_RTC_CTRLOW_CTRSEC_M 0x00007F00 189 #define AM_REG_RTC_CTRLOW_CTRSEC(n) (((uint32_t)(n) << 8) & 0x00007F00) 190 191 // 100ths of a second Counter 192 #define AM_REG_RTC_CTRLOW_CTR100_S 0 193 #define AM_REG_RTC_CTRLOW_CTR100_M 0x000000FF 194 #define AM_REG_RTC_CTRLOW_CTR100(n) (((uint32_t)(n) << 0) & 0x000000FF) 195 196 //***************************************************************************** 197 // 198 // RTC_CTRUP - RTC Counters Upper 199 // 200 //***************************************************************************** 201 // Counter read error status 202 #define AM_REG_RTC_CTRUP_CTERR_S 31 203 #define AM_REG_RTC_CTRUP_CTERR_M 0x80000000 204 #define AM_REG_RTC_CTRUP_CTERR(n) (((uint32_t)(n) << 31) & 0x80000000) 205 #define AM_REG_RTC_CTRUP_CTERR_NOERR 0x00000000 206 #define AM_REG_RTC_CTRUP_CTERR_RDERR 0x80000000 207 208 // Century enable 209 #define AM_REG_RTC_CTRUP_CEB_S 28 210 #define AM_REG_RTC_CTRUP_CEB_M 0x10000000 211 #define AM_REG_RTC_CTRUP_CEB(n) (((uint32_t)(n) << 28) & 0x10000000) 212 #define AM_REG_RTC_CTRUP_CEB_DIS 0x00000000 213 #define AM_REG_RTC_CTRUP_CEB_EN 0x10000000 214 215 // Century 216 #define AM_REG_RTC_CTRUP_CB_S 27 217 #define AM_REG_RTC_CTRUP_CB_M 0x08000000 218 #define AM_REG_RTC_CTRUP_CB(n) (((uint32_t)(n) << 27) & 0x08000000) 219 #define AM_REG_RTC_CTRUP_CB_2000 0x00000000 220 #define AM_REG_RTC_CTRUP_CB_1900_2100 0x08000000 221 222 // Weekdays Counter 223 #define AM_REG_RTC_CTRUP_CTRWKDY_S 24 224 #define AM_REG_RTC_CTRUP_CTRWKDY_M 0x07000000 225 #define AM_REG_RTC_CTRUP_CTRWKDY(n) (((uint32_t)(n) << 24) & 0x07000000) 226 227 // Years Counter 228 #define AM_REG_RTC_CTRUP_CTRYR_S 16 229 #define AM_REG_RTC_CTRUP_CTRYR_M 0x00FF0000 230 #define AM_REG_RTC_CTRUP_CTRYR(n) (((uint32_t)(n) << 16) & 0x00FF0000) 231 232 // Months Counter 233 #define AM_REG_RTC_CTRUP_CTRMO_S 8 234 #define AM_REG_RTC_CTRUP_CTRMO_M 0x00001F00 235 #define AM_REG_RTC_CTRUP_CTRMO(n) (((uint32_t)(n) << 8) & 0x00001F00) 236 237 // Date Counter 238 #define AM_REG_RTC_CTRUP_CTRDATE_S 0 239 #define AM_REG_RTC_CTRUP_CTRDATE_M 0x0000003F 240 #define AM_REG_RTC_CTRUP_CTRDATE(n) (((uint32_t)(n) << 0) & 0x0000003F) 241 242 //***************************************************************************** 243 // 244 // RTC_ALMLOW - RTC Alarms Lower 245 // 246 //***************************************************************************** 247 // Hours Alarm 248 #define AM_REG_RTC_ALMLOW_ALMHR_S 24 249 #define AM_REG_RTC_ALMLOW_ALMHR_M 0x3F000000 250 #define AM_REG_RTC_ALMLOW_ALMHR(n) (((uint32_t)(n) << 24) & 0x3F000000) 251 252 // Minutes Alarm 253 #define AM_REG_RTC_ALMLOW_ALMMIN_S 16 254 #define AM_REG_RTC_ALMLOW_ALMMIN_M 0x007F0000 255 #define AM_REG_RTC_ALMLOW_ALMMIN(n) (((uint32_t)(n) << 16) & 0x007F0000) 256 257 // Seconds Alarm 258 #define AM_REG_RTC_ALMLOW_ALMSEC_S 8 259 #define AM_REG_RTC_ALMLOW_ALMSEC_M 0x00007F00 260 #define AM_REG_RTC_ALMLOW_ALMSEC(n) (((uint32_t)(n) << 8) & 0x00007F00) 261 262 // 100ths of a second Alarm 263 #define AM_REG_RTC_ALMLOW_ALM100_S 0 264 #define AM_REG_RTC_ALMLOW_ALM100_M 0x000000FF 265 #define AM_REG_RTC_ALMLOW_ALM100(n) (((uint32_t)(n) << 0) & 0x000000FF) 266 267 //***************************************************************************** 268 // 269 // RTC_ALMUP - RTC Alarms Upper 270 // 271 //***************************************************************************** 272 // Weekdays Alarm 273 #define AM_REG_RTC_ALMUP_ALMWKDY_S 16 274 #define AM_REG_RTC_ALMUP_ALMWKDY_M 0x00070000 275 #define AM_REG_RTC_ALMUP_ALMWKDY(n) (((uint32_t)(n) << 16) & 0x00070000) 276 277 // Months Alarm 278 #define AM_REG_RTC_ALMUP_ALMMO_S 8 279 #define AM_REG_RTC_ALMUP_ALMMO_M 0x00001F00 280 #define AM_REG_RTC_ALMUP_ALMMO(n) (((uint32_t)(n) << 8) & 0x00001F00) 281 282 // Date Alarm 283 #define AM_REG_RTC_ALMUP_ALMDATE_S 0 284 #define AM_REG_RTC_ALMUP_ALMDATE_M 0x0000003F 285 #define AM_REG_RTC_ALMUP_ALMDATE(n) (((uint32_t)(n) << 0) & 0x0000003F) 286 287 //***************************************************************************** 288 // 289 // RTC_RTCCTL - RTC Control Register 290 // 291 //***************************************************************************** 292 // Hours Counter mode 293 #define AM_REG_RTC_RTCCTL_HR1224_S 5 294 #define AM_REG_RTC_RTCCTL_HR1224_M 0x00000020 295 #define AM_REG_RTC_RTCCTL_HR1224(n) (((uint32_t)(n) << 5) & 0x00000020) 296 #define AM_REG_RTC_RTCCTL_HR1224_24HR 0x00000000 297 #define AM_REG_RTC_RTCCTL_HR1224_12HR 0x00000020 298 299 // RTC input clock control 300 #define AM_REG_RTC_RTCCTL_RSTOP_S 4 301 #define AM_REG_RTC_RTCCTL_RSTOP_M 0x00000010 302 #define AM_REG_RTC_RTCCTL_RSTOP(n) (((uint32_t)(n) << 4) & 0x00000010) 303 #define AM_REG_RTC_RTCCTL_RSTOP_RUN 0x00000000 304 #define AM_REG_RTC_RTCCTL_RSTOP_STOP 0x00000010 305 306 // Alarm repeat interval 307 #define AM_REG_RTC_RTCCTL_RPT_S 1 308 #define AM_REG_RTC_RTCCTL_RPT_M 0x0000000E 309 #define AM_REG_RTC_RTCCTL_RPT(n) (((uint32_t)(n) << 1) & 0x0000000E) 310 #define AM_REG_RTC_RTCCTL_RPT_DIS 0x00000000 311 #define AM_REG_RTC_RTCCTL_RPT_YEAR 0x00000002 312 #define AM_REG_RTC_RTCCTL_RPT_MONTH 0x00000004 313 #define AM_REG_RTC_RTCCTL_RPT_WEEK 0x00000006 314 #define AM_REG_RTC_RTCCTL_RPT_DAY 0x00000008 315 #define AM_REG_RTC_RTCCTL_RPT_HR 0x0000000A 316 #define AM_REG_RTC_RTCCTL_RPT_MIN 0x0000000C 317 #define AM_REG_RTC_RTCCTL_RPT_SEC 0x0000000E 318 319 // Counter write control 320 #define AM_REG_RTC_RTCCTL_WRTC_S 0 321 #define AM_REG_RTC_RTCCTL_WRTC_M 0x00000001 322 #define AM_REG_RTC_RTCCTL_WRTC(n) (((uint32_t)(n) << 0) & 0x00000001) 323 #define AM_REG_RTC_RTCCTL_WRTC_DIS 0x00000000 324 #define AM_REG_RTC_RTCCTL_WRTC_EN 0x00000001 325 326 #endif // AM_REG_RTC_H 327