1 //***************************************************************************** 2 // 3 // am_reg_tpiu.h 4 //! @file 5 //! 6 //! @brief Register macros for the TPIU module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_TPIU_H 45 #define AM_REG_TPIU_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_TPIU_NUM_MODULES 1 53 #define AM_REG_TPIUn(n) \ 54 (REG_TPIU_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_TPIU_SSPSR_O 0xE0040000 62 #define AM_REG_TPIU_CSPSR_O 0xE0040004 63 #define AM_REG_TPIU_ACPR_O 0xE0040010 64 #define AM_REG_TPIU_SPPR_O 0xE00400F0 65 #define AM_REG_TPIU_FFCR_O 0xE0040304 66 #define AM_REG_TPIU_ITCTRL_O 0xE0040F00 67 #define AM_REG_TPIU_TYPE_O 0xE0040FC8 68 69 //***************************************************************************** 70 // 71 // TPIU_SSPSR - Supported Parallel Port Sizes. 72 // 73 //***************************************************************************** 74 // Parallel Port Width 1 supported 75 #define AM_REG_TPIU_SSPSR_SWIDTH0_S 0 76 #define AM_REG_TPIU_SSPSR_SWIDTH0_M 0x00000001 77 #define AM_REG_TPIU_SSPSR_SWIDTH0(n) (((uint32_t)(n) << 0) & 0x00000001) 78 79 //***************************************************************************** 80 // 81 // TPIU_CSPSR - Current Parallel Port Size. 82 // 83 //***************************************************************************** 84 // One-hot representation of the current port width. 85 #define AM_REG_TPIU_CSPSR_CWIDTH_S 0 86 #define AM_REG_TPIU_CSPSR_CWIDTH_M 0xFFFFFFFF 87 #define AM_REG_TPIU_CSPSR_CWIDTH(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 88 #define AM_REG_TPIU_CSPSR_CWIDTH_1BIT 0x00000001 89 90 //***************************************************************************** 91 // 92 // TPIU_ACPR - Asynchronous Clock Prescaler. 93 // 94 //***************************************************************************** 95 // Prescaler value for the baudrate of SWO. 96 #define AM_REG_TPIU_ACPR_SWOSCALER_S 0 97 #define AM_REG_TPIU_ACPR_SWOSCALER_M 0x0000FFFF 98 #define AM_REG_TPIU_ACPR_SWOSCALER(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 99 #define AM_REG_TPIU_ACPR_SWOSCALER_115200 0x00000033 100 101 //***************************************************************************** 102 // 103 // TPIU_SPPR - Selected Pin Protocol. 104 // 105 //***************************************************************************** 106 // Selects the protocol used for trace output. 107 #define AM_REG_TPIU_SPPR_TXMODE_S 0 108 #define AM_REG_TPIU_SPPR_TXMODE_M 0x00000003 109 #define AM_REG_TPIU_SPPR_TXMODE(n) (((uint32_t)(n) << 0) & 0x00000003) 110 #define AM_REG_TPIU_SPPR_TXMODE_PARALLEL 0x00000000 111 #define AM_REG_TPIU_SPPR_TXMODE_MANCHESTER 0x00000001 112 #define AM_REG_TPIU_SPPR_TXMODE_NRZ 0x00000002 113 #define AM_REG_TPIU_SPPR_TXMODE_UART 0x00000002 114 115 //***************************************************************************** 116 // 117 // TPIU_FFCR - Formatter and Flush Control Register. 118 // 119 //***************************************************************************** 120 // Enable continuous formatting. 121 #define AM_REG_TPIU_FFCR_ENFCONT_S 1 122 #define AM_REG_TPIU_FFCR_ENFCONT_M 0x00000002 123 #define AM_REG_TPIU_FFCR_ENFCONT(n) (((uint32_t)(n) << 1) & 0x00000002) 124 125 //***************************************************************************** 126 // 127 // TPIU_ITCTRL - Specifies normal or integration mode for the TPIU. 128 // 129 //***************************************************************************** 130 // Specifies the current mode for the TPIU. 131 #define AM_REG_TPIU_ITCTRL_MODE_S 0 132 #define AM_REG_TPIU_ITCTRL_MODE_M 0x00000003 133 #define AM_REG_TPIU_ITCTRL_MODE(n) (((uint32_t)(n) << 0) & 0x00000003) 134 #define AM_REG_TPIU_ITCTRL_MODE_NORMAL 0x00000000 135 #define AM_REG_TPIU_ITCTRL_MODE_TEST 0x00000001 136 #define AM_REG_TPIU_ITCTRL_MODE_DATA_TEST 0x00000002 137 138 //***************************************************************************** 139 // 140 // TPIU_TYPE - TPIU Type. 141 // 142 //***************************************************************************** 143 // 1 Indicates UART/NRZ support. 144 #define AM_REG_TPIU_TYPE_NRZVALID_S 11 145 #define AM_REG_TPIU_TYPE_NRZVALID_M 0x00000800 146 #define AM_REG_TPIU_TYPE_NRZVALID(n) (((uint32_t)(n) << 11) & 0x00000800) 147 148 // 1 Indicates Manchester support. 149 #define AM_REG_TPIU_TYPE_MANCVALID_S 10 150 #define AM_REG_TPIU_TYPE_MANCVALID_M 0x00000400 151 #define AM_REG_TPIU_TYPE_MANCVALID(n) (((uint32_t)(n) << 10) & 0x00000400) 152 153 // 0 Indicates Parallel Trace support. 154 #define AM_REG_TPIU_TYPE_PTINVALID_S 9 155 #define AM_REG_TPIU_TYPE_PTINVALID_M 0x00000200 156 #define AM_REG_TPIU_TYPE_PTINVALID(n) (((uint32_t)(n) << 9) & 0x00000200) 157 158 // FIFO Size reported as a power of two. For instance, 0x3 indicates a FIFO size 159 // of 8 bytes. 160 #define AM_REG_TPIU_TYPE_FIFOSZ_S 6 161 #define AM_REG_TPIU_TYPE_FIFOSZ_M 0x000001C0 162 #define AM_REG_TPIU_TYPE_FIFOSZ(n) (((uint32_t)(n) << 6) & 0x000001C0) 163 164 #endif // AM_REG_TPIU_H 165