1 //***************************************************************************** 2 // 3 // am_reg_uart.h 4 //! @file 5 //! 6 //! @brief Register macros for the UART module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_UART_H 45 #define AM_REG_UART_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (2 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_UART_NUM_MODULES 2 53 #define AM_REG_UARTn(n) \ 54 (REG_UART_BASEADDR + 0x00001000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_UART_DR_O 0x00000000 62 #define AM_REG_UART_RSR_O 0x00000004 63 #define AM_REG_UART_FR_O 0x00000018 64 #define AM_REG_UART_ILPR_O 0x00000020 65 #define AM_REG_UART_IBRD_O 0x00000024 66 #define AM_REG_UART_FBRD_O 0x00000028 67 #define AM_REG_UART_LCRH_O 0x0000002C 68 #define AM_REG_UART_CR_O 0x00000030 69 #define AM_REG_UART_IFLS_O 0x00000034 70 #define AM_REG_UART_IER_O 0x00000038 71 #define AM_REG_UART_IES_O 0x0000003C 72 #define AM_REG_UART_MIS_O 0x00000040 73 #define AM_REG_UART_IEC_O 0x00000044 74 75 //***************************************************************************** 76 // 77 // UART_DR - UART Data Register 78 // 79 //***************************************************************************** 80 // This is the overrun error indicator. 81 #define AM_REG_UART_DR_OEDATA_S 11 82 #define AM_REG_UART_DR_OEDATA_M 0x00000800 83 #define AM_REG_UART_DR_OEDATA(n) (((uint32_t)(n) << 11) & 0x00000800) 84 #define AM_REG_UART_DR_OEDATA_NOERR 0x00000000 85 #define AM_REG_UART_DR_OEDATA_ERR 0x00000800 86 87 // This is the break error indicator. 88 #define AM_REG_UART_DR_BEDATA_S 10 89 #define AM_REG_UART_DR_BEDATA_M 0x00000400 90 #define AM_REG_UART_DR_BEDATA(n) (((uint32_t)(n) << 10) & 0x00000400) 91 #define AM_REG_UART_DR_BEDATA_NOERR 0x00000000 92 #define AM_REG_UART_DR_BEDATA_ERR 0x00000400 93 94 // This is the parity error indicator. 95 #define AM_REG_UART_DR_PEDATA_S 9 96 #define AM_REG_UART_DR_PEDATA_M 0x00000200 97 #define AM_REG_UART_DR_PEDATA(n) (((uint32_t)(n) << 9) & 0x00000200) 98 #define AM_REG_UART_DR_PEDATA_NOERR 0x00000000 99 #define AM_REG_UART_DR_PEDATA_ERR 0x00000200 100 101 // This is the framing error indicator. 102 #define AM_REG_UART_DR_FEDATA_S 8 103 #define AM_REG_UART_DR_FEDATA_M 0x00000100 104 #define AM_REG_UART_DR_FEDATA(n) (((uint32_t)(n) << 8) & 0x00000100) 105 #define AM_REG_UART_DR_FEDATA_NOERR 0x00000000 106 #define AM_REG_UART_DR_FEDATA_ERR 0x00000100 107 108 // This is the UART data port. 109 #define AM_REG_UART_DR_DATA_S 0 110 #define AM_REG_UART_DR_DATA_M 0x000000FF 111 #define AM_REG_UART_DR_DATA(n) (((uint32_t)(n) << 0) & 0x000000FF) 112 113 //***************************************************************************** 114 // 115 // UART_RSR - UART Status Register 116 // 117 //***************************************************************************** 118 // This is the overrun error indicator. 119 #define AM_REG_UART_RSR_OESTAT_S 3 120 #define AM_REG_UART_RSR_OESTAT_M 0x00000008 121 #define AM_REG_UART_RSR_OESTAT(n) (((uint32_t)(n) << 3) & 0x00000008) 122 #define AM_REG_UART_RSR_OESTAT_NOERR 0x00000000 123 #define AM_REG_UART_RSR_OESTAT_ERR 0x00000008 124 125 // This is the break error indicator. 126 #define AM_REG_UART_RSR_BESTAT_S 2 127 #define AM_REG_UART_RSR_BESTAT_M 0x00000004 128 #define AM_REG_UART_RSR_BESTAT(n) (((uint32_t)(n) << 2) & 0x00000004) 129 #define AM_REG_UART_RSR_BESTAT_NOERR 0x00000000 130 #define AM_REG_UART_RSR_BESTAT_ERR 0x00000004 131 132 // This is the parity error indicator. 133 #define AM_REG_UART_RSR_PESTAT_S 1 134 #define AM_REG_UART_RSR_PESTAT_M 0x00000002 135 #define AM_REG_UART_RSR_PESTAT(n) (((uint32_t)(n) << 1) & 0x00000002) 136 #define AM_REG_UART_RSR_PESTAT_NOERR 0x00000000 137 #define AM_REG_UART_RSR_PESTAT_ERR 0x00000002 138 139 // This is the framing error indicator. 140 #define AM_REG_UART_RSR_FESTAT_S 0 141 #define AM_REG_UART_RSR_FESTAT_M 0x00000001 142 #define AM_REG_UART_RSR_FESTAT(n) (((uint32_t)(n) << 0) & 0x00000001) 143 #define AM_REG_UART_RSR_FESTAT_NOERR 0x00000000 144 #define AM_REG_UART_RSR_FESTAT_ERR 0x00000001 145 146 //***************************************************************************** 147 // 148 // UART_FR - Flag Register 149 // 150 //***************************************************************************** 151 // This bit holds the transmit BUSY indicator. 152 #define AM_REG_UART_FR_TXBUSY_S 8 153 #define AM_REG_UART_FR_TXBUSY_M 0x00000100 154 #define AM_REG_UART_FR_TXBUSY(n) (((uint32_t)(n) << 8) & 0x00000100) 155 156 // This bit holds the transmit FIFO empty indicator. 157 #define AM_REG_UART_FR_TXFE_S 7 158 #define AM_REG_UART_FR_TXFE_M 0x00000080 159 #define AM_REG_UART_FR_TXFE(n) (((uint32_t)(n) << 7) & 0x00000080) 160 #define AM_REG_UART_FR_TXFE_XMTFIFO_EMPTY 0x00000080 161 162 // This bit holds the receive FIFO full indicator. 163 #define AM_REG_UART_FR_RXFF_S 6 164 #define AM_REG_UART_FR_RXFF_M 0x00000040 165 #define AM_REG_UART_FR_RXFF(n) (((uint32_t)(n) << 6) & 0x00000040) 166 #define AM_REG_UART_FR_RXFF_RCVFIFO_FULL 0x00000040 167 168 // This bit holds the transmit FIFO full indicator. 169 #define AM_REG_UART_FR_TXFF_S 5 170 #define AM_REG_UART_FR_TXFF_M 0x00000020 171 #define AM_REG_UART_FR_TXFF(n) (((uint32_t)(n) << 5) & 0x00000020) 172 #define AM_REG_UART_FR_TXFF_XMTFIFO_FULL 0x00000020 173 174 // This bit holds the receive FIFO empty indicator. 175 #define AM_REG_UART_FR_RXFE_S 4 176 #define AM_REG_UART_FR_RXFE_M 0x00000010 177 #define AM_REG_UART_FR_RXFE(n) (((uint32_t)(n) << 4) & 0x00000010) 178 #define AM_REG_UART_FR_RXFE_RCVFIFO_EMPTY 0x00000010 179 180 // This bit holds the busy indicator. 181 #define AM_REG_UART_FR_BUSY_S 3 182 #define AM_REG_UART_FR_BUSY_M 0x00000008 183 #define AM_REG_UART_FR_BUSY(n) (((uint32_t)(n) << 3) & 0x00000008) 184 #define AM_REG_UART_FR_BUSY_BUSY 0x00000008 185 186 // This bit holds the data carrier detect indicator. 187 #define AM_REG_UART_FR_DCD_S 2 188 #define AM_REG_UART_FR_DCD_M 0x00000004 189 #define AM_REG_UART_FR_DCD(n) (((uint32_t)(n) << 2) & 0x00000004) 190 #define AM_REG_UART_FR_DCD_DETECTED 0x00000004 191 192 // This bit holds the data set ready indicator. 193 #define AM_REG_UART_FR_DSR_S 1 194 #define AM_REG_UART_FR_DSR_M 0x00000002 195 #define AM_REG_UART_FR_DSR(n) (((uint32_t)(n) << 1) & 0x00000002) 196 #define AM_REG_UART_FR_DSR_READY 0x00000002 197 198 // This bit holds the clear to send indicator. 199 #define AM_REG_UART_FR_CTS_S 0 200 #define AM_REG_UART_FR_CTS_M 0x00000001 201 #define AM_REG_UART_FR_CTS(n) (((uint32_t)(n) << 0) & 0x00000001) 202 #define AM_REG_UART_FR_CTS_CLEARTOSEND 0x00000001 203 204 //***************************************************************************** 205 // 206 // UART_ILPR - IrDA Counter 207 // 208 //***************************************************************************** 209 // These bits hold the IrDA counter divisor. 210 #define AM_REG_UART_ILPR_ILPDVSR_S 0 211 #define AM_REG_UART_ILPR_ILPDVSR_M 0x000000FF 212 #define AM_REG_UART_ILPR_ILPDVSR(n) (((uint32_t)(n) << 0) & 0x000000FF) 213 214 //***************************************************************************** 215 // 216 // UART_IBRD - Integer Baud Rate Divisor 217 // 218 //***************************************************************************** 219 // These bits hold the baud integer divisor. 220 #define AM_REG_UART_IBRD_DIVINT_S 0 221 #define AM_REG_UART_IBRD_DIVINT_M 0x0000FFFF 222 #define AM_REG_UART_IBRD_DIVINT(n) (((uint32_t)(n) << 0) & 0x0000FFFF) 223 224 //***************************************************************************** 225 // 226 // UART_FBRD - Fractional Baud Rate Divisor 227 // 228 //***************************************************************************** 229 // These bits hold the baud fractional divisor. 230 #define AM_REG_UART_FBRD_DIVFRAC_S 0 231 #define AM_REG_UART_FBRD_DIVFRAC_M 0x0000003F 232 #define AM_REG_UART_FBRD_DIVFRAC(n) (((uint32_t)(n) << 0) & 0x0000003F) 233 234 //***************************************************************************** 235 // 236 // UART_LCRH - Line Control High 237 // 238 //***************************************************************************** 239 // This bit holds the stick parity select. 240 #define AM_REG_UART_LCRH_SPS_S 7 241 #define AM_REG_UART_LCRH_SPS_M 0x00000080 242 #define AM_REG_UART_LCRH_SPS(n) (((uint32_t)(n) << 7) & 0x00000080) 243 244 // These bits hold the write length. 245 #define AM_REG_UART_LCRH_WLEN_S 5 246 #define AM_REG_UART_LCRH_WLEN_M 0x00000060 247 #define AM_REG_UART_LCRH_WLEN(n) (((uint32_t)(n) << 5) & 0x00000060) 248 249 // This bit holds the FIFO enable. 250 #define AM_REG_UART_LCRH_FEN_S 4 251 #define AM_REG_UART_LCRH_FEN_M 0x00000010 252 #define AM_REG_UART_LCRH_FEN(n) (((uint32_t)(n) << 4) & 0x00000010) 253 254 // This bit holds the two stop bits select. 255 #define AM_REG_UART_LCRH_STP2_S 3 256 #define AM_REG_UART_LCRH_STP2_M 0x00000008 257 #define AM_REG_UART_LCRH_STP2(n) (((uint32_t)(n) << 3) & 0x00000008) 258 259 // This bit holds the even parity select. 260 #define AM_REG_UART_LCRH_EPS_S 2 261 #define AM_REG_UART_LCRH_EPS_M 0x00000004 262 #define AM_REG_UART_LCRH_EPS(n) (((uint32_t)(n) << 2) & 0x00000004) 263 264 // This bit holds the parity enable. 265 #define AM_REG_UART_LCRH_PEN_S 1 266 #define AM_REG_UART_LCRH_PEN_M 0x00000002 267 #define AM_REG_UART_LCRH_PEN(n) (((uint32_t)(n) << 1) & 0x00000002) 268 269 // This bit holds the break set. 270 #define AM_REG_UART_LCRH_BRK_S 0 271 #define AM_REG_UART_LCRH_BRK_M 0x00000001 272 #define AM_REG_UART_LCRH_BRK(n) (((uint32_t)(n) << 0) & 0x00000001) 273 274 //***************************************************************************** 275 // 276 // UART_CR - Control Register 277 // 278 //***************************************************************************** 279 // This bit enables CTS hardware flow control. 280 #define AM_REG_UART_CR_CTSEN_S 15 281 #define AM_REG_UART_CR_CTSEN_M 0x00008000 282 #define AM_REG_UART_CR_CTSEN(n) (((uint32_t)(n) << 15) & 0x00008000) 283 284 // This bit enables RTS hardware flow control. 285 #define AM_REG_UART_CR_RTSEN_S 14 286 #define AM_REG_UART_CR_RTSEN_M 0x00004000 287 #define AM_REG_UART_CR_RTSEN(n) (((uint32_t)(n) << 14) & 0x00004000) 288 289 // This bit holds modem Out2. 290 #define AM_REG_UART_CR_OUT2_S 13 291 #define AM_REG_UART_CR_OUT2_M 0x00002000 292 #define AM_REG_UART_CR_OUT2(n) (((uint32_t)(n) << 13) & 0x00002000) 293 294 // This bit holds modem Out1. 295 #define AM_REG_UART_CR_OUT1_S 12 296 #define AM_REG_UART_CR_OUT1_M 0x00001000 297 #define AM_REG_UART_CR_OUT1(n) (((uint32_t)(n) << 12) & 0x00001000) 298 299 // This bit enables request to send. 300 #define AM_REG_UART_CR_RTS_S 11 301 #define AM_REG_UART_CR_RTS_M 0x00000800 302 #define AM_REG_UART_CR_RTS(n) (((uint32_t)(n) << 11) & 0x00000800) 303 304 // This bit enables data transmit ready. 305 #define AM_REG_UART_CR_DTR_S 10 306 #define AM_REG_UART_CR_DTR_M 0x00000400 307 #define AM_REG_UART_CR_DTR(n) (((uint32_t)(n) << 10) & 0x00000400) 308 309 // This bit is the receive enable. 310 #define AM_REG_UART_CR_RXE_S 9 311 #define AM_REG_UART_CR_RXE_M 0x00000200 312 #define AM_REG_UART_CR_RXE(n) (((uint32_t)(n) << 9) & 0x00000200) 313 314 // This bit is the transmit enable. 315 #define AM_REG_UART_CR_TXE_S 8 316 #define AM_REG_UART_CR_TXE_M 0x00000100 317 #define AM_REG_UART_CR_TXE(n) (((uint32_t)(n) << 8) & 0x00000100) 318 319 // This bit is the loopback enable. 320 #define AM_REG_UART_CR_LBE_S 7 321 #define AM_REG_UART_CR_LBE_M 0x00000080 322 #define AM_REG_UART_CR_LBE(n) (((uint32_t)(n) << 7) & 0x00000080) 323 324 // This bitfield is the UART clock select. 325 #define AM_REG_UART_CR_CLKSEL_S 4 326 #define AM_REG_UART_CR_CLKSEL_M 0x00000070 327 #define AM_REG_UART_CR_CLKSEL(n) (((uint32_t)(n) << 4) & 0x00000070) 328 #define AM_REG_UART_CR_CLKSEL_NOCLK 0x00000000 329 #define AM_REG_UART_CR_CLKSEL_24MHZ 0x00000010 330 #define AM_REG_UART_CR_CLKSEL_12MHZ 0x00000020 331 #define AM_REG_UART_CR_CLKSEL_6MHZ 0x00000030 332 #define AM_REG_UART_CR_CLKSEL_3MHZ 0x00000040 333 #define AM_REG_UART_CR_CLKSEL_RSVD5 0x00000050 334 #define AM_REG_UART_CR_CLKSEL_RSVD6 0x00000060 335 #define AM_REG_UART_CR_CLKSEL_RSVD7 0x00000070 336 337 // This bit is the UART clock enable. 338 #define AM_REG_UART_CR_CLKEN_S 3 339 #define AM_REG_UART_CR_CLKEN_M 0x00000008 340 #define AM_REG_UART_CR_CLKEN(n) (((uint32_t)(n) << 3) & 0x00000008) 341 342 // This bit is the SIR low power select. 343 #define AM_REG_UART_CR_SIRLP_S 2 344 #define AM_REG_UART_CR_SIRLP_M 0x00000004 345 #define AM_REG_UART_CR_SIRLP(n) (((uint32_t)(n) << 2) & 0x00000004) 346 347 // This bit is the SIR ENDEC enable. 348 #define AM_REG_UART_CR_SIREN_S 1 349 #define AM_REG_UART_CR_SIREN_M 0x00000002 350 #define AM_REG_UART_CR_SIREN(n) (((uint32_t)(n) << 1) & 0x00000002) 351 352 // This bit is the UART enable. 353 #define AM_REG_UART_CR_UARTEN_S 0 354 #define AM_REG_UART_CR_UARTEN_M 0x00000001 355 #define AM_REG_UART_CR_UARTEN(n) (((uint32_t)(n) << 0) & 0x00000001) 356 357 //***************************************************************************** 358 // 359 // UART_IFLS - FIFO Interrupt Level Select 360 // 361 //***************************************************************************** 362 // These bits hold the receive FIFO interrupt level. 363 #define AM_REG_UART_IFLS_RXIFLSEL_S 3 364 #define AM_REG_UART_IFLS_RXIFLSEL_M 0x00000038 365 #define AM_REG_UART_IFLS_RXIFLSEL(n) (((uint32_t)(n) << 3) & 0x00000038) 366 367 // These bits hold the transmit FIFO interrupt level. 368 #define AM_REG_UART_IFLS_TXIFLSEL_S 0 369 #define AM_REG_UART_IFLS_TXIFLSEL_M 0x00000007 370 #define AM_REG_UART_IFLS_TXIFLSEL(n) (((uint32_t)(n) << 0) & 0x00000007) 371 372 //***************************************************************************** 373 // 374 // UART_IER - Interrupt Enable 375 // 376 //***************************************************************************** 377 // This bit holds the overflow interrupt enable. 378 #define AM_REG_UART_IER_OEIM_S 10 379 #define AM_REG_UART_IER_OEIM_M 0x00000400 380 #define AM_REG_UART_IER_OEIM(n) (((uint32_t)(n) << 10) & 0x00000400) 381 382 // This bit holds the break error interrupt enable. 383 #define AM_REG_UART_IER_BEIM_S 9 384 #define AM_REG_UART_IER_BEIM_M 0x00000200 385 #define AM_REG_UART_IER_BEIM(n) (((uint32_t)(n) << 9) & 0x00000200) 386 387 // This bit holds the parity error interrupt enable. 388 #define AM_REG_UART_IER_PEIM_S 8 389 #define AM_REG_UART_IER_PEIM_M 0x00000100 390 #define AM_REG_UART_IER_PEIM(n) (((uint32_t)(n) << 8) & 0x00000100) 391 392 // This bit holds the framing error interrupt enable. 393 #define AM_REG_UART_IER_FEIM_S 7 394 #define AM_REG_UART_IER_FEIM_M 0x00000080 395 #define AM_REG_UART_IER_FEIM(n) (((uint32_t)(n) << 7) & 0x00000080) 396 397 // This bit holds the receive timeout interrupt enable. 398 #define AM_REG_UART_IER_RTIM_S 6 399 #define AM_REG_UART_IER_RTIM_M 0x00000040 400 #define AM_REG_UART_IER_RTIM(n) (((uint32_t)(n) << 6) & 0x00000040) 401 402 // This bit holds the transmit interrupt enable. 403 #define AM_REG_UART_IER_TXIM_S 5 404 #define AM_REG_UART_IER_TXIM_M 0x00000020 405 #define AM_REG_UART_IER_TXIM(n) (((uint32_t)(n) << 5) & 0x00000020) 406 407 // This bit holds the receive interrupt enable. 408 #define AM_REG_UART_IER_RXIM_S 4 409 #define AM_REG_UART_IER_RXIM_M 0x00000010 410 #define AM_REG_UART_IER_RXIM(n) (((uint32_t)(n) << 4) & 0x00000010) 411 412 // This bit holds the modem DSR interrupt enable. 413 #define AM_REG_UART_IER_DSRMIM_S 3 414 #define AM_REG_UART_IER_DSRMIM_M 0x00000008 415 #define AM_REG_UART_IER_DSRMIM(n) (((uint32_t)(n) << 3) & 0x00000008) 416 417 // This bit holds the modem DCD interrupt enable. 418 #define AM_REG_UART_IER_DCDMIM_S 2 419 #define AM_REG_UART_IER_DCDMIM_M 0x00000004 420 #define AM_REG_UART_IER_DCDMIM(n) (((uint32_t)(n) << 2) & 0x00000004) 421 422 // This bit holds the modem CTS interrupt enable. 423 #define AM_REG_UART_IER_CTSMIM_S 1 424 #define AM_REG_UART_IER_CTSMIM_M 0x00000002 425 #define AM_REG_UART_IER_CTSMIM(n) (((uint32_t)(n) << 1) & 0x00000002) 426 427 // This bit holds the modem TXCMP interrupt enable. 428 #define AM_REG_UART_IER_TXCMPMIM_S 0 429 #define AM_REG_UART_IER_TXCMPMIM_M 0x00000001 430 #define AM_REG_UART_IER_TXCMPMIM(n) (((uint32_t)(n) << 0) & 0x00000001) 431 432 //***************************************************************************** 433 // 434 // UART_IES - Interrupt Status 435 // 436 //***************************************************************************** 437 // This bit holds the overflow interrupt status. 438 #define AM_REG_UART_IES_OERIS_S 10 439 #define AM_REG_UART_IES_OERIS_M 0x00000400 440 #define AM_REG_UART_IES_OERIS(n) (((uint32_t)(n) << 10) & 0x00000400) 441 442 // This bit holds the break error interrupt status. 443 #define AM_REG_UART_IES_BERIS_S 9 444 #define AM_REG_UART_IES_BERIS_M 0x00000200 445 #define AM_REG_UART_IES_BERIS(n) (((uint32_t)(n) << 9) & 0x00000200) 446 447 // This bit holds the parity error interrupt status. 448 #define AM_REG_UART_IES_PERIS_S 8 449 #define AM_REG_UART_IES_PERIS_M 0x00000100 450 #define AM_REG_UART_IES_PERIS(n) (((uint32_t)(n) << 8) & 0x00000100) 451 452 // This bit holds the framing error interrupt status. 453 #define AM_REG_UART_IES_FERIS_S 7 454 #define AM_REG_UART_IES_FERIS_M 0x00000080 455 #define AM_REG_UART_IES_FERIS(n) (((uint32_t)(n) << 7) & 0x00000080) 456 457 // This bit holds the receive timeout interrupt status. 458 #define AM_REG_UART_IES_RTRIS_S 6 459 #define AM_REG_UART_IES_RTRIS_M 0x00000040 460 #define AM_REG_UART_IES_RTRIS(n) (((uint32_t)(n) << 6) & 0x00000040) 461 462 // This bit holds the transmit interrupt status. 463 #define AM_REG_UART_IES_TXRIS_S 5 464 #define AM_REG_UART_IES_TXRIS_M 0x00000020 465 #define AM_REG_UART_IES_TXRIS(n) (((uint32_t)(n) << 5) & 0x00000020) 466 467 // This bit holds the receive interrupt status. 468 #define AM_REG_UART_IES_RXRIS_S 4 469 #define AM_REG_UART_IES_RXRIS_M 0x00000010 470 #define AM_REG_UART_IES_RXRIS(n) (((uint32_t)(n) << 4) & 0x00000010) 471 472 // This bit holds the modem DSR interrupt status. 473 #define AM_REG_UART_IES_DSRMRIS_S 3 474 #define AM_REG_UART_IES_DSRMRIS_M 0x00000008 475 #define AM_REG_UART_IES_DSRMRIS(n) (((uint32_t)(n) << 3) & 0x00000008) 476 477 // This bit holds the modem DCD interrupt status. 478 #define AM_REG_UART_IES_DCDMRIS_S 2 479 #define AM_REG_UART_IES_DCDMRIS_M 0x00000004 480 #define AM_REG_UART_IES_DCDMRIS(n) (((uint32_t)(n) << 2) & 0x00000004) 481 482 // This bit holds the modem CTS interrupt status. 483 #define AM_REG_UART_IES_CTSMRIS_S 1 484 #define AM_REG_UART_IES_CTSMRIS_M 0x00000002 485 #define AM_REG_UART_IES_CTSMRIS(n) (((uint32_t)(n) << 1) & 0x00000002) 486 487 // This bit holds the modem TXCMP interrupt status. 488 #define AM_REG_UART_IES_TXCMPMRIS_S 0 489 #define AM_REG_UART_IES_TXCMPMRIS_M 0x00000001 490 #define AM_REG_UART_IES_TXCMPMRIS(n) (((uint32_t)(n) << 0) & 0x00000001) 491 492 //***************************************************************************** 493 // 494 // UART_MIS - Masked Interrupt Status 495 // 496 //***************************************************************************** 497 // This bit holds the overflow interrupt status masked. 498 #define AM_REG_UART_MIS_OEMIS_S 10 499 #define AM_REG_UART_MIS_OEMIS_M 0x00000400 500 #define AM_REG_UART_MIS_OEMIS(n) (((uint32_t)(n) << 10) & 0x00000400) 501 502 // This bit holds the break error interrupt status masked. 503 #define AM_REG_UART_MIS_BEMIS_S 9 504 #define AM_REG_UART_MIS_BEMIS_M 0x00000200 505 #define AM_REG_UART_MIS_BEMIS(n) (((uint32_t)(n) << 9) & 0x00000200) 506 507 // This bit holds the parity error interrupt status masked. 508 #define AM_REG_UART_MIS_PEMIS_S 8 509 #define AM_REG_UART_MIS_PEMIS_M 0x00000100 510 #define AM_REG_UART_MIS_PEMIS(n) (((uint32_t)(n) << 8) & 0x00000100) 511 512 // This bit holds the framing error interrupt status masked. 513 #define AM_REG_UART_MIS_FEMIS_S 7 514 #define AM_REG_UART_MIS_FEMIS_M 0x00000080 515 #define AM_REG_UART_MIS_FEMIS(n) (((uint32_t)(n) << 7) & 0x00000080) 516 517 // This bit holds the receive timeout interrupt status masked. 518 #define AM_REG_UART_MIS_RTMIS_S 6 519 #define AM_REG_UART_MIS_RTMIS_M 0x00000040 520 #define AM_REG_UART_MIS_RTMIS(n) (((uint32_t)(n) << 6) & 0x00000040) 521 522 // This bit holds the transmit interrupt status masked. 523 #define AM_REG_UART_MIS_TXMIS_S 5 524 #define AM_REG_UART_MIS_TXMIS_M 0x00000020 525 #define AM_REG_UART_MIS_TXMIS(n) (((uint32_t)(n) << 5) & 0x00000020) 526 527 // This bit holds the receive interrupt status masked. 528 #define AM_REG_UART_MIS_RXMIS_S 4 529 #define AM_REG_UART_MIS_RXMIS_M 0x00000010 530 #define AM_REG_UART_MIS_RXMIS(n) (((uint32_t)(n) << 4) & 0x00000010) 531 532 // This bit holds the modem DSR interrupt status masked. 533 #define AM_REG_UART_MIS_DSRMMIS_S 3 534 #define AM_REG_UART_MIS_DSRMMIS_M 0x00000008 535 #define AM_REG_UART_MIS_DSRMMIS(n) (((uint32_t)(n) << 3) & 0x00000008) 536 537 // This bit holds the modem DCD interrupt status masked. 538 #define AM_REG_UART_MIS_DCDMMIS_S 2 539 #define AM_REG_UART_MIS_DCDMMIS_M 0x00000004 540 #define AM_REG_UART_MIS_DCDMMIS(n) (((uint32_t)(n) << 2) & 0x00000004) 541 542 // This bit holds the modem CTS interrupt status masked. 543 #define AM_REG_UART_MIS_CTSMMIS_S 1 544 #define AM_REG_UART_MIS_CTSMMIS_M 0x00000002 545 #define AM_REG_UART_MIS_CTSMMIS(n) (((uint32_t)(n) << 1) & 0x00000002) 546 547 // This bit holds the modem TXCMP interrupt status masked. 548 #define AM_REG_UART_MIS_TXCMPMMIS_S 0 549 #define AM_REG_UART_MIS_TXCMPMMIS_M 0x00000001 550 #define AM_REG_UART_MIS_TXCMPMMIS(n) (((uint32_t)(n) << 0) & 0x00000001) 551 552 //***************************************************************************** 553 // 554 // UART_IEC - Interrupt Clear 555 // 556 //***************************************************************************** 557 // This bit holds the overflow interrupt clear. 558 #define AM_REG_UART_IEC_OEIC_S 10 559 #define AM_REG_UART_IEC_OEIC_M 0x00000400 560 #define AM_REG_UART_IEC_OEIC(n) (((uint32_t)(n) << 10) & 0x00000400) 561 562 // This bit holds the break error interrupt clear. 563 #define AM_REG_UART_IEC_BEIC_S 9 564 #define AM_REG_UART_IEC_BEIC_M 0x00000200 565 #define AM_REG_UART_IEC_BEIC(n) (((uint32_t)(n) << 9) & 0x00000200) 566 567 // This bit holds the parity error interrupt clear. 568 #define AM_REG_UART_IEC_PEIC_S 8 569 #define AM_REG_UART_IEC_PEIC_M 0x00000100 570 #define AM_REG_UART_IEC_PEIC(n) (((uint32_t)(n) << 8) & 0x00000100) 571 572 // This bit holds the framing error interrupt clear. 573 #define AM_REG_UART_IEC_FEIC_S 7 574 #define AM_REG_UART_IEC_FEIC_M 0x00000080 575 #define AM_REG_UART_IEC_FEIC(n) (((uint32_t)(n) << 7) & 0x00000080) 576 577 // This bit holds the receive timeout interrupt clear. 578 #define AM_REG_UART_IEC_RTIC_S 6 579 #define AM_REG_UART_IEC_RTIC_M 0x00000040 580 #define AM_REG_UART_IEC_RTIC(n) (((uint32_t)(n) << 6) & 0x00000040) 581 582 // This bit holds the transmit interrupt clear. 583 #define AM_REG_UART_IEC_TXIC_S 5 584 #define AM_REG_UART_IEC_TXIC_M 0x00000020 585 #define AM_REG_UART_IEC_TXIC(n) (((uint32_t)(n) << 5) & 0x00000020) 586 587 // This bit holds the receive interrupt clear. 588 #define AM_REG_UART_IEC_RXIC_S 4 589 #define AM_REG_UART_IEC_RXIC_M 0x00000010 590 #define AM_REG_UART_IEC_RXIC(n) (((uint32_t)(n) << 4) & 0x00000010) 591 592 // This bit holds the modem DSR interrupt clear. 593 #define AM_REG_UART_IEC_DSRMIC_S 3 594 #define AM_REG_UART_IEC_DSRMIC_M 0x00000008 595 #define AM_REG_UART_IEC_DSRMIC(n) (((uint32_t)(n) << 3) & 0x00000008) 596 597 // This bit holds the modem DCD interrupt clear. 598 #define AM_REG_UART_IEC_DCDMIC_S 2 599 #define AM_REG_UART_IEC_DCDMIC_M 0x00000004 600 #define AM_REG_UART_IEC_DCDMIC(n) (((uint32_t)(n) << 2) & 0x00000004) 601 602 // This bit holds the modem CTS interrupt clear. 603 #define AM_REG_UART_IEC_CTSMIC_S 1 604 #define AM_REG_UART_IEC_CTSMIC_M 0x00000002 605 #define AM_REG_UART_IEC_CTSMIC(n) (((uint32_t)(n) << 1) & 0x00000002) 606 607 // This bit holds the modem TXCMP interrupt clear. 608 #define AM_REG_UART_IEC_TXCMPMIC_S 0 609 #define AM_REG_UART_IEC_TXCMPMIC_M 0x00000001 610 #define AM_REG_UART_IEC_TXCMPMIC(n) (((uint32_t)(n) << 0) & 0x00000001) 611 612 #endif // AM_REG_UART_H 613