1 //***************************************************************************** 2 // 3 // am_reg_wdt.h 4 //! @file 5 //! 6 //! @brief Register macros for the WDT module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_WDT_H 45 #define AM_REG_WDT_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_WDT_NUM_MODULES 1 53 #define AM_REG_WDTn(n) \ 54 (REG_WDT_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_WDT_CFG_O 0x00000000 62 #define AM_REG_WDT_RSTRT_O 0x00000004 63 #define AM_REG_WDT_LOCK_O 0x00000008 64 #define AM_REG_WDT_COUNT_O 0x0000000C 65 #define AM_REG_WDT_INTEN_O 0x00000200 66 #define AM_REG_WDT_INTSTAT_O 0x00000204 67 #define AM_REG_WDT_INTCLR_O 0x00000208 68 #define AM_REG_WDT_INTSET_O 0x0000020C 69 70 //***************************************************************************** 71 // 72 // WDT_INTEN - WDT Interrupt register: Enable 73 // 74 //***************************************************************************** 75 // Watchdog Timer Interrupt. 76 #define AM_REG_WDT_INTEN_WDT_S 0 77 #define AM_REG_WDT_INTEN_WDT_M 0x00000001 78 #define AM_REG_WDT_INTEN_WDT(n) (((uint32_t)(n) << 0) & 0x00000001) 79 80 //***************************************************************************** 81 // 82 // WDT_INTSTAT - WDT Interrupt register: Status 83 // 84 //***************************************************************************** 85 // Watchdog Timer Interrupt. 86 #define AM_REG_WDT_INTSTAT_WDT_S 0 87 #define AM_REG_WDT_INTSTAT_WDT_M 0x00000001 88 #define AM_REG_WDT_INTSTAT_WDT(n) (((uint32_t)(n) << 0) & 0x00000001) 89 90 //***************************************************************************** 91 // 92 // WDT_INTCLR - WDT Interrupt register: Clear 93 // 94 //***************************************************************************** 95 // Watchdog Timer Interrupt. 96 #define AM_REG_WDT_INTCLR_WDT_S 0 97 #define AM_REG_WDT_INTCLR_WDT_M 0x00000001 98 #define AM_REG_WDT_INTCLR_WDT(n) (((uint32_t)(n) << 0) & 0x00000001) 99 100 //***************************************************************************** 101 // 102 // WDT_INTSET - WDT Interrupt register: Set 103 // 104 //***************************************************************************** 105 // Watchdog Timer Interrupt. 106 #define AM_REG_WDT_INTSET_WDT_S 0 107 #define AM_REG_WDT_INTSET_WDT_M 0x00000001 108 #define AM_REG_WDT_INTSET_WDT(n) (((uint32_t)(n) << 0) & 0x00000001) 109 110 //***************************************************************************** 111 // 112 // WDT_CFG - Configuration Register 113 // 114 //***************************************************************************** 115 // Select the frequency for the WDT. All values not enumerated below are 116 // undefined. 117 #define AM_REG_WDT_CFG_CLKSEL_S 24 118 #define AM_REG_WDT_CFG_CLKSEL_M 0x07000000 119 #define AM_REG_WDT_CFG_CLKSEL(n) (((uint32_t)(n) << 24) & 0x07000000) 120 #define AM_REG_WDT_CFG_CLKSEL_OFF 0x00000000 121 #define AM_REG_WDT_CFG_CLKSEL_128HZ 0x01000000 122 #define AM_REG_WDT_CFG_CLKSEL_16HZ 0x02000000 123 #define AM_REG_WDT_CFG_CLKSEL_1HZ 0x03000000 124 #define AM_REG_WDT_CFG_CLKSEL_1_16HZ 0x04000000 125 126 // This bitfield is the compare value for counter bits 7:0 to generate a 127 // watchdog interrupt. 128 #define AM_REG_WDT_CFG_INTVAL_S 16 129 #define AM_REG_WDT_CFG_INTVAL_M 0x00FF0000 130 #define AM_REG_WDT_CFG_INTVAL(n) (((uint32_t)(n) << 16) & 0x00FF0000) 131 132 // This bitfield is the compare value for counter bits 7:0 to generate a 133 // watchdog reset. 134 #define AM_REG_WDT_CFG_RESVAL_S 8 135 #define AM_REG_WDT_CFG_RESVAL_M 0x0000FF00 136 #define AM_REG_WDT_CFG_RESVAL(n) (((uint32_t)(n) << 8) & 0x0000FF00) 137 138 // This bitfield enables the WDT reset. 139 #define AM_REG_WDT_CFG_RESEN_S 2 140 #define AM_REG_WDT_CFG_RESEN_M 0x00000004 141 #define AM_REG_WDT_CFG_RESEN(n) (((uint32_t)(n) << 2) & 0x00000004) 142 143 // This bitfield enables the WDT interrupt. Note : This bit must be set before 144 // the interrupt status bit will reflect a watchdog timer expiration. The IER 145 // interrupt register must also be enabled for a WDT interrupt to be sent to the 146 // NVIC. 147 #define AM_REG_WDT_CFG_INTEN_S 1 148 #define AM_REG_WDT_CFG_INTEN_M 0x00000002 149 #define AM_REG_WDT_CFG_INTEN(n) (((uint32_t)(n) << 1) & 0x00000002) 150 151 // This bitfield enables the WDT. 152 #define AM_REG_WDT_CFG_WDTEN_S 0 153 #define AM_REG_WDT_CFG_WDTEN_M 0x00000001 154 #define AM_REG_WDT_CFG_WDTEN(n) (((uint32_t)(n) << 0) & 0x00000001) 155 156 //***************************************************************************** 157 // 158 // WDT_RSTRT - Restart the watchdog timer 159 // 160 //***************************************************************************** 161 // Writing 0xB2 to WDTRSTRT restarts the watchdog timer. 162 #define AM_REG_WDT_RSTRT_RSTRT_S 0 163 #define AM_REG_WDT_RSTRT_RSTRT_M 0x000000FF 164 #define AM_REG_WDT_RSTRT_RSTRT(n) (((uint32_t)(n) << 0) & 0x000000FF) 165 #define AM_REG_WDT_RSTRT_RSTRT_KEYVALUE 0x000000B2 166 167 //***************************************************************************** 168 // 169 // WDT_LOCK - Locks the WDT 170 // 171 //***************************************************************************** 172 // Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be 173 // written and WDTEN is set. 174 #define AM_REG_WDT_LOCK_LOCK_S 0 175 #define AM_REG_WDT_LOCK_LOCK_M 0x000000FF 176 #define AM_REG_WDT_LOCK_LOCK(n) (((uint32_t)(n) << 0) & 0x000000FF) 177 #define AM_REG_WDT_LOCK_LOCK_KEYVALUE 0x0000003A 178 179 //***************************************************************************** 180 // 181 // WDT_COUNT - Current Counter Value for WDT 182 // 183 //***************************************************************************** 184 // Read-Only current value of the WDT counter 185 #define AM_REG_WDT_COUNT_COUNT_S 0 186 #define AM_REG_WDT_COUNT_COUNT_M 0x000000FF 187 #define AM_REG_WDT_COUNT_COUNT(n) (((uint32_t)(n) << 0) & 0x000000FF) 188 189 #endif // AM_REG_WDT_H 190