1 /** 2 ****************************************************************************** 3 * @file acomp_reg.h 4 * @version V1.0 5 * @date 2023-03-07 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 37 #ifndef __HARDWARE_ACOMP_H__ 38 #define __HARDWARE_ACOMP_H__ 39 40 /**************************************************************************** 41 * Pre-processor Definitions 42 ****************************************************************************/ 43 44 /* Register offsets *********************************************************/ 45 /* aon base */ 46 #define AON_ACOMP_REG_ACOMP0_CTRL_OFFSET (0x900) /* acomp0_ctrl */ 47 #define AON_ACOMP_REG_ACOMP1_CTRL_OFFSET (0x904) /* acomp0_ctrl */ 48 #define AON_ACOMP_REG_ACOMP_CFG_OFFSET (0x908) /* acomp_ctrl */ 49 50 51 /* Register Bitfield definitions *****************************************************/ 52 /* 0x900 : acomp0_ctrl */ 53 /* 0x904 : acomp1_ctrl */ 54 #define AON_ACOMP_MUX_EN (1 << 26U) 55 #define AON_ACOMP_POS_SEL_SHIFT (22U) 56 #define AON_ACOMP_POS_SEL_MASK (0xf << AON_ACOMP_POS_SEL_SHIFT) 57 #define AON_ACOMP_NEG_SEL_SHIFT (18U) 58 #define AON_ACOMP_NEG_SEL_MASK (0xf << AON_ACOMP_NEG_SEL_SHIFT) 59 #define AON_ACOMP_LEVEL_SEL_SHIFT (12U) 60 #define AON_ACOMP_LEVEL_SEL_MASK (0x3f << AON_ACOMP_LEVEL_SEL_SHIFT) 61 #define AON_ACOMP_BIAS_PROG_SHIFT (10U) 62 #define AON_ACOMP_BIAS_PROG_MASK (0x3 << AON_ACOMP_BIAS_PROG_SHIFT) 63 #define AON_ACOMP_HYST_SELP_SHIFT (7U) 64 #define AON_ACOMP_HYST_SELP_MASK (0x7 << AON_ACOMP_HYST_SELP_SHIFT) 65 #define AON_ACOMP_HYST_SELN_SHIFT (4U) 66 #define AON_ACOMP_HYST_SELN_MASK (0x7 << AON_ACOMP_HYST_SELN_SHIFT) 67 #define AON_ACOMP_EN (1 << 0U) 68 69 /* 0x908 : acomp_ctrl */ 70 #define AON_ACOMP_VREF_SEL_SHIFT (24U) 71 #define AON_ACOMP_VREF_SEL_MASK (0x3f << AON_ACOMP_VREF_SEL_SHIFT) 72 #define AON_ACOMP0_OUT_RAW_DATA_SHIFT (19U) 73 #define AON_ACOMP0_OUT_RAW_DATA_MASK (0x1 << AON_ACOMP0_OUT_RAW_DATA_SHIFT) 74 #define AON_ACOMP1_OUT_RAW_DATA_SHIFT (17U) 75 #define AON_ACOMP1_OUT_RAW_DATA_MASK (0x1 << AON_ACOMP1_OUT_RAW_DATA_SHIFT) 76 #define AON_ACOMP0_TEST_SEL_SHIFT (12U) 77 #define AON_ACOMP0_TEST_SEL_MASK (0x3 << AON_ACOMP0_TEST_SEL_SHIFT) 78 #define AON_ACOMP1_TEST_SEL_SHIFT (10U) 79 #define AON_ACOMP1_TEST_SEL_MASK (0x3 << AON_ACOMP1_TEST_SEL_SHIFT) 80 #define AON_ACOMP0_TEST_EN (1 << 9U) 81 #define AON_ACOMP1_TEST_EN (1 << 8U) 82 #define AON_ACOMP0_RSTN_ANA (1 << 1U) 83 #define AON_ACOMP1_RSTN_ANA (1 << 0U) 84 #endif 85