1 /* 2 * Copyright (C) 2017-2024 Alibaba Group Holding Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 /* 20 * attention: don't modify this file as a suggest 21 * you should copy from chip_riscv_dummy/include/asm/riscv_csr.h and keep it newer 22 * please contact xuantie-rtos os team if have question 23 */ 24 25 #ifndef __RISCV_CSR_H__ 26 #define __RISCV_CSR_H__ 27 28 #if __riscv_xlen == 64 29 #define portWORD_SIZE 8 30 #define store_x sd 31 #define load_x ld 32 #elif __riscv_xlen == 32 33 #define store_x sw 34 #define load_x lw 35 #define portWORD_SIZE 4 36 #else 37 #error Assembler did not define __riscv_xlen 38 #endif 39 40 #if __riscv_flen == 64 41 #define fstore_x fsd 42 #define fload_x fld 43 #elif __riscv_flen == 32 44 #define fstore_x fsw 45 #define fload_x flw 46 #endif 47 48 #if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE 49 #define MODE_PREFIX(suffix) s##suffix 50 #else 51 #define MODE_PREFIX(suffix) m##suffix 52 #endif 53 54 /* Status register flags */ 55 #define SR_SIE 0x00000002UL /* Supervisor Interrupt Enable */ 56 #define SR_MIE 0x00000008UL /* Machine Interrupt Enable */ 57 #define SR_SPIE 0x00000020UL /* Previous Supervisor IE */ 58 #define SR_MPIE 0x00000080UL /* Previous Machine IE */ 59 #define SR_SPP_U 0x00000000UL /* Previously User mode */ 60 #define SR_SPP_S 0x00000100UL /* Previously Supervisor mode */ 61 #define SR_MPP_U 0x00000000UL /* Previously User mode */ 62 #define SR_MPP_S 0x00000800UL /* Previously Supervisor mode */ 63 #define SR_MPP_M 0x00001800UL /* Previously Machine mode */ 64 #define SR_SUM 0x00040000UL /* Supervisor User Memory Access */ 65 66 #define SR_FS 0x00006000UL /* Floating-point Status */ 67 #define SR_FS_OFF 0x00000000UL 68 #define SR_FS_INITIAL 0x00002000UL 69 #define SR_FS_CLEAN 0x00004000UL 70 #define SR_FS_DIRTY 0x00006000UL 71 72 #if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_R920 73 #define SR_VS 0x01800000 74 #define SR_VS_OFF 0x00000000 75 #define SR_VS_INITIAL 0x00800000 76 #define SR_VS_CLEAN 0x01000000 77 #define SR_VS_DIRTY 0x01800000 78 #else 79 #define SR_VS 0x00000600 80 #define SR_VS_OFF 0x00000000 81 #define SR_VS_INITIAL 0x00000200 82 #define SR_VS_CLEAN 0x00000400 83 #define SR_VS_DIRTY 0x00000600 84 #endif 85 86 #if __riscv_matrix || __riscv_xtheadmatrix 87 #define SR_MS 0x06000000 88 #define SR_MS_OFF 0x00000000 89 #define SR_MS_INITIAL 0x02000000 90 #define SR_MS_CLEAN 0x04000000 91 #define SR_MS_DIRTY 0x06000000 92 #endif 93 94 /* Interrupt-enable Registers */ 95 #define IE_MTIE 0x00000080UL 96 #define IE_MEIE 0x00000800UL 97 98 /* ===== Trap/Exception Causes ===== */ 99 #define CAUSE_MISALIGNED_FETCH 0x0 100 #define CAUSE_FETCH_ACCESS 0x1 101 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 102 #define CAUSE_BREAKPOINT 0x3 103 #define CAUSE_MISALIGNED_LOAD 0x4 104 #define CAUSE_LOAD_ACCESS 0x5 105 #define CAUSE_MISALIGNED_STORE 0x6 106 #define CAUSE_STORE_ACCESS 0x7 107 #define CAUSE_USER_ECALL 0x8 108 #define CAUSE_SUPERVISOR_ECALL 0x9 109 #define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa 110 #define CAUSE_MACHINE_ECALL 0xb 111 #define CAUSE_FETCH_PAGE_FAULT 0xc 112 #define CAUSE_LOAD_PAGE_FAULT 0xd 113 #define CAUSE_STORE_PAGE_FAULT 0xf 114 115 #define PRV_U 0 116 #define PRV_S 1 117 #define PRV_M 3 118 119 120 #define MSTATUS_SIE 0x00000002 121 #define MSTATUS_MIE 0x00000008 122 #define MSTATUS_SPIE_SHIFT 5 123 #define MSTATUS_SPIE (1 << MSTATUS_SPIE_SHIFT) 124 #define MSTATUS_UBE 0x00000040 125 #define MSTATUS_MPIE 0x00000080 126 #define MSTATUS_SPP_SHIFT 8 127 #define MSTATUS_SPP (1 << MSTATUS_SPP_SHIFT) 128 #define MSTATUS_MPP_SHIFT 11 129 #define MSTATUS_MPP (3 << MSTATUS_MPP_SHIFT) 130 131 #if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 132 #define MSTATUS_VS_SHIFT 23 133 #else 134 #define MSTATUS_VS_SHIFT 9 135 #endif 136 #define MSTATUS_FS_SHIFT 13 137 #define MSTATUS_MS_SHIFT 25 138 139 #define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) 140 141 #if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V ||CONFIG_CPU_XUANTIE_C908I || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 142 #define ATTR_SO (1ull << 4) 143 #define ATTR_CA (1ull << 3) 144 #define ATTR_BU (1ull << 2) 145 #define ATTR_SH (1ull << 1) 146 #define ATTR_SE (1ull << 0) 147 148 #define UPPER_ATTRS_SHIFT (59) 149 #define UPPER_ATTRS(x) (((x) & 0x1f) << UPPER_ATTRS_SHIFT) 150 #else 151 #if __riscv_xlen == 32 152 #define PTE_PBMT_SHIFT (30) 153 #else 154 #define PTE_PBMT_SHIFT (61) 155 #endif /* end __riscv_xlen */ 156 #define SVPBMT_PMA ((unsigned long)0x0 << PTE_PBMT_SHIFT) 157 #define SVPBMT_NC ((unsigned long)0x1 << PTE_PBMT_SHIFT) 158 #define SVPBMT_IO ((unsigned long)0x2 << PTE_PBMT_SHIFT) 159 #define SVPBMT_MASK ((unsigned long)0x3 << PTE_PBMT_SHIFT) 160 161 #endif 162 163 #define DIRTY_FLAG (1 << 6) 164 #define ACCESS_FLAG (1 << 5) 165 #define GLOBAL_FLAG (1 << 4) 166 #define AP_UNPRIV (1 << 3) 167 #define AP_X (1 << 2) 168 #define AP_W (1 << 1) 169 #define AP_R (1 << 0) 170 171 #define LOWER_ATTRS_SHIFT 1 172 #define LOWER_ATTRS(x) (((x) & 0x1ff) << LOWER_ATTRS_SHIFT) 173 174 175 176 #endif /* __RISCV_CSR_H__ */ 177 178