1 /** 2 ****************************************************************************** 3 * @file audac_reg.h 4 * @version V1.0 5 * @date 2022-12-03 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __AUDAC_REG_H__ 37 #define __AUDAC_REG_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define AUDAC_0_OFFSET (0x000) /* audac_0 */ 46 #define AUDAC_STATUS_OFFSET (0x4) /* audac_status */ 47 #define AUDAC_S0_OFFSET (0x8) /* audac_s0 */ 48 #define AUDAC_S0_MISC_OFFSET (0xC) /* audac_s0_misc */ 49 #define AUDAC_ZD_0_OFFSET (0x10) /* audac_zd_0 */ 50 #define AUDAC_1_OFFSET (0x14) /* audac_1 */ 51 #define AUDAC_RSVD_OFFSET (0x18) /* audac_rsvd */ 52 #define AUDAC_TEST_0_OFFSET (0x1C) /* audac_test_0 */ 53 #define AUDAC_TEST_1_OFFSET (0x20) /* audac_test_1 */ 54 #define AUDAC_TEST_2_OFFSET (0x24) /* audac_test_2 */ 55 #define AUDAC_TEST_3_OFFSET (0x28) /* audac_test_3 */ 56 #define AUDAC_FIFO_CTRL_OFFSET (0x8C) /* audac_fifo_ctrl */ 57 #define AUDAC_FIFO_STATUS_OFFSET (0x90) /* audac_fifo_status */ 58 #define AUDAC_FIFO_DATA_OFFSET (0x94) /* audac_fifo_data */ 59 60 /* Register Bitfield definitions *****************************************************/ 61 62 /* 0x000 : audac_0 */ 63 #define AUDAC_DAC_0_EN (1 << 0U) 64 #define AUDAC_DAC_ITF_EN (1 << 1U) 65 #define AUDAC_CKG_ENA (1 << 27U) 66 #define AUDAC_AU_PWM_MODE_SHIFT (28U) 67 #define AUDAC_AU_PWM_MODE_MASK (0xf << AUDAC_AU_PWM_MODE_SHIFT) 68 69 /* 0x4 : audac_status */ 70 #define AUDAC_DAC_H0_BUSY (1 << 12U) 71 #define AUDAC_DAC_H0_MUTE_DONE (1 << 13U) 72 #define AUDAC_DAC_S0_INT (1 << 16U) 73 #define AUDAC_DAC_S0_INT_CLR (1 << 17U) 74 #define AUDAC_ZD_AMUTE (1 << 23U) 75 #define AUDAC_AUDIO_INT_ALL (1 << 24U) 76 77 /* 0x8 : audac_s0 */ 78 #define AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT (2U) 79 #define AUDAC_DAC_S0_CTRL_RMP_RATE_MASK (0xf << AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT) 80 #define AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT (6U) 81 #define AUDAC_DAC_S0_CTRL_ZCD_RATE_MASK (0xf << AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT) 82 #define AUDAC_DAC_S0_CTRL_MODE_SHIFT (10U) 83 #define AUDAC_DAC_S0_CTRL_MODE_MASK (0x3 << AUDAC_DAC_S0_CTRL_MODE_SHIFT) 84 #define AUDAC_DAC_S0_VOLUME_UPDATE (1 << 12U) 85 #define AUDAC_DAC_S0_VOLUME_SHIFT (13U) 86 #define AUDAC_DAC_S0_VOLUME_MASK (0x1ff << AUDAC_DAC_S0_VOLUME_SHIFT) 87 #define AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT (22U) 88 #define AUDAC_DAC_S0_MUTE_RMPUP_RATE_MASK (0xf << AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT) 89 #define AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT (26U) 90 #define AUDAC_DAC_S0_MUTE_RMPDN_RATE_MASK (0xf << AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT) 91 #define AUDAC_DAC_S0_MUTE_SOFTMODE (1 << 30U) 92 #define AUDAC_DAC_S0_MUTE (1 << 31U) 93 94 /* 0xC : audac_s0_misc */ 95 #define AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_SHIFT (28U) 96 #define AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_MASK (0xf << AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_SHIFT) 97 98 /* 0x10 : audac_zd_0 */ 99 #define AUDAC_ZD_TIME_SHIFT (0U) 100 #define AUDAC_ZD_TIME_MASK (0x7fff << AUDAC_ZD_TIME_SHIFT) 101 #define AUDAC_ZD_EN (1 << 16U) 102 103 /* 0x14 : audac_1 */ 104 #define AUDAC_DAC_MIX_SEL_SHIFT (0U) 105 #define AUDAC_DAC_MIX_SEL_MASK (0x3 << AUDAC_DAC_MIX_SEL_SHIFT) 106 #define AUDAC_DAC_DSM_OUT_FMT (1 << 4U) 107 #define AUDAC_DAC_DSM_ORDER_SHIFT (5U) 108 #define AUDAC_DAC_DSM_ORDER_MASK (0x3 << AUDAC_DAC_DSM_ORDER_SHIFT) 109 #define AUDAC_DAC_DSM_SCALING_MODE_SHIFT (7U) 110 #define AUDAC_DAC_DSM_SCALING_MODE_MASK (0x3 << AUDAC_DAC_DSM_SCALING_MODE_SHIFT) 111 #define AUDAC_DAC_DSM_SCALING_EN (1 << 10U) 112 #define AUDAC_DAC_DSM_DITHER_AMP_SHIFT (11U) 113 #define AUDAC_DAC_DSM_DITHER_AMP_MASK (0x7 << AUDAC_DAC_DSM_DITHER_AMP_SHIFT) 114 #define AUDAC_DAC_DSM_DITHER_EN (1 << 14U) 115 #define AUDAC_DAC_DSM_DITHER_PRBS_MODE_SHIFT (15U) 116 #define AUDAC_DAC_DSM_DITHER_PRBS_MODE_MASK (0x3 << AUDAC_DAC_DSM_DITHER_PRBS_MODE_SHIFT) 117 118 /* 0x18 : audac_rsvd */ 119 #define AUDAC_AU_PWM_RESERVED_SHIFT (0U) 120 #define AUDAC_AU_PWM_RESERVED_MASK (0xffffffff << AUDAC_AU_PWM_RESERVED_SHIFT) 121 122 /* 0x1C : audac_test_0 */ 123 #define AUDAC_DAC_IN_0_SHIFT (0U) 124 #define AUDAC_DAC_IN_0_MASK (0xffff << AUDAC_DAC_IN_0_SHIFT) 125 #define AUDAC_DAC_DPGA_0_SHIFT (16U) 126 #define AUDAC_DAC_DPGA_0_MASK (0xffff << AUDAC_DAC_DPGA_0_SHIFT) 127 128 /* 0x20 : audac_test_1 */ 129 #define AUDAC_DAC_FIR_0_SHIFT (0U) 130 #define AUDAC_DAC_FIR_0_MASK (0x1ffff << AUDAC_DAC_FIR_0_SHIFT) 131 132 /* 0x24 : audac_test_2 */ 133 #define AUDAC_DAC_SINC_0_SHIFT (0U) 134 #define AUDAC_DAC_SINC_0_MASK (0xffff << AUDAC_DAC_SINC_0_SHIFT) 135 136 /* 0x28 : audac_test_3 */ 137 #define AUDAC_AU_PWM_TEST_READ_SHIFT (0U) 138 #define AUDAC_AU_PWM_TEST_READ_MASK (0xffffffff << AUDAC_AU_PWM_TEST_READ_SHIFT) 139 140 /* 0x8C : audac_fifo_ctrl */ 141 #define AUDAC_TX_FIFO_FLUSH (1 << 0U) 142 #define AUDAC_TXO_INT_EN (1 << 1U) 143 #define AUDAC_TXU_INT_EN (1 << 2U) 144 #define AUDAC_TXA_INT_EN (1 << 3U) 145 #define AUDAC_TX_DRQ_EN (1 << 4U) 146 #define AUDAC_TX_CH_EN_SHIFT (8U) 147 #define AUDAC_TX_CH_EN_MASK (0x3 << AUDAC_TX_CH_EN_SHIFT) 148 #define AUDAC_TX_DRQ_CNT_SHIFT (14U) 149 #define AUDAC_TX_DRQ_CNT_MASK (0x3 << AUDAC_TX_DRQ_CNT_SHIFT) 150 #define AUDAC_TX_TRG_LEVEL_SHIFT (16U) 151 #define AUDAC_TX_TRG_LEVEL_MASK (0x1f << AUDAC_TX_TRG_LEVEL_SHIFT) 152 #define AUDAC_TX_DATA_MODE_SHIFT (24U) 153 #define AUDAC_TX_DATA_MODE_MASK (0x3 << AUDAC_TX_DATA_MODE_SHIFT) 154 155 /* 0x90 : audac_fifo_status */ 156 #define AUDAC_TXO_INT (1 << 1U) 157 #define AUDAC_TXU_INT (1 << 2U) 158 #define AUDAC_TXA_INT (1 << 4U) 159 #define AUDAC_TXA_CNT_SHIFT (16U) 160 #define AUDAC_TXA_CNT_MASK (0x1f << AUDAC_TXA_CNT_SHIFT) 161 #define AUDAC_TXA (1 << 24U) 162 163 /* 0x94 : audac_fifo_data */ 164 #define AUDAC_TX_DATA_SHIFT (0U) 165 #define AUDAC_TX_DATA_MASK (0xffffffff << AUDAC_TX_DATA_SHIFT) 166 167 #endif /* __AUDAC_REG_H__ */ 168