| /bsp/raspberry-pi/raspi4-64/drivers/ |
| A D | drv_uart.h | 59 #define PL011_REG_DR(BASE) HWREG32(BASE + 0x00) argument
60 #define PL011_REG_RSRECR(BASE) HWREG32(BASE + 0x04) argument
61 #define PL011_REG_RESERVED0(BASE) HWREG32(BASE + 0x08) argument
62 #define PL011_REG_FR(BASE) HWREG32(BASE + 0x18) argument
63 #define PL011_REG_RESERVED1(BASE) HWREG32(BASE + 0x1C) argument
64 #define PL011_REG_ILPR(BASE) HWREG32(BASE + 0x20) argument
65 #define PL011_REG_IBRD(BASE) HWREG32(BASE + 0x24) argument
66 #define PL011_REG_FBRD(BASE) HWREG32(BASE + 0x28) argument
67 #define PL011_REG_LCRH(BASE) HWREG32(BASE + 0x2C) argument
68 #define PL011_REG_CR(BASE) HWREG32(BASE + 0x30) argument
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| A D | drv_gpio.h | 28 #define GPIO_REG_GPFSEL0(BASE) HWREG32(BASE + 0x00) argument
29 #define GPIO_REG_GPFSEL1(BASE) HWREG32(BASE + 0x04) argument
30 #define GPIO_REG_GPFSEL2(BASE) HWREG32(BASE + 0x08) argument
31 #define GPIO_REG_GPFSEL3(BASE) HWREG32(BASE + 0x0C) argument
32 #define GPIO_REG_GPFSEL4(BASE) HWREG32(BASE + 0x10) argument
33 #define GPIO_REG_GPFSEL5(BASE) HWREG32(BASE + 0x14) argument
34 #define GPIO_REG_REV0(BASE) HWREG32(BASE + 0x18) argument
35 #define GPIO_REG_GPSET0(BASE) HWREG32(BASE + 0x1C) argument
36 #define GPIO_REG_GPSET1(BASE) HWREG32(BASE + 0x20) argument
37 #define GPIO_REG_REV1(BASE) HWREG32(BASE + 0x24) argument
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| A D | drv_spi.h | 15 #define SPI_REG_CS(BASE) HWREG32(BASE + 0x00) argument
16 #define SPI_REG_FIFO(BASE) HWREG32(BASE + 0x04) argument
17 #define SPI_REG_CLK(BASE) HWREG32(BASE + 0x08) argument
18 #define SPI_REG_DLEN(BASE) HWREG32(BASE + 0x0C) argument
19 #define SPI_REG_LTOH(BASE) HWREG32(BASE + 0x10) argument
20 #define SPI_REG_DC(BASE) HWREG32(BASE + 0x14) argument
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| /bsp/raspberry-pi/raspi-dm2.0/drivers/ |
| A D | drv_uart.h | 59 #define PL011_REG_DR(BASE) HWREG32(BASE + 0x00) argument
60 #define PL011_REG_RSRECR(BASE) HWREG32(BASE + 0x04) argument
61 #define PL011_REG_RESERVED0(BASE) HWREG32(BASE + 0x08) argument
62 #define PL011_REG_FR(BASE) HWREG32(BASE + 0x18) argument
63 #define PL011_REG_RESERVED1(BASE) HWREG32(BASE + 0x1C) argument
64 #define PL011_REG_ILPR(BASE) HWREG32(BASE + 0x20) argument
65 #define PL011_REG_IBRD(BASE) HWREG32(BASE + 0x24) argument
66 #define PL011_REG_FBRD(BASE) HWREG32(BASE + 0x28) argument
67 #define PL011_REG_LCRH(BASE) HWREG32(BASE + 0x2C) argument
68 #define PL011_REG_CR(BASE) HWREG32(BASE + 0x30) argument
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| /bsp/raspberry-pi/raspi4-32/driver/ |
| A D | drv_uart.h | 59 #define PL011_REG_DR(BASE) HWREG32(BASE + 0x00) argument
60 #define PL011_REG_RSRECR(BASE) HWREG32(BASE + 0x04) argument
61 #define PL011_REG_RESERVED0(BASE) HWREG32(BASE + 0x08) argument
62 #define PL011_REG_FR(BASE) HWREG32(BASE + 0x18) argument
63 #define PL011_REG_RESERVED1(BASE) HWREG32(BASE + 0x1C) argument
64 #define PL011_REG_ILPR(BASE) HWREG32(BASE + 0x20) argument
65 #define PL011_REG_IBRD(BASE) HWREG32(BASE + 0x24) argument
66 #define PL011_REG_FBRD(BASE) HWREG32(BASE + 0x28) argument
67 #define PL011_REG_LCRH(BASE) HWREG32(BASE + 0x2C) argument
68 #define PL011_REG_CR(BASE) HWREG32(BASE + 0x30) argument
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| A D | drv_gpio.h | 28 #define GPIO_REG_GPFSEL0(BASE) HWREG32(BASE + 0x00) argument
29 #define GPIO_REG_GPFSEL1(BASE) HWREG32(BASE + 0x04) argument
30 #define GPIO_REG_GPFSEL2(BASE) HWREG32(BASE + 0x08) argument
31 #define GPIO_REG_GPFSEL3(BASE) HWREG32(BASE + 0x0C) argument
32 #define GPIO_REG_GPFSEL4(BASE) HWREG32(BASE + 0x10) argument
33 #define GPIO_REG_GPFSEL5(BASE) HWREG32(BASE + 0x14) argument
34 #define GPIO_REG_REV0(BASE) HWREG32(BASE + 0x18) argument
35 #define GPIO_REG_GPSET0(BASE) HWREG32(BASE + 0x1C) argument
36 #define GPIO_REG_GPSET1(BASE) HWREG32(BASE + 0x20) argument
37 #define GPIO_REG_REV1(BASE) HWREG32(BASE + 0x24) argument
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| A D | drv_i2c.h | 16 #define BSC_C(BASE) __REG32(BASE + 0x0000) /* BSC Master Control */ argument
17 #define BSC_S(BASE) __REG32(BASE + 0x0004) /* BSC Master Status */ argument
18 #define BSC_DLEN(BASE) __REG32(BASE + 0x0008) /* BSC Master Data Length */ argument
19 #define BSC_A(BASE) __REG32(BASE + 0x000c) /* BSC Master Slave Address */ argument
20 #define BSC_FIFO(BASE) __REG32(BASE + 0x0010) /* BSC Master Data FIFO */ argument
21 #define BSC_DIV(BASE) __REG32(BASE + 0x0014) /* BSC Master Clock Divider */ argument
22 #define BSC_DEL(BASE) __REG32(BASE + 0x0018) /* BSC Master Data Delay */ argument
23 #define BSC_CLKT(BASE) __REG32(BASE + 0x001c) /* BSC Master Clock Stretch Timeout */ argument
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| A D | drv_spi.h | 15 #define SPI_REG_CS(BASE) HWREG32(BASE + 0x00) argument
16 #define SPI_REG_FIFO(BASE) HWREG32(BASE + 0x04) argument
17 #define SPI_REG_CLK(BASE) HWREG32(BASE + 0x08) argument
18 #define SPI_REG_DLEN(BASE) HWREG32(BASE + 0x0C) argument
19 #define SPI_REG_LTOH(BASE) HWREG32(BASE + 0x10) argument
20 #define SPI_REG_DC(BASE) HWREG32(BASE + 0x14) argument
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| /bsp/raspberry-pi/raspi3-32/driver/ |
| A D | drv_uart.h | 17 #define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */ argument
18 #define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */ argument
19 #define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */ argument
22 #define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */ argument
24 #define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */ argument
25 #define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */ argument
26 #define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */ argument
29 #define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */ argument
32 #define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */ argument
33 #define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */ argument
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| A D | raspi.h | 202 #define BCM283X_BSC_C(BASE) HWREG32(BASE + 0x0000) /* BSC Master Control */ argument
203 #define BCM283X_BSC_S(BASE) HWREG32(BASE + 0x0004) /* BSC Master Status */ argument
205 #define BCM283X_BSC_A(BASE) HWREG32(BASE + 0x000c) /* BSC Master Slave Address */ argument
206 #define BCM283X_BSC_FIFO(BASE) HWREG32(BASE + 0x0010) /* BSC Master Data FIFO */ argument
208 #define BCM283X_BSC_DEL(BASE) HWREG32(BASE + 0x0018) /* BSC Master Data Delay */ argument
240 #define BCM283X_SPI0_CS(BASE) HWREG32(BASE + 0x0000) /* SPI Master Control and Status */ argument
241 #define BCM283X_SPI0_FIFO(BASE) HWREG32(BASE + 0x0004) /* SPI Master TX and RX FIFOs */ argument
242 #define BCM283X_SPI0_CLK(BASE) HWREG32(BASE + 0x0008) /* SPI Master Clock Divider */ argument
243 #define BCM283X_SPI0_DLEN(BASE) HWREG32(BASE + 0x000c) /* SPI Master Data Length */ argument
244 #define BCM283X_SPI0_LTOH(BASE) HWREG32(BASE + 0x0010) /* SPI LOSSI mode TOH */ argument
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| /bsp/raspberry-pi/raspi3-64/driver/ |
| A D | drv_uart.h | 18 #define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */ argument
19 #define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */ argument
20 #define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */ argument
23 #define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */ argument
25 #define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */ argument
26 #define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */ argument
27 #define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */ argument
30 #define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */ argument
33 #define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */ argument
34 #define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */ argument
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| A D | raspi.h | 206 #define BCM283X_BSC_C(BASE) __REG32(BASE + 0x0000) /* BSC Master Control */ argument
207 #define BCM283X_BSC_S(BASE) __REG32(BASE + 0x0004) /* BSC Master Status */ argument
209 #define BCM283X_BSC_A(BASE) __REG32(BASE + 0x000c) /* BSC Master Slave Address */ argument
210 #define BCM283X_BSC_FIFO(BASE) __REG32(BASE + 0x0010) /* BSC Master Data FIFO */ argument
212 #define BCM283X_BSC_DEL(BASE) __REG32(BASE + 0x0018) /* BSC Master Data Delay */ argument
244 #define BCM283X_SPI0_CS(BASE) __REG32(BASE + 0x0000) /* SPI Master Control and Status */ argument
245 #define BCM283X_SPI0_FIFO(BASE) __REG32(BASE + 0x0004) /* SPI Master TX and RX FIFOs */ argument
246 #define BCM283X_SPI0_CLK(BASE) __REG32(BASE + 0x0008) /* SPI Master Clock Divider */ argument
247 #define BCM283X_SPI0_DLEN(BASE) __REG32(BASE + 0x000c) /* SPI Master Data Length */ argument
248 #define BCM283X_SPI0_LTOH(BASE) __REG32(BASE + 0x0010) /* SPI LOSSI mode TOH */ argument
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| /bsp/raspberry-pi/raspi2/driver/ |
| A D | drv_uart.h | 18 #define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */ argument
19 #define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */ argument
20 #define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */ argument
23 #define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */ argument
25 #define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */ argument
26 #define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */ argument
27 #define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */ argument
30 #define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */ argument
33 #define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */ argument
34 #define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */ argument
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| /bsp/cvitek/drivers/ |
| A D | drv_sdhci.c | 48 uintptr_t BASE = (uintptr_t)base; in sdhci_set_card_clock() local
124 uintptr_t BASE = (uintptr_t)base; in SDIF_ChangeCardClock() local
546 uintptr_t BASE = (uintptr_t)base; in sdhci_set_bus_width() local
569 uintptr_t BASE = (uintptr_t)base; in sdhci_enable_card_power() local
583 uintptr_t BASE = (uintptr_t)base; in sdhci_detect_card_insert() local
596 uintptr_t BASE = (uintptr_t)base; in sdhci_enable_card_clock() local
609 uintptr_t BASE = (uintptr_t)base; in sdhci_hw_reset() local
623 uintptr_t BASE = (uintptr_t)base; in sdhci_pad_setting() local
700 uintptr_t BASE = (uintptr_t)base; in sdhci_phy_init() local
732 uintptr_t BASE = (uintptr_t)base; in sdhci_init() local
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| /bsp/acm32/acm32f4xx-nucleo/libraries/CMSIS/ |
| A D | mpu_armv8.h | 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
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| /bsp/airm2m/air105/libraries/HAL_Driver/Inc/ |
| A D | mpu_armv8.h | 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
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| /bsp/microchip/samd51-adafruit-metro-m4/bsp/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
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| /bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
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| /bsp/microchip/samc21/bsp/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
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| /bsp/microchip/samd51-seeed-wio-terminal/bsp/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
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| /bsp/msp432e401y-LaunchPad/libraries/Drivers/CMSIS/Include/ |
| A D | mpu_armv8.h | 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
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| /bsp/tae32f5300/Libraries/CMSIS/Include/ |
| A D | mpu_armv8.h | 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
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| /bsp/synwit/libraries/SWM341_CSL/CMSIS/CoreSupport/ |
| A D | mpu_armv8.h | 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
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| /bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
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| /bsp/renesas/ra8m1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/ |
| A D | mpu_armv8.h | 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ argument
|