1 /**************************************************************************//** 2 * @file 3 * @brief Board Control register definitions 4 * @author Energy Micro AS 5 * @version 2.0.1 6 ****************************************************************************** 7 * @section License 8 * <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b> 9 ******************************************************************************* 10 * 11 * Permission is granted to anyone to use this software for any purpose, 12 * including commercial applications, and to alter it and redistribute it 13 * freely, subject to the following restrictions: 14 * 15 * 1. The origin of this software must not be misrepresented; you must not 16 * claim that you wrote the original software. 17 * 2. Altered source versions must be plainly marked as such, and must not be 18 * misrepresented as being the original software. 19 * 3. This notice may not be removed or altered from any source distribution. 20 * 4. The source and compiled code may only be used on Energy Micro "EFM32" 21 * microcontrollers and "EFR4" radios. 22 * 23 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no 24 * obligation to support this Software. Energy Micro AS is providing the 25 * Software "AS IS", with no express or implied warranties of any kind, 26 * including, but not limited to, any implied warranties of merchantability 27 * or fitness for any particular purpose or warranties against infringement 28 * of any proprietary rights of a third party. 29 * 30 * Energy Micro AS will not be liable for any consequential, incidental, or 31 * special damages, or any other relief, or for any claim by any third party, 32 * arising from your use of this Software. 33 * 34 *****************************************************************************/ 35 #ifndef __DVK_BCREGISTERS_H 36 #define __DVK_BCREGISTERS_H 37 38 /***************************************************************************//** 39 * @addtogroup BSP 40 * @{ 41 ******************************************************************************/ 42 43 #include <stdint.h> 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /**************************************************************************//** 50 * Defines FPGA register bank for Energy Micro Development Kit (DVK) board, 51 * i.e. board control registers 52 *****************************************************************************/ 53 #define BC_REGISTER_BASE 0x80000000 /**< Board Controller registers base address */ 54 #define BC_SSD2119_BASE 0x84000000 /**< TFT-LCD controller */ 55 #define BC_PSRAM_BASE 0x88000000 /**< PSRAM base address */ 56 #define BC_FLASH_BASE 0x8C000000 /**< External Flash base address */ 57 58 59 /**************************************************************************//** 60 * Defines bit fields for board control registers 61 *****************************************************************************/ 62 63 /* Define registers in a similar manner to CMSIS standards */ 64 /** Read/Write board controller register */ 65 #define __IO volatile 66 67 /** Board Controller Register definiton */ 68 typedef struct 69 { 70 __IO uint16_t RESERVERD0; /**< 0x00 - Reserved */ 71 __IO uint16_t EM; /**< 0x02 - Energy Mode indicator */ 72 __IO uint16_t MAGIC; /**< 0x04 - Should always read 0xEF32 */ 73 74 __IO uint16_t UIF_LEDS; /**< 0x06 - On board LEDs */ 75 __IO uint16_t UIF_PB; /**< 0x08 - Push button PB0-PB4 status */ 76 __IO uint16_t UIF_DIP; /**< 0x0A - DIP switch status */ 77 __IO uint16_t UIF_JOYSTICK; /**< 0x0C - Joystick presses */ 78 __IO uint16_t UIF_AEM; /**< 0x0E - AEM button */ 79 __IO uint16_t UIF_CTRL; /**< 0x10 - CPLD control register */ 80 __IO uint16_t DISPLAY_CTRL; /**< 0x12 - SSD2119 TFT display control */ 81 __IO uint16_t EBI_CTRL; /**< 0x14 - Extended Address Mode control */ 82 __IO uint16_t ARB_CTRL; /**< 0x16 - Arbiter control, board control or EFM32GG access to display */ 83 __IO uint16_t PERICON; /**< 0x18 - Peripheral Control, on board switches */ 84 __IO uint16_t SPI_DEMUX; /**< 0x1A - SPI DEMUX */ 85 __IO uint16_t RESERVERD1[0x02]; /**< 0x1C - Reserved */ 86 87 __IO uint16_t ADC_WRITE; /**< 0x20 - AEM ADC SPI interface */ 88 __IO uint16_t ADC_STATUS; /**< 0x22 - AEM ADC SPI interface */ 89 __IO uint16_t ADC_READ; /**< 0x24 - AEM ADC SPI interface */ 90 91 __IO uint16_t CLKRST; /**< 0x26 - Clock and reset control */ 92 93 __IO uint16_t HW_VERSION; /**< 0x28 - Hardware version */ 94 __IO uint16_t FW_BUILDNO; /**< 0x2A - Firmware build number */ 95 __IO uint16_t FW_VERSION; /**< 0x2C - Firmware version */ 96 97 __IO uint16_t SCRATCH_COMMON; /**< 0x2E - Shared register between board controller and EFM32 */ 98 99 __IO uint16_t SCRATCH_EFM0; /**< 0x30 - EFM32 accessible registers */ 100 __IO uint16_t SCRATCH_EFM1; /**< 0x32 */ 101 __IO uint16_t SCRATCH_EFM2; /**< 0x34 */ 102 __IO uint16_t SCRATCH_EFM3; /**< 0x36 */ 103 104 __IO uint16_t SCRATCH_BC0; /**< 0x38 - Board Control registers */ 105 __IO uint16_t SCRATCH_BC1; /**< 0x3A */ 106 __IO uint16_t SCRATCH_BC2; /**< 0x3C */ 107 __IO uint16_t SCRATCH_BC3; /**< 0x3E */ 108 109 __IO uint16_t INTFLAG; /**< 0x40 - Interrupt Status flags */ 110 __IO uint16_t INTEN; /**< 0x42 - Interrupt Enable flags */ 111 112 __IO uint16_t RESERVERD3[0x1e]; /**< 0x44 - Reserved */ 113 114 __IO uint16_t BC_MBOX_TXCTRL; /**< 0x80 - BC <-> EFM32 communication channel */ 115 __IO uint16_t BC_MBOX_TXDATA; /**< 0x82 */ 116 __IO uint16_t BC_MBOX_TXSTATUS0; /**< 0x84 */ 117 __IO uint16_t BC_MBOX_TXSTATUS1; /**< 0x86 */ 118 119 __IO uint16_t RESERVED4[0x0d]; /**< 0xa0 - Reserved */ 120 121 __IO uint16_t MBOX_TXCTRL; /**< 0xa2 - BC <-> EFM32 communication channel */ 122 __IO uint16_t MBOX_TXDATA; /**< 0xa4 */ 123 __IO uint16_t MBOX_TXSTATUS0; /**< 0xa6 */ 124 __IO uint16_t MBOX_TXSTATUS1; /**< 0xa8 */ 125 126 __IO uint16_t RESERVED5[0x0b]; /**< 0xaa - Reserved */ 127 128 __IO uint16_t BUF_CTRL; /**< 0xc0 - Buffer Controller Control */ 129 } BC_TypeDef; 130 131 /* Cast into register structure */ 132 #define BC_REGISTER ((BC_TypeDef *) BC_REGISTER_BASE) /**< Register block base */ 133 134 /* Energy Mode indicator */ 135 #define BC_EM_EM0 (0) /**< Indicate EM0 */ 136 #define BC_EM_EM1 (1) /**< Indicate EM1 */ 137 #define BC_EM_EM2 (2) /**< Indicate EM2 */ 138 #define BC_EM_EM3 (3) /**< Indicate EM3 */ 139 #define BC_EM_EM4 (4) /**< Indicate EM4 */ 140 141 /* Magic value */ 142 #define BC_MAGIC_VALUE (0xef32) /**< Magic */ 143 144 /* Push buttons, PB1-PB4 */ 145 #define BC_UIF_PB_MASK (0x000f) /**< Push button mask */ 146 #define BC_UIF_PB1 (1 << 0) /**< Push button PB1 */ 147 #define BC_UIF_PB2 (1 << 1) /**< Push button PB2 */ 148 #define BC_UIF_PB3 (1 << 2) /**< Push button PB3 */ 149 #define BC_UIF_PB4 (1 << 3) /**< Push button PB4 */ 150 151 /* Dip switch */ 152 #define BC_DIPSWITCH_MASK (0x000f) /**< Dip switch mask */ 153 154 /* Joystick directions */ 155 #define BC_UIF_JOYSTICK_MASK (0x001f) /**< Joystick mask */ 156 #define BC_UIF_JOYSTICK_DOWN (1 << 0) /**< Joystick down */ 157 #define BC_UIF_JOYSTICK_RIGHT (1 << 1) /**< Joystick right */ 158 #define BC_UIF_JOYSTICK_UP (1 << 2) /**< Joystick up */ 159 #define BC_UIF_JOYSTICK_LEFT (1 << 3) /**< Joystick left */ 160 #define BC_UIF_JOYSTICK_CENTER (1 << 4) /**< Joystick center button */ 161 162 /* AEM state */ 163 #define BC_UIF_AEM_BC (0) /**< AEM button state, BC controls buttons */ 164 #define BC_UIF_AEM_EFM (1) /**< AEM button state, EFM32 controls buttons */ 165 166 /* Display control */ 167 #define BC_DISPLAY_CTRL_RESET (1 << 1) /**< Reset */ 168 #define BC_DISPLAY_CTRL_POWER_ENABLE (1 << 0) /**< Display Control Power and Backlight Enable */ 169 #define BC_DISPLAY_CTRL_MODE_SHIFT 2 /**< Bit offset value for Display_Mode setting */ 170 #define BC_DISPLAY_CTRL_MODE_8080 (0 << BC_DISPLAY_CTRL_MODE_SHIFT) /**< Address mapped mode */ 171 #define BC_DISPLAY_CTRL_MODE_GENERIC (1 << BC_DISPLAY_CTRL_MODE_SHIFT) /**< Direct Drive + SPI mode */ 172 173 /* EBI control - extended address range enable bit */ 174 #define BC_EBI_CTRL_EXTADDR_MASK (0x0001) /**< Enable extended addressing support */ 175 176 /* Arbiter control - directs access to display controller */ 177 #define BC_ARB_CTRL_SHIFT 0 /**< Bit offset value for ARB_CTRL setting */ 178 #define BC_ARB_CTRL_BC (0 << BC_ARB_CTRL_SHIFT) /**< BC drives display */ 179 #define BC_ARB_CTRL_EBI (1 << BC_ARB_CTRL_SHIFT) /**< EFM32GG EBI drives display, memory mapped or direct drive */ 180 #define BC_ARB_CTRL_SPI (2 << BC_ARB_CTRL_SHIFT) /**< EFM32GG SPI drives display */ 181 182 /* Interrupt flag registers, INTEN and INTFLAG */ 183 #define BC_INTEN_MASK (0x000f) /**< Interrupt enable mask */ 184 #define BC_INTEN_PB (1 << 0) /**< Push Button Interrupt enable */ 185 #define BC_INTEN_DIP (1 << 1) /**< DIP Switch Interrupt enable */ 186 #define BC_INTEN_JOYSTICK (1 << 2) /**< Joystick Interrupt enable */ 187 #define BC_INTEN_AEM (1 << 3) /**< AEM Interrupt enable */ 188 #define BC_INTEN_ETH (1 << 4) /**< Ethernet Interrupt enable */ 189 190 #define BC_INTFLAG_MASK (0x000f) /**< Interrupt flag mask */ 191 #define BC_INTFLAG_PB (1 << 0) /**< Push Button interrupt triggered */ 192 #define BC_INTFLAG_DIP (1 << 1) /**< DIP interrupt triggered */ 193 #define BC_INTFLAG_JOYSTICK (1 << 2) /**< Joystick interrupt triggered */ 194 #define BC_INTFLAG_AEM (1 << 3) /**< AEM Interrupt triggered */ 195 #define BC_INTFLAG_ETH (1 << 4) /**< Ethernet Interrupt triggered */ 196 197 /* Peripheral control registers */ 198 #define BC_PERICON_RS232_SHUTDOWN_SHIFT 13 /**< RS232 enable MUX bit */ 199 #define BC_PERICON_RS232_UART_SHIFT 12 /**< UART enable */ 200 #define BC_PERICON_RS232_LEUART_SHIFT 11 /**< LEUART enable */ 201 #define BC_PERICON_I2C_SHIFT 10 /**< I2C enable */ 202 #define BC_PERICON_I2S_ETH_SEL_SHIFT 9 /**< I2S/ETH/TFT SPI enable */ 203 #define BC_PERICON_I2S_ETH_SHIFT 8 /**< I2S/ETH mux select */ 204 #define BC_PERICON_TRACE_SHIFT 7 /**< ETM Trace enable */ 205 #define BC_PERICON_TOUCH_SHIFT 6 /**< Touch enable */ 206 #define BC_PERICON_AUDIO_IN_SHIFT 5 /**< Audio In enable */ 207 #define BC_PERICON_AUDIO_OUT_SEL_SHIFT 4 /**< Audio Out I2S/DAC select */ 208 #define BC_PERICON_AUDIO_OUT_SHIFT 3 /**< Audio Out enable */ 209 #define BC_PERICON_ANALOG_DIFF_SHIFT 2 /**< Analog Diff enable */ 210 #define BC_PERICON_ANALOG_SE_SHIFT 1 /**< Anallog SE enable */ 211 #define BC_PERICON_SPI_SHIFT 0 /**< Micro-SD SPI enable */ 212 213 /* SPI DEMUX control */ 214 #define BC_SPI_DEMUX_SLAVE_MASK (0x0003) /**< Mask for SPI MUX bits */ 215 #define BC_SPI_DEMUX_SLAVE_AUDIO (0) /**< SPI interface to I2S Audio */ 216 #define BC_SPI_DEMUX_SLAVE_ETHERNET (1) /**< SPI interface to Ethernet controller */ 217 #define BC_SPI_DEMUX_SLAVE_DISPLAY (2) /**< SPI interface to TFT-LCD-SSD2119 controller */ 218 219 /* ADC */ 220 #define BC_ADC_STATUS_DONE (0) /**< ADC Status Done */ 221 #define BC_ADC_STATUS_BUSY (1) /**< ADC Status Busy */ 222 223 /* Clock and Reset Control */ 224 #define BC_CLKRST_FLASH_SHIFT (1 << 1) /**< Flash Reset Control */ 225 #define BC_CLKRST_ETH_SHIFT (1 << 2) /**< Ethernet Reset Control */ 226 227 /* Hardware version information */ 228 #define BC_HW_VERSION_PCB_MASK (0x07f0) /**< PCB Version mask */ 229 #define BC_HW_VERSION_PCB_SHIFT (4) /**< PCB Version shift */ 230 #define BC_HW_VERSION_BOARD_MASK (0x000f) /**< Board version mask */ 231 #define BC_HW_VERSION_BOARD_SHIFT (0) /**< Board version shift */ 232 233 /* Firmware version information */ 234 #define BC_FW_VERSION_MAJOR_MASK (0xf000) /**< FW Version major mask */ 235 #define BC_FW_VERSION_MAJOR_SHIFT (12) /**< FW version major shift */ 236 #define BC_FW_VERSION_MINOR_MASK (0x0f00) /**< FW version minor mask */ 237 #define BC_FW_VERSION_MINOR_SHIFT (8) /**< FW version minor shift */ 238 #define BC_FW_VERSION_PATCHLEVEL_MASK (0x00ff) /**< FW Patchlevel mask */ 239 #define BC_FW_VERSION_PATCHLEVEL_SHIFT (0) /**< FW Patchlevel shift */ 240 241 /* MBOX - BC <-> EFM32 communication */ 242 #define BC_MBOX_TXSTATUS0_FIFOEMPTY (1 << 0) /**< BC/EFM32 communication register */ 243 #define BC_MBOX_TXSTATUS0_FIFOFULL (1 << 1) /**< BC/EFM32 communication register */ 244 #define BC_MBOX_TXSTATUS0_FIFOUNDERFLOW (1 << 4) /**< BC/EFM32 communication register */ 245 #define BC_MBOX_TXSTATUS0_FIFOOVERFLOW (1 << 5) /**< BC/EFM32 communication register */ 246 247 #define BC_MBOX_TXSTATUS1_WORDCOUNT_MASK (0x07FF) /**< BC/EFM32 communication register */ 248 249 /* Buffer Controller */ 250 #define BC_BUF_CTRL_CS_ENABLE (1 << 0) /**< BC/EFM32 communication register */ 251 252 #ifdef __cplusplus 253 } 254 #endif 255 256 /** @} (end group BSP) */ 257 258 #endif 259