1 /*
2  * Copyright (c) 2006-2018, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2017-5-30      Bernard      the first version
9  */
10 
11 #ifndef BOARD_H__
12 #define BOARD_H__
13 
14 #include <stdint.h>
15 
16 extern unsigned char __bss_start__;
17 extern unsigned char __bss_end__;
18 
19 #define RT_HW_HEAP_BEGIN    (void*)&__bss_end__
20 #define RT_HW_HEAP_END      (void*)(0x20000000 + 0x00030000 - 0x1800)
21 
22 #define BOARD_USDHC0_BASEADDR USDHC0
23 #define BOARD_USDHC_CD_PORT_BASE PORTC
24 #define BOARD_USDHC_CD_GPIO_BASE GPIOC
25 #define BOARD_USDHC_CD_GPIO_PIN 27
26 #define BOARD_USDHC_CD_PORT_IRQ PORTC_IRQn
27 #define BOARD_USDHC_CD_PORT_IRQ_HANDLER PORTC_IRQHandler
28 
29 #define BOARD_USDHC_CD_GPIO_INIT()                                                                                \
30     {                                                                                                             \
31         gpio_pin_config_t sw_config = {kGPIO_DigitalInput, 0};                                                    \
32         GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config);                              \
33         PORT_SetPinInterruptConfig(BOARD_USDHC_CD_PORT_BASE, BOARD_USDHC_CD_GPIO_PIN, kPORT_InterruptRisingEdge); \
34     }
35 
36 #define BOARD_USDHC_CD_STATUS() (GPIO_ReadPinInput(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
37 
38 #define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_GetPinsInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
39 #define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_ClearPinsInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
40 #define BOARD_USDHC_CARD_INSERT_CD_LEVEL (1U)
41 #define BOARD_USDHC0_CLK_FREQ (CLOCK_GetIpFreq(kCLOCK_Sdhc0))
42 
43 #define BOARD_SD_HOST_BASEADDR BOARD_USDHC0_BASEADDR
44 #define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC0_CLK_FREQ
45 #define BOARD_SD_HOST_IRQ USDHC0_IRQn
46 #define BOARD_SD_SUPPORT_180V (0U)
47 #define BOARD_MMC_HOST_BASEADDR BOARD_USDHC0_BASEADDR
48 #define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC0_CLK_FREQ
49 #define BOARD_MMC_HOST_IRQ USDHC0_IRQn
50 #define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindows270to360
51 #define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
52 #define BOARD_MMC_PIN_CONFIG(speed, strength)
53 
54 /* this define not implement, due to EVK board have no power reset circuit */
55 #define BOARD_SD_POWER_RESET_GPIO ()
56 #define BOARD_SD_POWER_RESET_GPIO_PIN ()
57 #define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT()
58 #define BOARD_USDHC_SDCARD_POWER_CONTROL(state)
59 #define BOARD_SD_PIN_CONFIG(speed, strength)
60 #define BOARD_USDHC_MMCCARD_POWER_CONTROL(enable)
61 #define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT()
62 
63 void rt_hw_board_init(void);
64 
65 #endif
66