1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2017-01-01 Urey first version 9 */ 10 11 #ifndef __CORE_CK802_H_GENERIC 12 #define __CORE_CK802_H_GENERIC 13 14 #include <stdint.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /******************************************************************************* 21 * CSI definitions 22 ******************************************************************************/ 23 /** 24 \ingroup Ck802 25 @{ 26 */ 27 28 /* CSI CK802 definitions */ 29 #define __CK802_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */ 30 #define __CK802_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */ 31 #define __CK802_CSI_VERSION ((__CK802_CSI_VERSION_MAIN << 16U) | \ 32 __CK802_CSI_VERSION_SUB ) /*!< CSI HAL version number */ 33 34 #define __CK80X (0x02U) /*!< CK80X Core */ 35 36 /** __FPU_USED indicates whether an FPU is used or not. 37 This core does not support an FPU at all 38 */ 39 #define __FPU_USED 0U 40 41 #if defined ( __GNUC__ ) 42 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 43 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 44 #endif 45 #endif 46 47 #include "csi_gcc.h" 48 49 #ifdef __cplusplus 50 } 51 #endif 52 53 #endif /* __CORE_CK802_H_GENERIC */ 54 55 #ifndef __CSI_GENERIC 56 57 #ifndef __CORE_CK802_H_DEPENDANT 58 #define __CORE_CK802_H_DEPENDANT 59 60 #ifdef __cplusplus 61 extern "C" { 62 #endif 63 64 /* check device defines and use defaults */ 65 //#if defined __CHECK_DEVICE_DEFINES 66 #ifndef __CK802_REV 67 #define __CK802_REV 0x0000U 68 //#warning "__CK802_REV not defined in device header file; using default!" 69 #endif 70 71 #ifndef __NVIC_PRIO_BITS 72 #define __NVIC_PRIO_BITS 2U 73 //#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 74 #endif 75 76 #ifndef __Vendor_SysTickConfig 77 #define __Vendor_SysTickConfig 0U 78 //#warning "__Vendor_SysTickConfig not defined in device header file; using default!" 79 #endif 80 81 #ifndef __GSR_GCR_PRESENT 82 #define __GSR_GCR_PRESENT 0U 83 //#warning "__GSR_GCR_PRESENT not defined in device header file; using default!" 84 #endif 85 86 #ifndef __MGU_PRESENT 87 #define __MGU_PRESENT 0U 88 //#warning "__MGU_PRESENT not defined in device header file; using default!" 89 #endif 90 //#endif 91 92 /* IO definitions (access restrictions to peripheral registers) */ 93 /** 94 \defgroup CSI_glob_defs CSI Global Defines 95 96 <strong>IO Type Qualifiers</strong> are used 97 \li to specify the access to peripheral variables. 98 \li for automatic generation of peripheral register debug information. 99 */ 100 #ifdef __cplusplus 101 #define __I volatile /*!< Defines 'read only' permissions */ 102 #else 103 #define __I volatile const /*!< Defines 'read only' permissions */ 104 #endif 105 #define __O volatile /*!< Defines 'write only' permissions */ 106 #define __IO volatile /*!< Defines 'read / write' permissions */ 107 108 /* following defines should be used for structure members */ 109 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 110 #define __OM volatile /*! Defines 'write only' structure member permissions */ 111 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 112 113 /*@} end of group CK802 */ 114 115 /******************************************************************************* 116 * Register Abstraction 117 Core Register contain: 118 - Core Register 119 - Core NVIC Register 120 - Core SCB Register 121 - Core SysTick Register 122 ******************************************************************************/ 123 /** 124 \defgroup CSI_core_register Defines and Type Definitions 125 \brief Type definitions and defines for CK80X processor based devices. 126 */ 127 128 /** 129 \ingroup CSI_core_register 130 \defgroup CSI_CORE Status and Control Registers 131 \brief Core Register type definitions. 132 @{ 133 */ 134 135 /** 136 \brief 访问处理器状态寄存器(PSR)的联合体定义. 137 */ 138 typedef union 139 { 140 struct 141 { 142 uint32_t C: 1; /*!< bit: 0 条件码／进位位 */ 143 uint32_t _reserved0: 5; /*!< bit: 2.. 5 保留 */ 144 uint32_t IE: 1; /*!< bit: 6 中断有效控制位 */ 145 uint32_t IC: 1; /*!< bit: 7 中断控制位 */ 146 uint32_t EE: 1; /*!< bit: 8 异常有效控制位 */ 147 uint32_t MM: 1; /*!< bit: 9 不对齐异常掩盖位 */ 148 uint32_t _reserved1: 6; /*!< bit: 10..15 保留 */ 149 uint32_t VEC: 8; /*!< bit: 16..23 异常事件向量值 */ 150 uint32_t _reserved2: 7; /*!< bit: 24..30 保留 */ 151 uint32_t S: 1; /*!< bit: 31 超级用户模式设置位 */ 152 } b; /*!< Structure 用来按位访问 */ 153 uint32_t w; /*!< Type 整个寄存器访问 */ 154 } PSR_Type; 155 156 /* PSR Register Definitions */ 157 #define PSR_S_Pos 31U /*!< PSR: S Position */ 158 #define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */ 159 160 #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */ 161 #define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */ 162 163 #define PSR_MM_Pos 9U /*!< PSR: MM Position */ 164 #define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */ 165 166 #define PSR_EE_Pos 8U /*!< PSR: EE Position */ 167 #define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */ 168 169 #define PSR_IC_Pos 7U /*!< PSR: IC Position */ 170 #define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */ 171 172 #define PSR_IE_Pos 6U /*!< PSR: IE Position */ 173 #define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */ 174 175 #define PSR_C_Pos 0U /*!< PSR: C Position */ 176 #define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */ 177 178 /** 179 \brief 访问高速缓存配置寄存器(CCR, CR<18, 0>)的联合体定义. 180 */ 181 typedef union 182 { 183 struct 184 { 185 uint32_t MP: 1; /*!< bit: 0 内存保护设置位 */ 186 uint32_t _reserved0: 6; /*!< bit: 1.. 6 保留 */ 187 uint32_t BE: 1; /*!< bit: 7 Endian模式 */ 188 uint32_t SCK: 3; /*!< bit: 8..10 系统和处理器的时钟比 */ 189 uint32_t _reserved1: 2; /*!< bit: 11..12 保留 */ 190 uint32_t BE_V2: 1; /*!< bit: 13 V2版本大小端 */ 191 uint32_t _reserved2: 18; /*!< bit: 14..31 保留 */ 192 } b; /*!< Structure 用来按位访问 */ 193 uint32_t w; /*!< Type 整个寄存器访问 */ 194 } CCR_Type; 195 196 /* CCR Register Definitions */ 197 #define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */ 198 #define CCR_BE_V2_Msk (0x1UL << CCR_ISR_Pos) /*!< CCR: BE_V2 Mask */ 199 200 #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */ 201 #define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */ 202 203 #define CCR_BE_Pos 7U /*!< CCR: BE Position */ 204 #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */ 205 206 #define CCR_MP_Pos 0U /*!< CCR: MP Position */ 207 #define CCR_MP_Msk (0x1UL << CCR_MP_Pos) /*!< CCR: MP Mask */ 208 209 /** 210 \brief 访问可高缓和访问权限配置寄存器(CAPR, CR<19,0>)的联合体定义.. 211 */ 212 typedef union 213 { 214 struct 215 { 216 uint32_t X0: 1; /*!< bit: 0 不可执行属性设置位 */ 217 uint32_t X1: 1; /*!< bit: 1 不可执行属性设置位 */ 218 uint32_t X2: 1; /*!< bit: 2 不可执行属性设置位 */ 219 uint32_t X3: 1; /*!< bit: 3 不可执行属性设置位 */ 220 uint32_t X4: 1; /*!< bit: 4 不可执行属性设置位 */ 221 uint32_t X5: 1; /*!< bit: 5 不可执行属性设置位 */ 222 uint32_t X6: 1; /*!< bit: 6 不可执行属性设置位 */ 223 uint32_t X7: 1; /*!< bit: 7 不可执行属性设置位 */ 224 uint32_t AP0: 2; /*!< bit: 8.. 9 访问权限设置位 */ 225 uint32_t AP1: 2; /*!< bit: 10..11 访问权限设置位 */ 226 uint32_t AP2: 2; /*!< bit: 12..13 访问权限设置位 */ 227 uint32_t AP3: 2; /*!< bit: 14..15 访问权限设置位 */ 228 uint32_t AP4: 2; /*!< bit: 16..17 访问权限设置位 */ 229 uint32_t AP5: 2; /*!< bit: 18..19 访问权限设置位 */ 230 uint32_t AP6: 2; /*!< bit: 20..21 访问权限设置位 */ 231 uint32_t AP7: 2; /*!< bit: 22..23 访问权限设置位 */ 232 uint32_t S0: 1; /*!< bit: 24 安全属性设置位 */ 233 uint32_t S1: 1; /*!< bit: 25 安全属性设置位 */ 234 uint32_t S2: 1; /*!< bit: 26 安全属性设置位 */ 235 uint32_t S3: 1; /*!< bit: 27 安全属性设置位 */ 236 uint32_t S4: 1; /*!< bit: 28 安全属性设置位 */ 237 uint32_t S5: 1; /*!< bit: 29 安全属性设置位 */ 238 uint32_t S6: 1; /*!< bit: 30 安全属性设置位 */ 239 uint32_t S7: 1; /*!< bit: 31 安全属性设置位 */ 240 } b; /*!< Structure 用来按位访问 */ 241 uint32_t w; /*!< Type 整个寄存器访问 */ 242 } CAPR_Type; 243 244 /* CAPR Register Definitions */ 245 #define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */ 246 #define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */ 247 248 #define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */ 249 #define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */ 250 251 #define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */ 252 #define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */ 253 254 #define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */ 255 #define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */ 256 257 #define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */ 258 #define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */ 259 260 #define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */ 261 #define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */ 262 263 #define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */ 264 #define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */ 265 266 #define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */ 267 #define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */ 268 269 #define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */ 270 #define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */ 271 272 #define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */ 273 #define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */ 274 275 #define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */ 276 #define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */ 277 278 #define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */ 279 #define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */ 280 281 #define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */ 282 #define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */ 283 284 #define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */ 285 #define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */ 286 287 #define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */ 288 #define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */ 289 290 #define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */ 291 #define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */ 292 293 #define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */ 294 #define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */ 295 296 #define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */ 297 #define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */ 298 299 #define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */ 300 #define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */ 301 302 #define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */ 303 #define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */ 304 305 #define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */ 306 #define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */ 307 308 #define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */ 309 #define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */ 310 311 #define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */ 312 #define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */ 313 314 #define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */ 315 #define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */ 316 317 /** 318 \brief 访问保护区控制寄存器(PACR, CR<20,0>)的联合体定义. 319 */ 320 typedef union 321 { 322 struct 323 { 324 uint32_t E: 1; /*!< bit: 0 保护区有效设置 */ 325 uint32_t Size: 5; /*!< bit: 1.. 5 保护区大小 */ 326 uint32_t _reserved0: 4; /*!< bit: 6.. 9 保留 */ 327 uint32_t base_addr: 22; /*!< bit: 10..31 保护区地址的高位 */ 328 } b; /*!< Structure 用来按位访问 */ 329 uint32_t w; /*!< Type 整个寄存器访问 */ 330 } PACR_Type; 331 332 /* PACR Register Definitions */ 333 #define PACR_BASE_ADDR_Pos 10U /*!< PACR: base_addr Position */ 334 #define PACK_BASE_ADDR_Msk (0x3FFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */ 335 336 #define PACR_SIZE_Pos 1U /*!< PACR: Size Position */ 337 #define PACK_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */ 338 339 #define PACR_E_Pos 0U /*!< PACR: E Position */ 340 #define PACK_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */ 341 342 /** 343 \brief 访问保护区选择寄存器(PRSR,CR<21,0>)的联合体定义. 344 */ 345 typedef union 346 { 347 struct 348 { 349 uint32_t RID: 3; /*!< bit: 0.. 2 保护区索引值 */ 350 uint32_t _reserved0: 30; /*!< bit: 3..31 保留 */ 351 } b; /*!< Structure 用来按位访问 */ 352 uint32_t w; /*!< Type 整个寄存器访问 */ 353 } PRSR_Type; 354 355 /* PRSR Register Definitions */ 356 #define PRSR_RID_Pos 0U /*!< PRSR: RID Position */ 357 #define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */ 358 359 /*@} end of group CSI_CORE */ 360 361 362 /** 363 \ingroup CSI_core_register 364 \defgroup CSI_NVIC Vectored Interrupt Controller (NVIC) 365 \brief Type definitions for the NVIC Registers 366 @{ 367 */ 368 369 /** 370 \brief 访问矢量中断控制器的结构体. 371 */ 372 typedef struct 373 { 374 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) 中断使能设置寄存器 */ 375 uint32_t RESERVED0[15U]; 376 __IOM uint32_t IWER[1U]; /*!< Offset: 0x040 (R/W) 中断低功耗唤醒设置寄存器 */ 377 uint32_t RESERVED1[15U]; 378 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) 中断使能清除寄存器 */ 379 uint32_t RESERVED2[15U]; 380 __IOM uint32_t IWDR[1U]; /*!< Offset: 0x0c0 (R/W) 中断低功耗唤醒清除寄存器 */ 381 uint32_t RESERVED3[15U]; 382 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) 中断等待设置寄存器 */ 383 uint32_t RESERVED4[15U]; 384 __IOM uint32_t ISSR[1U]; /*!< Offset: 0x140 (R/W) 安全中断使能设置寄存器 */ 385 uint32_t RESERVED5[15U]; 386 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) 中断等待清除寄存器 */ 387 uint32_t RESERVED6[31U]; 388 __IOM uint32_t IABR[1U]; /*!< Offset: 0x200 (R/W) 中断响应状态寄存器 */ 389 uint32_t RESERVED7[63U]; 390 __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) 中断优先级设置寄存器 */ 391 uint32_t RESERVED8[504U]; 392 __IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) 中断状态寄存器 */ 393 __IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) 中断优先级阈值寄存器 */ 394 } NVIC_Type; 395 396 /*@} end of group CSI_NVIC */ 397 398 /** 399 \ingroup CSI_core_register 400 \defgroup CSI_SysTick System Tick Timer (CORET) 401 \brief Type definitions for the System Timer Registers. 402 @{ 403 */ 404 405 /** 406 \brief 访问系统计时器的数据结构. 407 */ 408 typedef struct 409 { 410 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) 控制状态寄存器 */ 411 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) 回填值寄存器 */ 412 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) 当前值寄存器 */ 413 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) 校准寄存器 */ 414 } CORET_Type; 415 416 /* CORET Control / Status Register Definitions */ 417 #define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */ 418 #define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */ 419 420 #define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */ 421 #define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */ 422 423 #define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */ 424 #define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */ 425 426 #define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */ 427 #define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */ 428 429 /* CORET Reload Register Definitions */ 430 #define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */ 431 #define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */ 432 433 /* CORET Current Register Definitions */ 434 #define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */ 435 #define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */ 436 437 /* CORET Calibration Register Definitions */ 438 #define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */ 439 #define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */ 440 441 #define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */ 442 #define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */ 443 444 #define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */ 445 #define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */ 446 447 /*@} end of group CSI_SysTick */ 448 449 /** 450 \ingroup CSI_core_register 451 \defgroup CSI_DCC 452 \brief Type definitions for the DCC. 453 @{ 454 */ 455 456 /** 457 \brief 访问DCC的数据结构. 458 */ 459 typedef struct 460 { 461 uint32_t RESERVED0[13U]; 462 __IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */ 463 __IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */ 464 uint32_t RESERVED1[6U]; 465 union 466 { 467 __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) 数据交换寄存器 CPU读*/ 468 __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) 数据交换寄存器 CPU写*/ 469 }; 470 471 } DCC_Type; 472 473 #define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */ 474 #define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */ 475 476 #define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */ 477 #define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */ 478 479 #define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */ 480 #define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */ 481 482 #define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */ 483 #define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */ 484 485 /*@} end of group CSI_DCC */ 486 487 488 /** 489 \ingroup CSI_core_register 490 \defgroup CSI_core_bitfield Core register bit field macros 491 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 492 @{ 493 */ 494 495 /** 496 \brief Mask and shift a bit field value for use in a register bit range. 497 \param[in] field Name of the register bit field. 498 \param[in] value Value of the bit field. 499 \return Masked and shifted value. 500 */ 501 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) 502 503 /** 504 \brief Mask and shift a register value to extract a bit filed value. 505 \param[in] field Name of the register bit field. 506 \param[in] value Value of register. 507 \return Masked and shifted bit field value. 508 */ 509 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) 510 511 /*@} end of group CSI_core_bitfield */ 512 513 /** 514 \ingroup CSI_core_register 515 \defgroup CSI_core_base Core Definitions 516 \brief Definitions for base addresses, unions, and structures. 517 @{ 518 */ 519 520 /* Memory mapping of CK802 Hardware */ 521 #define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */ 522 #define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */ 523 #define NVIC_BASE (TCIP_BASE + 0x0100UL) /*!< NVIC Base Address */ 524 #define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */ 525 526 #define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */ 527 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 528 #define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */ 529 530 /*@} */ 531 532 #ifdef __cplusplus 533 } 534 #endif 535 536 #endif /* __CORE_CK802_H_DEPENDANT */ 537 538 #endif /* __CSI_GENERIC */ 539