1;/*****************************************************************************
2; * @file:    startup_MK70F12.s
3; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
4; *           MK70F12
5; * @version: 1.5
6; * @date:    2012-10-19
7; *
8; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
9;*
10; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
11; *
12; *****************************************************************************/
13
14
15; <h> Stack Configuration
16;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
17; </h>
18
19Stack_Size      EQU     0x00000400
20
21                AREA    STACK, NOINIT, READWRITE, ALIGN=3
22Stack_Mem       SPACE   Stack_Size
23__initial_sp
24
25
26; <h> Heap Configuration
27;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
28; </h>
29
30Heap_Size       EQU     0x00000000
31
32                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
33__heap_base
34Heap_Mem        SPACE   Heap_Size
35__heap_limit
36
37                PRESERVE8
38                THUMB
39
40
41; Vector Table Mapped to Address 0 at Reset
42
43                AREA    RESET, DATA, READONLY
44                EXPORT  __Vectors
45                EXPORT  __Vectors_End
46                EXPORT  __Vectors_Size
47
48__Vectors       DCD     __initial_sp  ; Top of Stack
49                DCD     Reset_Handler  ; Reset Handler
50                DCD     NMI_Handler  ; NMI Handler
51                DCD     HardFault_Handler  ; Hard Fault Handler
52                DCD     MemManage_Handler  ; MPU Fault Handler
53                DCD     BusFault_Handler  ; Bus Fault Handler
54                DCD     UsageFault_Handler  ; Usage Fault Handler
55                DCD     0  ; Reserved
56                DCD     0  ; Reserved
57                DCD     0  ; Reserved
58                DCD     0  ; Reserved
59                DCD     SVC_Handler  ; SVCall Handler
60                DCD     DebugMon_Handler  ; Debug Monitor Handler
61                DCD     0  ; Reserved
62                DCD     PendSV_Handler  ; PendSV Handler
63                DCD     SysTick_Handler  ; SysTick Handler
64
65                ; External Interrupts
66                DCD     DMA0_IRQHandler  ; DMA Channel 0 Transfer Complete
67                DCD     DMA1_IRQHandler  ; DMA Channel 1 Transfer Complete
68                DCD     DMA2_IRQHandler  ; DMA Channel 2 Transfer Complete
69                DCD     DMA3_IRQHandler  ; DMA Channel 3 Transfer Complete
70                DCD     DMA4_IRQHandler  ; DMA Channel 4 Transfer Complete
71                DCD     DMA5_IRQHandler  ; DMA Channel 5 Transfer Complete
72                DCD     DMA6_IRQHandler  ; DMA Channel 6 Transfer Complete
73                DCD     DMA7_IRQHandler  ; DMA Channel 7 Transfer Complete
74                DCD     DMA8_IRQHandler  ; DMA Channel 8 Transfer Complete
75                DCD     DMA9_IRQHandler  ; DMA Channel 9 Transfer Complete
76                DCD     DMA10_IRQHandler  ; DMA Channel 10 Transfer Complete
77                DCD     DMA11_IRQHandler  ; DMA Channel 11 Transfer Complete
78                DCD     DMA12_IRQHandler  ; DMA Channel 12 Transfer Complete
79                DCD     DMA13_IRQHandler  ; DMA Channel 13 Transfer Complete
80                DCD     DMA14_IRQHandler  ; DMA Channel 14 Transfer Complete
81                DCD     DMA15_IRQHandler  ; DMA Channel 15 Transfer Complete
82                DCD     DMA_Error_IRQHandler  ; DMA Error Interrupt
83                DCD     MCM_IRQHandler  ; Normal Interrupt
84                DCD     FTFE_IRQHandler  ; FTFE Command complete interrupt
85                DCD     Read_Collision_IRQHandler  ; Read Collision Interrupt
86                DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
87                DCD     LLW_IRQHandler  ; Low Leakage Wakeup
88                DCD     Watchdog_IRQHandler  ; WDOG Interrupt
89                DCD     RNG_IRQHandler  ; RNG Interrupt
90                DCD     I2C0_IRQHandler  ; I2C0 interrupt
91                DCD     I2C1_IRQHandler  ; I2C1 interrupt
92                DCD     SPI0_IRQHandler  ; SPI0 Interrupt
93                DCD     SPI1_IRQHandler  ; SPI1 Interrupt
94                DCD     I2S0_Tx_IRQHandler  ; I2S0 transmit interrupt
95                DCD     I2S0_Rx_IRQHandler  ; I2S0 receive interrupt
96                DCD     UART0_LON_IRQHandler  ; UART0 LON interrupt
97                DCD     UART0_RX_TX_IRQHandler  ; UART0 Receive/Transmit interrupt
98                DCD     UART0_ERR_IRQHandler  ; UART0 Error interrupt
99                DCD     UART1_RX_TX_IRQHandler  ; UART1 Receive/Transmit interrupt
100                DCD     UART1_ERR_IRQHandler  ; UART1 Error interrupt
101                DCD     UART2_RX_TX_IRQHandler  ; UART2 Receive/Transmit interrupt
102                DCD     UART2_ERR_IRQHandler  ; UART2 Error interrupt
103                DCD     UART3_RX_TX_IRQHandler  ; UART3 Receive/Transmit interrupt
104                DCD     UART3_ERR_IRQHandler  ; UART3 Error interrupt
105                DCD     ADC0_IRQHandler  ; ADC0 interrupt
106                DCD     CMP0_IRQHandler  ; CMP0 interrupt
107                DCD     CMP1_IRQHandler  ; CMP1 interrupt
108                DCD     FTM0_IRQHandler  ; FTM0 fault, overflow and channels interrupt
109                DCD     FTM1_IRQHandler  ; FTM1 fault, overflow and channels interrupt
110                DCD     FTM2_IRQHandler  ; FTM2 fault, overflow and channels interrupt
111                DCD     CMT_IRQHandler  ; CMT interrupt
112                DCD     RTC_IRQHandler  ; RTC interrupt
113                DCD     RTC_Seconds_IRQHandler  ; RTC seconds interrupt
114                DCD     PIT0_IRQHandler  ; PIT timer channel 0 interrupt
115                DCD     PIT1_IRQHandler  ; PIT timer channel 1 interrupt
116                DCD     PIT2_IRQHandler  ; PIT timer channel 2 interrupt
117                DCD     PIT3_IRQHandler  ; PIT timer channel 3 interrupt
118                DCD     PDB0_IRQHandler  ; PDB0 Interrupt
119                DCD     USB0_IRQHandler  ; USB0 interrupt
120                DCD     USBDCD_IRQHandler  ; USBDCD Interrupt
121                DCD     Reserved71_IRQHandler  ; Reserved interrupt 71
122                DCD     DAC0_IRQHandler  ; DAC0 interrupt
123                DCD     MCG_IRQHandler  ; MCG Interrupt
124                DCD     LPTimer_IRQHandler  ; LPTimer interrupt
125                DCD     PORTA_IRQHandler  ; Port A interrupt
126                DCD     PORTB_IRQHandler  ; Port B interrupt
127                DCD     PORTC_IRQHandler  ; Port C interrupt
128                DCD     PORTD_IRQHandler  ; Port D interrupt
129                DCD     PORTE_IRQHandler  ; Port E interrupt
130                DCD     SWI_IRQHandler  ; Software interrupt
131                DCD     SPI2_IRQHandler  ; SPI2 Interrupt
132                DCD     UART4_RX_TX_IRQHandler  ; UART4 Receive/Transmit interrupt
133                DCD     UART4_ERR_IRQHandler  ; UART4 Error interrupt
134                DCD     UART5_RX_TX_IRQHandler  ; UART5 Receive/Transmit interrupt
135                DCD     UART5_ERR_IRQHandler  ; UART5 Error interrupt
136                DCD     CMP2_IRQHandler  ; CMP2 interrupt
137                DCD     FTM3_IRQHandler  ; FTM3 fault, overflow and channels interrupt
138                DCD     DAC1_IRQHandler  ; DAC1 interrupt
139                DCD     ADC1_IRQHandler  ; ADC1 interrupt
140                DCD     I2C2_IRQHandler  ; I2C2 interrupt
141                DCD     CAN0_ORed_Message_buffer_IRQHandler  ; CAN0 OR'd message buffers interrupt
142                DCD     CAN0_Bus_Off_IRQHandler  ; CAN0 bus off interrupt
143                DCD     CAN0_Error_IRQHandler  ; CAN0 error interrupt
144                DCD     CAN0_Tx_Warning_IRQHandler  ; CAN0 Tx warning interrupt
145                DCD     CAN0_Rx_Warning_IRQHandler  ; CAN0 Rx warning interrupt
146                DCD     CAN0_Wake_Up_IRQHandler  ; CAN0 wake up interrupt
147                DCD     SDHC_IRQHandler  ; SDHC interrupt
148                DCD     ENET_1588_Timer_IRQHandler  ; Ethernet MAC IEEE 1588 Timer Interrupt
149                DCD     ENET_Transmit_IRQHandler  ; Ethernet MAC Transmit Interrupt
150                DCD     ENET_Receive_IRQHandler  ; Ethernet MAC Receive Interrupt
151                DCD     ENET_Error_IRQHandler  ; Ethernet MAC Error and miscelaneous Interrupt
152                DCD     DefaultISR  ; 102
153                DCD     DefaultISR  ; 103
154                DCD     DefaultISR  ; 104
155                DCD     DefaultISR  ; 105
156                DCD     DefaultISR  ; 106
157                DCD     DefaultISR  ; 107
158                DCD     DefaultISR  ; 108
159                DCD     DefaultISR  ; 109
160                DCD     DefaultISR  ; 110
161                DCD     DefaultISR  ; 111
162                DCD     DefaultISR  ; 112
163                DCD     DefaultISR  ; 113
164                DCD     DefaultISR  ; 114
165                DCD     DefaultISR  ; 115
166                DCD     DefaultISR  ; 116
167                DCD     DefaultISR  ; 117
168                DCD     DefaultISR  ; 118
169                DCD     DefaultISR  ; 119
170                DCD     DefaultISR  ; 120
171                DCD     DefaultISR  ; 121
172                DCD     DefaultISR  ; 122
173                DCD     DefaultISR  ; 123
174                DCD     DefaultISR  ; 124
175                DCD     DefaultISR  ; 125
176                DCD     DefaultISR  ; 126
177                DCD     DefaultISR  ; 127
178                DCD     DefaultISR  ; 128
179                DCD     DefaultISR  ; 129
180                DCD     DefaultISR  ; 130
181                DCD     DefaultISR  ; 131
182                DCD     DefaultISR  ; 132
183                DCD     DefaultISR  ; 133
184                DCD     DefaultISR  ; 134
185                DCD     DefaultISR  ; 135
186                DCD     DefaultISR  ; 136
187                DCD     DefaultISR  ; 137
188                DCD     DefaultISR  ; 138
189                DCD     DefaultISR  ; 139
190                DCD     DefaultISR  ; 140
191                DCD     DefaultISR  ; 141
192                DCD     DefaultISR  ; 142
193                DCD     DefaultISR  ; 143
194                DCD     DefaultISR  ; 144
195                DCD     DefaultISR  ; 145
196                DCD     DefaultISR  ; 146
197                DCD     DefaultISR  ; 147
198                DCD     DefaultISR  ; 148
199                DCD     DefaultISR  ; 149
200                DCD     DefaultISR  ; 150
201                DCD     DefaultISR  ; 151
202                DCD     DefaultISR  ; 152
203                DCD     DefaultISR  ; 153
204                DCD     DefaultISR  ; 154
205                DCD     DefaultISR  ; 155
206                DCD     DefaultISR  ; 156
207                DCD     DefaultISR  ; 157
208                DCD     DefaultISR  ; 158
209                DCD     DefaultISR  ; 159
210                DCD     DefaultISR  ; 160
211                DCD     DefaultISR  ; 161
212                DCD     DefaultISR  ; 162
213                DCD     DefaultISR  ; 163
214                DCD     DefaultISR  ; 164
215                DCD     DefaultISR  ; 165
216                DCD     DefaultISR  ; 166
217                DCD     DefaultISR  ; 167
218                DCD     DefaultISR  ; 168
219                DCD     DefaultISR  ; 169
220                DCD     DefaultISR  ; 170
221                DCD     DefaultISR  ; 171
222                DCD     DefaultISR  ; 172
223                DCD     DefaultISR  ; 173
224                DCD     DefaultISR  ; 174
225                DCD     DefaultISR  ; 175
226                DCD     DefaultISR  ; 176
227                DCD     DefaultISR  ; 177
228                DCD     DefaultISR  ; 178
229                DCD     DefaultISR  ; 179
230                DCD     DefaultISR  ; 180
231                DCD     DefaultISR  ; 181
232                DCD     DefaultISR  ; 182
233                DCD     DefaultISR  ; 183
234                DCD     DefaultISR  ; 184
235                DCD     DefaultISR  ; 185
236                DCD     DefaultISR  ; 186
237                DCD     DefaultISR  ; 187
238                DCD     DefaultISR  ; 188
239                DCD     DefaultISR  ; 189
240                DCD     DefaultISR  ; 190
241                DCD     DefaultISR  ; 191
242                DCD     DefaultISR  ; 192
243                DCD     DefaultISR  ; 193
244                DCD     DefaultISR  ; 194
245                DCD     DefaultISR  ; 195
246                DCD     DefaultISR  ; 196
247                DCD     DefaultISR  ; 197
248                DCD     DefaultISR  ; 198
249                DCD     DefaultISR  ; 199
250                DCD     DefaultISR  ; 200
251                DCD     DefaultISR  ; 201
252                DCD     DefaultISR  ; 202
253                DCD     DefaultISR  ; 203
254                DCD     DefaultISR  ; 204
255                DCD     DefaultISR  ; 205
256                DCD     DefaultISR  ; 206
257                DCD     DefaultISR  ; 207
258                DCD     DefaultISR  ; 208
259                DCD     DefaultISR  ; 209
260                DCD     DefaultISR  ; 210
261                DCD     DefaultISR  ; 211
262                DCD     DefaultISR  ; 212
263                DCD     DefaultISR  ; 213
264                DCD     DefaultISR  ; 214
265                DCD     DefaultISR  ; 215
266                DCD     DefaultISR  ; 216
267                DCD     DefaultISR  ; 217
268                DCD     DefaultISR  ; 218
269                DCD     DefaultISR  ; 219
270                DCD     DefaultISR  ; 220
271                DCD     DefaultISR  ; 221
272                DCD     DefaultISR  ; 222
273                DCD     DefaultISR  ; 223
274                DCD     DefaultISR  ; 224
275                DCD     DefaultISR  ; 225
276                DCD     DefaultISR  ; 226
277                DCD     DefaultISR  ; 227
278                DCD     DefaultISR  ; 228
279                DCD     DefaultISR  ; 229
280                DCD     DefaultISR  ; 230
281                DCD     DefaultISR  ; 231
282                DCD     DefaultISR  ; 232
283                DCD     DefaultISR  ; 233
284                DCD     DefaultISR  ; 234
285                DCD     DefaultISR  ; 235
286                DCD     DefaultISR  ; 236
287                DCD     DefaultISR  ; 237
288                DCD     DefaultISR  ; 238
289                DCD     DefaultISR  ; 239
290                DCD     DefaultISR  ; 240
291                DCD     DefaultISR  ; 241
292                DCD     DefaultISR  ; 242
293                DCD     DefaultISR  ; 243
294                DCD     DefaultISR  ; 244
295                DCD     DefaultISR  ; 245
296                DCD     DefaultISR  ; 246
297                DCD     DefaultISR  ; 247
298                DCD     DefaultISR  ; 248
299                DCD     DefaultISR  ; 249
300                DCD     DefaultISR  ; 250
301                DCD     DefaultISR  ; 251
302                DCD     DefaultISR  ; 252
303                DCD     DefaultISR  ; 253
304                DCD     DefaultISR  ; 254
305                DCD     DefaultISR  ; 255
306__Vectors_End
307
308__Vectors_Size  EQU     __Vectors_End - __Vectors
309
310; <h> Flash Configuration
311;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
312;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
313;   <h> Backdoor Comparison Key
314;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
315;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
316;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
317;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
318;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
319;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
320;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
321;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
322BackDoorK0      EQU     0xFF
323BackDoorK1      EQU     0xFF
324BackDoorK2      EQU     0xFF
325BackDoorK3      EQU     0xFF
326BackDoorK4      EQU     0xFF
327BackDoorK5      EQU     0xFF
328BackDoorK6      EQU     0xFF
329BackDoorK7      EQU     0xFF
330;   </h>
331;   <h> Program flash protection bytes (FPROT)
332;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
333;     <i> Each bit protects a 1/32 region of the program flash memory.
334;     <h> FPROT0
335;       <i> Program flash protection bytes
336;       <i> 1/32 - 8/32 region
337;       <o.0>   FPROT0.0
338;       <o.1>   FPROT0.1
339;       <o.2>   FPROT0.2
340;       <o.3>   FPROT0.3
341;       <o.4>   FPROT0.4
342;       <o.5>   FPROT0.5
343;       <o.6>   FPROT0.6
344;       <o.7>   FPROT0.7
345nFPROT0         EQU     0x00
346FPROT0          EQU     nFPROT0:EOR:0xFF
347;     </h>
348;     <h> FPROT1
349;       <i> Program Flash Region Protect Register 1
350;       <i> 9/32 - 16/32 region
351;       <o.0>   FPROT1.0
352;       <o.1>   FPROT1.1
353;       <o.2>   FPROT1.2
354;       <o.3>   FPROT1.3
355;       <o.4>   FPROT1.4
356;       <o.5>   FPROT1.5
357;       <o.6>   FPROT1.6
358;       <o.7>   FPROT1.7
359nFPROT1         EQU     0x00
360FPROT1          EQU     nFPROT1:EOR:0xFF
361;     </h>
362;     <h> FPROT2
363;       <i> Program Flash Region Protect Register 2
364;       <i> 17/32 - 24/32 region
365;       <o.0>   FPROT2.0
366;       <o.1>   FPROT2.1
367;       <o.2>   FPROT2.2
368;       <o.3>   FPROT2.3
369;       <o.4>   FPROT2.4
370;       <o.5>   FPROT2.5
371;       <o.6>   FPROT2.6
372;       <o.7>   FPROT2.7
373nFPROT2         EQU     0x00
374FPROT2          EQU     nFPROT2:EOR:0xFF
375;     </h>
376;     <h> FPROT3
377;       <i> Program Flash Region Protect Register 3
378;       <i> 25/32 - 32/32 region
379;       <o.0>   FPROT3.0
380;       <o.1>   FPROT3.1
381;       <o.2>   FPROT3.2
382;       <o.3>   FPROT3.3
383;       <o.4>   FPROT3.4
384;       <o.5>   FPROT3.5
385;       <o.6>   FPROT3.6
386;       <o.7>   FPROT3.7
387nFPROT3         EQU     0x00
388FPROT3          EQU     nFPROT3:EOR:0xFF
389;     </h>
390;   </h>
391;   <h> Data flash protection byte (FDPROT)
392;     <i> Each bit protects a 1/8 region of the data flash memory.
393;     <i> (Program flash only devices: Reserved)
394;     <o.0>   FDPROT.0
395;     <o.1>   FDPROT.1
396;     <o.2>   FDPROT.2
397;     <o.3>   FDPROT.3
398;     <o.4>   FDPROT.4
399;     <o.5>   FDPROT.5
400;     <o.6>   FDPROT.6
401;     <o.7>   FDPROT.7
402nFDPROT         EQU     0x00
403FDPROT          EQU     nFDPROT:EOR:0xFF
404;   </h>
405;   <h> EEPROM protection byte (FEPROT)
406;     <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
407;     <i> (Program flash only devices: Reserved)
408;     <o.0>   FEPROT.0
409;     <o.1>   FEPROT.1
410;     <o.2>   FEPROT.2
411;     <o.3>   FEPROT.3
412;     <o.4>   FEPROT.4
413;     <o.5>   FEPROT.5
414;     <o.6>   FEPROT.6
415;     <o.7>   FEPROT.7
416nFEPROT         EQU     0x00
417FEPROT          EQU     nFEPROT:EOR:0xFF
418;   </h>
419;   <h> Flash nonvolatile option byte (FOPT)
420;     <i> Allows the user to customize the operation of the MCU at boot time.
421;     <o.0>  LPBOOT
422;       <0=> Low-power boot
423;       <1=> normal boot
424;     <o.1>  EZPORT_DIS
425;       <0=> EzPort operation is enabled
426;       <1=> EzPort operation is disabled
427FOPT            EQU     0xFF
428;   </h>
429;   <h> Flash security byte (FSEC)
430;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
431;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
432;     <o.0..1> SEC
433;       <2=> MCU security status is unsecure
434;       <3=> MCU security status is secure
435;         <i> Flash Security
436;         <i> This bits define the security state of the MCU.
437;     <o.2..3> FSLACC
438;       <2=> Freescale factory access denied
439;       <3=> Freescale factory access granted
440;         <i> Freescale Failure Analysis Access Code
441;         <i> This bits define the security state of the MCU.
442;     <o.4..5> MEEN
443;       <2=> Mass erase is disabled
444;       <3=> Mass erase is enabled
445;         <i> Mass Erase Enable Bits
446;         <i> Enables and disables mass erase capability of the FTFL module
447;     <o.6..7> KEYEN
448;       <2=> Backdoor key access enabled
449;       <3=> Backdoor key access disabled
450;         <i> Backdoor key Security Enable
451;         <i> These bits enable and disable backdoor key access to the FTFL module.
452FSEC            EQU     0xFE
453;   </h>
454; </h>
455                IF      :LNOT::DEF:RAM_TARGET
456                AREA    |.ARM.__at_0x400|, CODE, READONLY
457                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
458                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
459                DCB     FPROT0,     FPROT1,     FPROT2,     FPROT3
460                DCB     FSEC,       FOPT,       FEPROT,     FDPROT
461                ENDIF
462
463                AREA    |.text|, CODE, READONLY
464
465
466; Reset Handler
467
468Reset_Handler   PROC
469                EXPORT  Reset_Handler             [WEAK]
470                IMPORT  SystemInit
471                IMPORT  __main
472                LDR     R0, =SystemInit
473                BLX     R0
474                LDR     R0, =__main
475                BX      R0
476                ENDP
477
478
479; Dummy Exception Handlers (infinite loops which can be modified)
480
481NMI_Handler     PROC
482                EXPORT  NMI_Handler               [WEAK]
483                B       .
484                ENDP
485HardFault_Handler\
486                PROC
487                EXPORT  HardFault_Handler         [WEAK]
488                B       .
489                ENDP
490MemManage_Handler\
491                PROC
492                EXPORT  MemManage_Handler         [WEAK]
493                B       .
494                ENDP
495BusFault_Handler\
496                PROC
497                EXPORT  BusFault_Handler          [WEAK]
498                B       .
499                ENDP
500UsageFault_Handler\
501                PROC
502                EXPORT  UsageFault_Handler        [WEAK]
503                B       .
504                ENDP
505SVC_Handler     PROC
506                EXPORT  SVC_Handler               [WEAK]
507                B       .
508                ENDP
509DebugMon_Handler\
510                PROC
511                EXPORT  DebugMon_Handler          [WEAK]
512                B       .
513                ENDP
514PendSV_Handler  PROC
515                EXPORT  PendSV_Handler            [WEAK]
516                B       .
517                ENDP
518SysTick_Handler PROC
519                EXPORT  SysTick_Handler           [WEAK]
520                B       .
521                ENDP
522
523Default_Handler PROC
524                EXPORT     DMA0_IRQHandler  [WEAK]
525                EXPORT     DMA1_IRQHandler  [WEAK]
526                EXPORT     DMA2_IRQHandler  [WEAK]
527                EXPORT     DMA3_IRQHandler  [WEAK]
528                EXPORT     DMA4_IRQHandler  [WEAK]
529                EXPORT     DMA5_IRQHandler  [WEAK]
530                EXPORT     DMA6_IRQHandler  [WEAK]
531                EXPORT     DMA7_IRQHandler  [WEAK]
532                EXPORT     DMA8_IRQHandler  [WEAK]
533                EXPORT     DMA9_IRQHandler  [WEAK]
534                EXPORT     DMA10_IRQHandler  [WEAK]
535                EXPORT     DMA11_IRQHandler  [WEAK]
536                EXPORT     DMA12_IRQHandler  [WEAK]
537                EXPORT     DMA13_IRQHandler  [WEAK]
538                EXPORT     DMA14_IRQHandler  [WEAK]
539                EXPORT     DMA15_IRQHandler  [WEAK]
540                EXPORT     DMA_Error_IRQHandler   [WEAK]
541                EXPORT     MCM_IRQHandler  [WEAK]
542                EXPORT     FTFE_IRQHandler     [WEAK]
543                EXPORT     Read_Collision_IRQHandler      [WEAK]
544                EXPORT     LVD_LVW_IRQHandler       [WEAK]
545                EXPORT     LLW_IRQHandler       [WEAK]
546                EXPORT     Watchdog_IRQHandler  [WEAK]
547                EXPORT     RNG_IRQHandler  [WEAK]
548                EXPORT     I2C0_IRQHandler  [WEAK]
549                EXPORT     I2C1_IRQHandler  [WEAK]
550                EXPORT     SPI0_IRQHandler  [WEAK]
551                EXPORT     SPI1_IRQHandler  [WEAK]
552                EXPORT     I2S0_Tx_IRQHandler     [WEAK]
553                EXPORT     I2S0_Rx_IRQHandler      [WEAK]
554                EXPORT     UART0_LON_IRQHandler      [WEAK]
555                EXPORT     UART0_RX_TX_IRQHandler      [WEAK]
556                EXPORT     UART0_ERR_IRQHandler      [WEAK]
557                EXPORT     UART1_RX_TX_IRQHandler      [WEAK]
558                EXPORT     UART1_ERR_IRQHandler      [WEAK]
559                EXPORT     UART2_RX_TX_IRQHandler      [WEAK]
560                EXPORT     UART2_ERR_IRQHandler      [WEAK]
561                EXPORT     UART3_RX_TX_IRQHandler      [WEAK]
562                EXPORT     UART3_ERR_IRQHandler      [WEAK]
563                EXPORT     ADC0_IRQHandler  [WEAK]
564                EXPORT     CMP0_IRQHandler  [WEAK]
565                EXPORT     CMP1_IRQHandler  [WEAK]
566                EXPORT     FTM0_IRQHandler      [WEAK]
567                EXPORT     FTM1_IRQHandler      [WEAK]
568                EXPORT     FTM2_IRQHandler      [WEAK]
569                EXPORT     CMT_IRQHandler      [WEAK]
570                EXPORT     RTC_IRQHandler      [WEAK]
571                EXPORT     RTC_Seconds_IRQHandler      [WEAK]
572                EXPORT     PIT0_IRQHandler      [WEAK]
573                EXPORT     PIT1_IRQHandler      [WEAK]
574                EXPORT     PIT2_IRQHandler      [WEAK]
575                EXPORT     PIT3_IRQHandler      [WEAK]
576                EXPORT     PDB0_IRQHandler      [WEAK]
577                EXPORT     USB0_IRQHandler  [WEAK]
578                EXPORT     USBDCD_IRQHandler  [WEAK]
579                EXPORT     Reserved71_IRQHandler      [WEAK]
580                EXPORT     DAC0_IRQHandler     [WEAK]
581                EXPORT     MCG_IRQHandler      [WEAK]
582                EXPORT     LPTimer_IRQHandler    [WEAK]
583                EXPORT     PORTA_IRQHandler      [WEAK]
584                EXPORT     PORTB_IRQHandler      [WEAK]
585                EXPORT     PORTC_IRQHandler      [WEAK]
586                EXPORT     PORTD_IRQHandler      [WEAK]
587                EXPORT     PORTE_IRQHandler      [WEAK]
588                EXPORT     SWI_IRQHandler    [WEAK]
589                EXPORT     SPI2_IRQHandler  [WEAK]
590                EXPORT     UART4_RX_TX_IRQHandler  [WEAK]
591                EXPORT     UART4_ERR_IRQHandler  [WEAK]
592                EXPORT     UART5_RX_TX_IRQHandler  [WEAK]
593                EXPORT     UART5_ERR_IRQHandler  [WEAK]
594                EXPORT     CMP2_IRQHandler  [WEAK]
595                EXPORT     FTM3_IRQHandler  [WEAK]
596                EXPORT     DAC1_IRQHandler      [WEAK]
597                EXPORT     ADC1_IRQHandler      [WEAK]
598                EXPORT     I2C2_IRQHandler      [WEAK]
599                EXPORT     CAN0_ORed_Message_buffer_IRQHandler   [WEAK]
600                EXPORT     CAN0_Bus_Off_IRQHandler      [WEAK]
601                EXPORT     CAN0_Error_IRQHandler      [WEAK]
602                EXPORT     CAN0_Tx_Warning_IRQHandler  [WEAK]
603                EXPORT     CAN0_Rx_Warning_IRQHandler  [WEAK]
604                EXPORT     CAN0_Wake_Up_IRQHandler  [WEAK]
605                EXPORT     SDHC_IRQHandler  [WEAK]
606                EXPORT     ENET_1588_Timer_IRQHandler  [WEAK]
607                EXPORT     ENET_Transmit_IRQHandler  [WEAK]
608                EXPORT     ENET_Receive_IRQHandler  [WEAK]
609                EXPORT     ENET_Error_IRQHandler  [WEAK]
610
611DMA0_IRQHandler  ; DMA Channel 0 Transfer Complete
612DMA1_IRQHandler  ; DMA Channel 1 Transfer Complete
613DMA2_IRQHandler  ; DMA Channel 2 Transfer Complete
614DMA3_IRQHandler  ; DMA Channel 3 Transfer Complete
615DMA4_IRQHandler  ; DMA Channel 4 Transfer Complete
616DMA5_IRQHandler  ; DMA Channel 5 Transfer Complete
617DMA6_IRQHandler  ; DMA Channel 6 Transfer Complete
618DMA7_IRQHandler  ; DMA Channel 7 Transfer Complete
619DMA8_IRQHandler  ; DMA Channel 8 Transfer Complete
620DMA9_IRQHandler  ; DMA Channel 9 Transfer Complete
621DMA10_IRQHandler  ; DMA Channel 10 Transfer Complete
622DMA11_IRQHandler  ; DMA Channel 11 Transfer Complete
623DMA12_IRQHandler  ; DMA Channel 12 Transfer Complete
624DMA13_IRQHandler  ; DMA Channel 13 Transfer Complete
625DMA14_IRQHandler  ; DMA Channel 14 Transfer Complete
626DMA15_IRQHandler  ; DMA Channel 15 Transfer Complete
627DMA_Error_IRQHandler  ; DMA Error Interrupt
628MCM_IRQHandler  ; Normal Interrupt
629FTFE_IRQHandler  ; FTFE Command complete interrupt
630Read_Collision_IRQHandler  ; Read Collision Interrupt
631LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
632LLW_IRQHandler  ; Low Leakage Wakeup
633Watchdog_IRQHandler  ; WDOG Interrupt
634RNG_IRQHandler  ; RNG Interrupt
635I2C0_IRQHandler  ; I2C0 interrupt
636I2C1_IRQHandler  ; I2C1 interrupt
637SPI0_IRQHandler  ; SPI0 Interrupt
638SPI1_IRQHandler  ; SPI1 Interrupt
639I2S0_Tx_IRQHandler  ; I2S0 transmit interrupt
640I2S0_Rx_IRQHandler  ; I2S0 receive interrupt
641UART0_LON_IRQHandler  ; UART0 LON interrupt
642UART0_RX_TX_IRQHandler  ; UART0 Receive/Transmit interrupt
643UART0_ERR_IRQHandler  ; UART0 Error interrupt
644UART1_RX_TX_IRQHandler  ; UART1 Receive/Transmit interrupt
645UART1_ERR_IRQHandler  ; UART1 Error interrupt
646UART2_RX_TX_IRQHandler  ; UART2 Receive/Transmit interrupt
647UART2_ERR_IRQHandler  ; UART2 Error interrupt
648UART3_RX_TX_IRQHandler  ; UART3 Receive/Transmit interrupt
649UART3_ERR_IRQHandler  ; UART3 Error interrupt
650ADC0_IRQHandler  ; ADC0 interrupt
651CMP0_IRQHandler  ; CMP0 interrupt
652CMP1_IRQHandler  ; CMP1 interrupt
653FTM0_IRQHandler  ; FTM0 fault, overflow and channels interrupt
654FTM1_IRQHandler  ; FTM1 fault, overflow and channels interrupt
655FTM2_IRQHandler  ; FTM2 fault, overflow and channels interrupt
656CMT_IRQHandler  ; CMT interrupt
657RTC_IRQHandler  ; RTC interrupt
658RTC_Seconds_IRQHandler  ; RTC seconds interrupt
659PIT0_IRQHandler  ; PIT timer channel 0 interrupt
660PIT1_IRQHandler  ; PIT timer channel 1 interrupt
661PIT2_IRQHandler  ; PIT timer channel 2 interrupt
662PIT3_IRQHandler  ; PIT timer channel 3 interrupt
663PDB0_IRQHandler  ; PDB0 Interrupt
664USB0_IRQHandler  ; USB0 interrupt
665USBDCD_IRQHandler  ; USBDCD Interrupt
666Reserved71_IRQHandler  ; Reserved interrupt 71
667DAC0_IRQHandler  ; DAC0 interrupt
668MCG_IRQHandler  ; MCG Interrupt
669LPTimer_IRQHandler  ; LPTimer interrupt
670PORTA_IRQHandler  ; Port A interrupt
671PORTB_IRQHandler  ; Port B interrupt
672PORTC_IRQHandler  ; Port C interrupt
673PORTD_IRQHandler  ; Port D interrupt
674PORTE_IRQHandler  ; Port E interrupt
675SWI_IRQHandler  ; Software interrupt
676SPI2_IRQHandler  ; SPI2 Interrupt
677UART4_RX_TX_IRQHandler  ; UART4 Receive/Transmit interrupt
678UART4_ERR_IRQHandler  ; UART4 Error interrupt
679UART5_RX_TX_IRQHandler  ; UART5 Receive/Transmit interrupt
680UART5_ERR_IRQHandler  ; UART5 Error interrupt
681CMP2_IRQHandler  ; CMP2 interrupt
682FTM3_IRQHandler  ; FTM3 fault, overflow and channels interrupt
683DAC1_IRQHandler  ; DAC1 interrupt
684ADC1_IRQHandler  ; ADC1 interrupt
685I2C2_IRQHandler  ; I2C2 interrupt
686CAN0_ORed_Message_buffer_IRQHandler  ; CAN0 OR'd message buffers interrupt
687CAN0_Bus_Off_IRQHandler  ; CAN0 bus off interrupt
688CAN0_Error_IRQHandler  ; CAN0 error interrupt
689CAN0_Tx_Warning_IRQHandler  ; CAN0 Tx warning interrupt
690CAN0_Rx_Warning_IRQHandler  ; CAN0 Rx warning interrupt
691CAN0_Wake_Up_IRQHandler  ; CAN0 wake up interrupt
692SDHC_IRQHandler  ; SDHC interrupt
693ENET_1588_Timer_IRQHandler  ; Ethernet MAC IEEE 1588 Timer Interrupt
694ENET_Transmit_IRQHandler  ; Ethernet MAC Transmit Interrupt
695ENET_Receive_IRQHandler  ; Ethernet MAC Receive Interrupt
696ENET_Error_IRQHandler  ; Ethernet MAC Error and miscelaneous Interrupt
697DefaultISR
698
699                B       .
700
701                ENDP
702
703
704                ALIGN
705
706
707; User Initial Stack & Heap
708
709                IF      :DEF:__MICROLIB
710
711                EXPORT  __initial_sp
712                EXPORT  __heap_base
713                EXPORT  __heap_limit
714
715                ELSE
716
717                IMPORT  __use_two_region_memory
718                EXPORT  __user_initial_stackheap
719__user_initial_stackheap
720
721                LDR     R0, =  Heap_Mem
722                LDR     R1, =(Stack_Mem + Stack_Size)
723                LDR     R2, = (Heap_Mem +  Heap_Size)
724                LDR     R3, = Stack_Mem
725                BX      LR
726
727                ALIGN
728
729                ENDIF
730
731
732                END
733