1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2012-02-13 mojingxian first version 9 */ 10 11 #ifndef _BOARD_H_ 12 #define _BOARD_H_ 13 14 #define CLKIN 33333000LL 15 #define SPEED_MULTIPLE 16 16 #define BUS_DIVISOR 4 17 #define CCLKSPEED (CLKIN * SPEED_MULTIPLE) 18 #define SCLKSPEED (CLKIN * BUS_DIVISOR) 19 #define CLOCKS_PER_SECD CCLKSPEED 20 #define SCLOCKS_PER_SEC SCLKSPEED 21 22 //SIC_IMASK寄存器 23 #define PLL_WAKEUP_INT_MASK 0x00000001 24 #define DMA_ERROR_INT_MASK 0x00000002 25 #define PPI_ERROR_INT_MASK 0x00000004 26 #define SPORT0_ERROR_INT_MASK 0x00000008 27 #define SPORT1_ERROR_INT_MASK 0x00000010 28 #define SPI_ERROR_INT_MASK 0x00000020 29 #define UART_ERROR_INT_MASK 0x00000040 30 #define RTC_INT_MASK 0x00000080 31 #define DMA0_PPI_INT_MASK 0x00000100 32 #define DMA1_SPORT0_RX_INT_MASK 0x00000200 33 #define DMA2_SPORT0_TX_INT_MASK 0x00000400 34 #define DMA3_SPORT1_RX_INT_MASK 0x00000800 35 #define DMA4_SPORT1_TX_INT_MASK 0x00001000 36 #define DMA5_SPI_INT_MASK 0x00002000 37 #define DMA6_UART_RX_INT_MASK 0x00004000 38 #define DMA7_UART_TX_INT_MASK 0x00008000 39 #define TIMER0_INT_MASK 0x00010000 40 #define TIMER1_INT_MASK 0x00020000 41 #define TIMER2_INT_MASK 0x00040000 42 #define PF_INTA_MASK 0x00080000 43 #define PF_INTB_MASK 0x00100000 44 #define MEM_DMA_STREAM0_MASK 0x00200000 45 #define MEM_DMA_STREAM1_MASK 0x00400000 46 #define SOFT_WATCHDOG_TMER_MASK 0x00800000 47 48 //SIC_IAR0 49 #define IAR0_PLL_WAKEUP_INT_IVG 0x00 50 #define IAR0_DMA_ERROR_INT_IVG 0x01 51 #define IAR0_PPI_ERROR_INT_IVG 0x02 52 #define IAR0_SPORT0_ERROR_INT_IVG 0x03 53 #define IAR0_SPORT1_ERROR_INT_IVG 0x04 54 #define IAR0_SPI_ERROR_INT_IVG 0x05 55 #define IAR0_UART_ERROR_INT_IVG 0x06 56 #define IAR0_RTC_INT_IVG 0x07 57 58 //SIC_IAR1 59 #define IAR1_DMA0_PPI_INT_IVG 0x00 60 #define IAR1_DMA1_SPORT0RX_IVG 0x01 61 #define IAR1_DMA2_SPORT0TX_IVG 0x02 62 #define IAR1_DMA3_SPORT1RX_IVG 0x03 63 #define IAR1_DMA4_SPORT1TX_IVG 0x04 64 #define IAR1_DMA5_SPI_INT_IVG 0x05 65 #define IAR1_DMA6_UARTRX_IVG 0x06 66 #define IAR1_DMA7_UARTTX_IVG 0x07 67 68 //SIC_IAR2 69 #define IAR2_TIMER0_INT_IVG 0x00 70 #define IAR2_TIMER1_INT_IVG 0x01 71 #define IAR2_TIMER2_INT_IVG 0x02 72 #define IAR2_PF_A_INT_IVG 0x03 73 #define IAR2_PF_B_INT_IVG 0x04 74 #define IAR2_MEM_DMA_STREAM0_INT_IVG 0x05 75 #define IAR2_MEM_DMA_STREAM1_INT_IVG 0x06 76 #define IAR2_SWATCHDOG_TIMER_INT_IVG 0x07 77 78 #ifdef __cplusplus 79 extern "C" { 80 #endif 81 82 void rt_hw_core_timer_init(void); 83 void rt_hw_board_init(void); 84 void rt_hw_isr_install(void); 85 86 #ifdef __cplusplus 87 } 88 #endif 89 90 #endif /* _BSP_H_ */ 91