1 /* Includes ------------------------------------------------------------------*/ 2 #include "air32f10x_cec.h" 3 #include "air32f10x_rcc.h" 4 5 /** @addtogroup STM32F10x_StdPeriph_Driver 6 * @{ 7 */ 8 9 /** @defgroup CEC 10 * @brief CEC driver modules 11 * @{ 12 */ 13 14 /** @defgroup CEC_Private_TypesDefinitions 15 * @{ 16 */ 17 18 /** 19 * @} 20 */ 21 22 23 /** @defgroup CEC_Private_Defines 24 * @{ 25 */ 26 27 /* ------------ CEC registers bit address in the alias region ----------- */ 28 #define CEC_OFFSET (CEC_BASE - PERIPH_BASE) 29 30 /* --- CFGR Register ---*/ 31 32 /* Alias word address of PE bit */ 33 #define CFGR_OFFSET (CEC_OFFSET + 0x00) 34 #define PE_BitNumber 0x00 35 #define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) 36 37 /* Alias word address of IE bit */ 38 #define IE_BitNumber 0x01 39 #define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) 40 41 /* --- CSR Register ---*/ 42 43 /* Alias word address of TSOM bit */ 44 #define CSR_OFFSET (CEC_OFFSET + 0x10) 45 #define TSOM_BitNumber 0x00 46 #define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) 47 48 /* Alias word address of TEOM bit */ 49 #define TEOM_BitNumber 0x01 50 #define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) 51 52 #define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ 53 #define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ 54 55 /** 56 * @} 57 */ 58 59 60 /** @defgroup CEC_Private_Macros 61 * @{ 62 */ 63 64 /** 65 * @} 66 */ 67 68 69 /** @defgroup CEC_Private_Variables 70 * @{ 71 */ 72 73 /** 74 * @} 75 */ 76 77 78 /** @defgroup CEC_Private_FunctionPrototypes 79 * @{ 80 */ 81 82 /** 83 * @} 84 */ 85 86 87 /** @defgroup CEC_Private_Functions 88 * @{ 89 */ 90 91 /** 92 * @brief Deinitializes the CEC peripheral registers to their default reset 93 * values. 94 * @param None 95 * @retval None 96 */ CEC_DeInit(void)97void CEC_DeInit(void) 98 { 99 /* Enable CEC reset state */ 100 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); 101 /* Release CEC from reset state */ 102 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 103 } 104 105 106 /** 107 * @brief Initializes the CEC peripheral according to the specified 108 * parameters in the CEC_InitStruct. 109 * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that 110 * contains the configuration information for the specified 111 * CEC peripheral. 112 * @retval None 113 */ CEC_Init(CEC_InitTypeDef * CEC_InitStruct)114void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) 115 { 116 uint16_t tmpreg = 0; 117 118 /* Check the parameters */ 119 assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 120 assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); 121 122 /*---------------------------- CEC CFGR Configuration -----------------*/ 123 /* Get the CEC CFGR value */ 124 tmpreg = CEC->CFGR; 125 126 /* Clear BTEM and BPEM bits */ 127 tmpreg &= CFGR_CLEAR_Mask; 128 129 /* Configure CEC: Bit Timing Error and Bit Period Error */ 130 tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); 131 132 /* Write to CEC CFGR register*/ 133 CEC->CFGR = tmpreg; 134 135 } 136 137 /** 138 * @brief Enables or disables the specified CEC peripheral. 139 * @param NewState: new state of the CEC peripheral. 140 * This parameter can be: ENABLE or DISABLE. 141 * @retval None 142 */ CEC_Cmd(FunctionalState NewState)143void CEC_Cmd(FunctionalState NewState) 144 { 145 /* Check the parameters */ 146 assert_param(IS_FUNCTIONAL_STATE(NewState)); 147 148 *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; 149 150 if(NewState == DISABLE) 151 { 152 /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ 153 while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) 154 { 155 } 156 } 157 } 158 159 /** 160 * @brief Enables or disables the CEC interrupt. 161 * @param NewState: new state of the CEC interrupt. 162 * This parameter can be: ENABLE or DISABLE. 163 * @retval None 164 */ CEC_ITConfig(FunctionalState NewState)165void CEC_ITConfig(FunctionalState NewState) 166 { 167 /* Check the parameters */ 168 assert_param(IS_FUNCTIONAL_STATE(NewState)); 169 170 *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; 171 } 172 173 /** 174 * @brief Defines the Own Address of the CEC device. 175 * @param CEC_OwnAddress: The CEC own address 176 * @retval None 177 */ CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)178void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) 179 { 180 /* Check the parameters */ 181 assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); 182 183 /* Set the CEC own address */ 184 CEC->OAR = CEC_OwnAddress; 185 } 186 187 /** 188 * @brief Sets the CEC prescaler value. 189 * @param CEC_Prescaler: CEC prescaler new value 190 * @retval None 191 */ CEC_SetPrescaler(uint16_t CEC_Prescaler)192void CEC_SetPrescaler(uint16_t CEC_Prescaler) 193 { 194 /* Check the parameters */ 195 assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); 196 197 /* Set the Prescaler value*/ 198 CEC->PRES = CEC_Prescaler; 199 } 200 201 /** 202 * @brief Transmits single data through the CEC peripheral. 203 * @param Data: the data to transmit. 204 * @retval None 205 */ CEC_SendDataByte(uint8_t Data)206void CEC_SendDataByte(uint8_t Data) 207 { 208 /* Transmit Data */ 209 CEC->TXD = Data ; 210 } 211 212 213 /** 214 * @brief Returns the most recent received data by the CEC peripheral. 215 * @param None 216 * @retval The received data. 217 */ CEC_ReceiveDataByte(void)218uint8_t CEC_ReceiveDataByte(void) 219 { 220 /* Receive Data */ 221 return (uint8_t)(CEC->RXD); 222 } 223 224 /** 225 * @brief Starts a new message. 226 * @param None 227 * @retval None 228 */ CEC_StartOfMessage(void)229void CEC_StartOfMessage(void) 230 { 231 /* Starts of new message */ 232 *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; 233 } 234 235 /** 236 * @brief Transmits message with or without an EOM bit. 237 * @param NewState: new state of the CEC Tx End Of Message. 238 * This parameter can be: ENABLE or DISABLE. 239 * @retval None 240 */ CEC_EndOfMessageCmd(FunctionalState NewState)241void CEC_EndOfMessageCmd(FunctionalState NewState) 242 { 243 /* Check the parameters */ 244 assert_param(IS_FUNCTIONAL_STATE(NewState)); 245 246 /* The data byte will be transmitted with or without an EOM bit*/ 247 *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; 248 } 249 250 /** 251 * @brief Gets the CEC flag status 252 * @param CEC_FLAG: specifies the CEC flag to check. 253 * This parameter can be one of the following values: 254 * @arg CEC_FLAG_BTE: Bit Timing Error 255 * @arg CEC_FLAG_BPE: Bit Period Error 256 * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error 257 * @arg CEC_FLAG_SBE: Start Bit Error 258 * @arg CEC_FLAG_ACKE: Block Acknowledge Error 259 * @arg CEC_FLAG_LINE: Line Error 260 * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error 261 * @arg CEC_FLAG_TEOM: Tx End Of Message 262 * @arg CEC_FLAG_TERR: Tx Error 263 * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished 264 * @arg CEC_FLAG_RSOM: Rx Start Of Message 265 * @arg CEC_FLAG_REOM: Rx End Of Message 266 * @arg CEC_FLAG_RERR: Rx Error 267 * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished 268 * @retval The new state of CEC_FLAG (SET or RESET) 269 */ CEC_GetFlagStatus(uint32_t CEC_FLAG)270FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) 271 { 272 FlagStatus bitstatus = RESET; 273 uint32_t cecreg = 0, cecbase = 0; 274 275 /* Check the parameters */ 276 assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); 277 278 /* Get the CEC peripheral base address */ 279 cecbase = (uint32_t)(CEC_BASE); 280 281 /* Read flag register index */ 282 cecreg = CEC_FLAG >> 28; 283 284 /* Get bit[23:0] of the flag */ 285 CEC_FLAG &= FLAG_Mask; 286 287 if(cecreg != 0) 288 { 289 /* Flag in CEC ESR Register */ 290 CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); 291 292 /* Get the CEC ESR register address */ 293 cecbase += 0xC; 294 } 295 else 296 { 297 /* Get the CEC CSR register address */ 298 cecbase += 0x10; 299 } 300 301 if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) 302 { 303 /* CEC_FLAG is set */ 304 bitstatus = SET; 305 } 306 else 307 { 308 /* CEC_FLAG is reset */ 309 bitstatus = RESET; 310 } 311 312 /* Return the CEC_FLAG status */ 313 return bitstatus; 314 } 315 316 /** 317 * @brief Clears the CEC's pending flags. 318 * @param CEC_FLAG: specifies the flag to clear. 319 * This parameter can be any combination of the following values: 320 * @arg CEC_FLAG_TERR: Tx Error 321 * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished 322 * @arg CEC_FLAG_RSOM: Rx Start Of Message 323 * @arg CEC_FLAG_REOM: Rx End Of Message 324 * @arg CEC_FLAG_RERR: Rx Error 325 * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished 326 * @retval None 327 */ CEC_ClearFlag(uint32_t CEC_FLAG)328void CEC_ClearFlag(uint32_t CEC_FLAG) 329 { 330 uint32_t tmp = 0x0; 331 332 /* Check the parameters */ 333 assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); 334 335 tmp = CEC->CSR & 0x2; 336 337 /* Clear the selected CEC flags */ 338 CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); 339 } 340 341 /** 342 * @brief Checks whether the specified CEC interrupt has occurred or not. 343 * @param CEC_IT: specifies the CEC interrupt source to check. 344 * This parameter can be one of the following values: 345 * @arg CEC_IT_TERR: Tx Error 346 * @arg CEC_IT_TBTF: Tx Block Transfer Finished 347 * @arg CEC_IT_RERR: Rx Error 348 * @arg CEC_IT_RBTF: Rx Block Transfer Finished 349 * @retval The new state of CEC_IT (SET or RESET). 350 */ CEC_GetITStatus(uint8_t CEC_IT)351ITStatus CEC_GetITStatus(uint8_t CEC_IT) 352 { 353 ITStatus bitstatus = RESET; 354 uint32_t enablestatus = 0; 355 356 /* Check the parameters */ 357 assert_param(IS_CEC_GET_IT(CEC_IT)); 358 359 /* Get the CEC IT enable bit status */ 360 enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; 361 362 /* Check the status of the specified CEC interrupt */ 363 if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) 364 { 365 /* CEC_IT is set */ 366 bitstatus = SET; 367 } 368 else 369 { 370 /* CEC_IT is reset */ 371 bitstatus = RESET; 372 } 373 /* Return the CEC_IT status */ 374 return bitstatus; 375 } 376 377 /** 378 * @brief Clears the CEC's interrupt pending bits. 379 * @param CEC_IT: specifies the CEC interrupt pending bit to clear. 380 * This parameter can be any combination of the following values: 381 * @arg CEC_IT_TERR: Tx Error 382 * @arg CEC_IT_TBTF: Tx Block Transfer Finished 383 * @arg CEC_IT_RERR: Rx Error 384 * @arg CEC_IT_RBTF: Rx Block Transfer Finished 385 * @retval None 386 */ CEC_ClearITPendingBit(uint16_t CEC_IT)387void CEC_ClearITPendingBit(uint16_t CEC_IT) 388 { 389 uint32_t tmp = 0x0; 390 391 /* Check the parameters */ 392 assert_param(IS_CEC_GET_IT(CEC_IT)); 393 394 tmp = CEC->CSR & 0x2; 395 396 /* Clear the selected CEC interrupt pending bits */ 397 CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); 398 } 399 400 /** 401 * @} 402 */ 403 404 /** 405 * @} 406 */ 407 408 /** 409 * @} 410 */ 411