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31
32 #ifndef __CCU_H__
33 #define __CCU_H__
34
35 #include <hal_clk.h>
36 #include <limits.h>
37 #include <aw_list.h>
38 #include <hal_log.h>
39 #include <sunxi_hal_common.h>
40 #include <hal_atomic.h>
41
42 struct clk;
43 struct clk_hw;
44 struct clk_core;
45 struct clk_ops;
46
47 #undef BIT
48 #define BIT(x) (1UL << (x))
49
50 #define BITS_PER_LONGS 32
51 #define GENMASK(h, l) \
52 (((~(0)) - ((1) << (l)) + 1) & \
53 (0x00ffffffff >> (BITS_PER_LONGS - 1 - (h))))
54 #define DIV_ROUND_UP_ULL(n, d) (((n) + (d) - 1) / (d))
55 /*
56 * flags used across common struct clk. these flags should only affect the
57 * top-level framework. custom flags for dealing with hardware specifics
58 * belong in struct clk_foo
59 *
60 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
61 */
62 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
63 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
64 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
65 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
66 /* unused */
67 /* unused */
68 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
69 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
70 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
71 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
72 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
73 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
74 /* parents need enable during gate/ungate, set rate and re-parent */
75 #define CLK_OPS_PARENT_ENABLE BIT(12)
76 /* duty cycle call may be forwarded to the parent clock */
77 #define CLK_DUTY_CYCLE_PARENT BIT(13)
78 #define CLK_DONT_HOLD_STATE BIT(14) /* Don't hold state */
79
80 /**
81 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
82 *
83 * @num: Numerator of the duty cycle ratio
84 * @den: Denominator of the duty cycle ratio
85 */
86 struct clk_duty
87 {
88 unsigned int num;
89 unsigned int den;
90 };
91
92
93 struct clk_parent_map
94 {
95 const struct clk_hw *hw;
96 struct clk_core *core;
97 const char *fw_name;
98 const char *name;
99 int index;
100 };
101
102 struct clk_core
103 {
104 const char *name;
105 const struct clk_ops *ops;
106 struct clk_hw *hw;
107 struct clk *clk;
108 struct clk_core *parent;
109 struct clk_parent_map *parents;
110 u8 num_parents;
111 u32 p_rate;
112 unsigned long rate;
113 unsigned long flags;
114 unsigned int enable_count;
115 unsigned long min_rate;
116 unsigned long max_rate;
117 unsigned long accuracy;
118 struct list_head node;
119 };
120
121 struct clk
122 {
123 struct clk_core *core;
124 const char *name;
125 u8 count; //the number that clk_get
126 };
127
128 /**
129 * struct clk_rate_request - Structure encoding the clk constraints that
130 * a clock user might require.
131 *
132 * @rate: Requested clock rate. This field will be adjusted by
133 * clock drivers according to hardware capabilities.
134 * @min_rate: Minimum rate imposed by clk users.
135 * @max_rate: Maximum rate imposed by clk users.
136 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
137 * requested constraints.
138 * @best_parent_hw: The most appropriate parent clock that fulfills the
139 * requested constraints.
140 *
141 */
142 struct clk_rate_request
143 {
144 unsigned long rate;
145 unsigned long min_rate;
146 unsigned long max_rate;
147 unsigned long best_parent_rate;
148 struct clk_hw *best_parent_hw;
149 };
150
151 /**
152 * struct clk_ops - Callback operations for hardware clocks; these are to
153 * be provided by the clock implementation, and will be called by drivers
154 * through the clk_* api.
155 *
156 * @prepare: Prepare the clock for enabling. This must not return until
157 * the clock is fully prepared, and it's safe to call clk_enable.
158 * This callback is intended to allow clock implementations to
159 * do any initialisation that may sleep. Called with
160 * prepare_lock held.
161 *
162 * @unprepare: Release the clock from its prepared state. This will typically
163 * undo any work done in the @prepare callback. Called with
164 * prepare_lock held.
165 *
166 * @is_prepared: Queries the hardware to determine if the clock is prepared.
167 * This function is allowed to sleep. Optional, if this op is not
168 * set then the prepare count will be used.
169 *
170 * @unprepare_unused: Unprepare the clock atomically. Only called from
171 * clk_disable_unused for prepare clocks with special needs.
172 * Called with prepare mutex held. This function may sleep.
173 *
174 * @enable: Enable the clock atomically. This must not return until the
175 * clock is generating a valid clock signal, usable by consumer
176 * devices. Called with enable_lock held. This function must not
177 * sleep.
178 *
179 * @disable: Disable the clock atomically. Called with enable_lock held.
180 * This function must not sleep.
181 *
182 * @is_enabled: Queries the hardware to determine if the clock is enabled.
183 * This function must not sleep. Optional, if this op is not
184 * set then the enable count will be used.
185 *
186 * @disable_unused: Disable the clock atomically. Only called from
187 * clk_disable_unused for gate clocks with special needs.
188 * Called with enable_lock held. This function must not
189 * sleep.
190 *
191 * @save_context: Save the context of the clock in prepration for poweroff.
192 *
193 * @restore_context: Restore the context of the clock after a restoration
194 * of power.
195 *
196 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
197 * parent rate is an input parameter. It is up to the caller to
198 * ensure that the prepare_mutex is held across this call.
199 * Returns the calculated rate. Optional, but recommended - if
200 * this op is not set then clock rate will be initialized to 0.
201 *
202 * @round_rate: Given a target rate as input, returns the closest rate actually
203 * supported by the clock. The parent rate is an input/output
204 * parameter.
205 *
206 * @determine_rate: Given a target rate as input, returns the closest rate
207 * actually supported by the clock, and optionally the parent clock
208 * that should be used to provide the clock rate.
209 *
210 * @set_parent: Change the input source of this clock; for clocks with multiple
211 * possible parents specify a new parent by passing in the index
212 * as a u8 corresponding to the parent in either the .parent_names
213 * or .parents arrays. This function in affect translates an
214 * array index into the value programmed into the hardware.
215 * Returns 0 on success, -EERROR otherwise.
216 *
217 * @get_parent: Queries the hardware to determine the parent of a clock. The
218 * return value is a u8 which specifies the index corresponding to
219 * the parent clock. This index can be applied to either the
220 * .parent_names or .parents arrays. In short, this function
221 * translates the parent value read from hardware into an array
222 * index. Currently only called when the clock is initialized by
223 * __clk_init. This callback is mandatory for clocks with
224 * multiple parents. It is optional (and unnecessary) for clocks
225 * with 0 or 1 parents.
226 *
227 * @set_rate: Change the rate of this clock. The requested rate is specified
228 * by the second argument, which should typically be the return
229 * of .round_rate call. The third argument gives the parent rate
230 * which is likely helpful for most .set_rate implementation.
231 * Returns 0 on success, -EERROR otherwise.
232 *
233 * @set_rate_and_parent: Change the rate and the parent of this clock. The
234 * requested rate is specified by the second argument, which
235 * should typically be the return of .round_rate call. The
236 * third argument gives the parent rate which is likely helpful
237 * for most .set_rate_and_parent implementation. The fourth
238 * argument gives the parent index. This callback is optional (and
239 * unnecessary) for clocks with 0 or 1 parents as well as
240 * for clocks that can tolerate switching the rate and the parent
241 * separately via calls to .set_parent and .set_rate.
242 * Returns 0 on success, -EERROR otherwise.
243 *
244 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
245 * is expressed in ppb (parts per billion). The parent accuracy is
246 * an input parameter.
247 * Returns the calculated accuracy. Optional - if this op is not
248 * set then clock accuracy will be initialized to parent accuracy
249 * or 0 (perfect clock) if clock has no parent.
250 *
251 * @get_phase: Queries the hardware to get the current phase of a clock.
252 * Returned values are 0-359 degrees on success, negative
253 * error codes on failure.
254 *
255 * @set_phase: Shift the phase this clock signal in degrees specified
256 * by the second argument. Valid values for degrees are
257 * 0-359. Return 0 on success, otherwise -EERROR.
258 *
259 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
260 * of a clock. Returned values denominator cannot be 0 and must be
261 * superior or equal to the numerator.
262 *
263 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
264 * the numerator (2nd argurment) and denominator (3rd argument).
265 * Argument must be a valid ratio (denominator > 0
266 * and >= numerator) Return 0 on success, otherwise -EERROR.
267 *
268 * @init: Perform platform-specific initialization magic.
269 * This is not not used by any of the basic clock types.
270 * Please consider other ways of solving initialization problems
271 * before using this callback, as its use is discouraged.
272 *
273 * @debug_init: Set up type-specific debugfs entries for this clock. This
274 * is called once, after the debugfs directory entry for this
275 * clock has been created. The dentry pointer representing that
276 * directory is provided as an argument. Called with
277 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
278 *
279 * @pre_rate_change: Optional callback for a clock to fulfill its rate
280 * change requirements before any rate change has occurred in
281 * its clock tree. Returns 0 on success, -EERROR otherwise.
282 *
283 * @post_rate_change: Optional callback for a clock to clean up any
284 * requirements that were needed while the clock and its tree
285 * was changing states. Returns 0 on success, -EERROR otherwise.
286 *
287 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
288 * implementations to split any work between atomic (enable) and sleepable
289 * (prepare) contexts. If enabling a clock requires code that might sleep,
290 * this must be done in clk_prepare. Clock enable code that will never be
291 * called in a sleepable context may be implemented in clk_enable.
292 *
293 * Typically, drivers will call clk_prepare when a clock may be needed later
294 * (eg. when a device is opened), and clk_enable when the clock is actually
295 * required (eg. from an interrupt). Note that clk_prepare MUST have been
296 * called before clk_enable.
297 */
298 struct clk_ops
299 {
300 int (*prepare)(struct clk_hw *hw);
301 void (*unprepare)(struct clk_hw *hw);
302 int (*is_prepared)(struct clk_hw *hw);
303 void (*unprepare_unused)(struct clk_hw *hw);
304 int (*enable)(struct clk_hw *hw);
305 void (*disable)(struct clk_hw *hw);
306 int (*is_enabled)(struct clk_hw *hw);
307 void (*disable_unused)(struct clk_hw *hw);
308 unsigned long (*recalc_rate)(struct clk_hw *hw,
309 unsigned long parent_rate);
310 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
311 unsigned long *parent_rate);
312 int (*determine_rate)(struct clk_hw *hw,
313 struct clk_rate_request *req);
314 int (*set_parent)(struct clk_hw *hw, u8 index);
315 u8(*get_parent)(struct clk_hw *hw);
316 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
317 unsigned long parent_rate);
318 int (*set_rate_and_parent)(struct clk_hw *hw,
319 unsigned long rate,
320 unsigned long parent_rate, u8 index);
321 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
322 unsigned long parent_accuracy);
323 void (*init)(struct clk_hw *hw);
324 };
325
326 /**
327 * struct clk_init_data - holds init data that's common to all clocks and is
328 * shared between the clock provider and the common clock framework.
329 *
330 * @name: clock name
331 * @ops: operations this clock supports
332 * @parent_names: array of string names for all possible parents
333 * @parent_data: array of parent data for all possible parents (when some
334 * parents are external to the clk controller)
335 * @parent_hws: array of pointers to all possible parents (when all parents
336 * are internal to the clk controller)
337 * @num_parents: number of possible parents
338 * @flags: framework-level hints and quirks
339 */
340 struct clk_init_data
341 {
342 const char *name;
343 const struct clk_ops *ops;
344 /* Only one of the following three should be assigned */
345 const char *const *parent_names;
346 const struct clk_parent_data *parent_data;
347 const struct clk_hw **parent_hws;
348 u8 num_parents;
349 unsigned long flags;
350 };
351
352 /**
353 * struct clk_hw - handle for traversing from a struct clk to its corresponding
354 * hardware-specific structure. struct clk_hw should be declared within struct
355 * clk_foo and then referenced by the struct clk instance that uses struct
356 * clk_foo's clk_ops
357 *
358 * @core: pointer to the struct clk_core instance that points back to this
359 * struct clk_hw instance
360 *
361 * @clk: pointer to the per-user struct clk instance that can be used to call
362 * into the clk API
363 *
364 * @init: pointer to struct clk_init_data that contains the init data shared
365 * with the common clock framework. This pointer will be set to NULL once
366 * a clk_register() variant is called on this clk_hw pointer.
367 */
368 struct clk_hw
369 {
370 struct clk_core *core;
371 hal_clk_id_t id;
372 hal_clk_type_t type;
373 struct clk_init_data *init;
374 };
375
376 /**
377 * struct clk_parent_data - clk parent information
378 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
379 * @fw_name: parent name local to provider registering clk
380 * @name: globally unique parent name (used as a fallback)
381 * @index: parent index local to provider registering clk (if @fw_name absent)
382 */
383 struct clk_parent_data
384 {
385 const struct clk_hw *hw;
386 const char *fw_name;
387 const char *name;
388 int index;
389 };
390
391 /**
392 * struct clk_fixed_rate - fixed-rate clock
393 * @hw: handle between common and hardware-specific interfaces
394 * @fixed_rate: constant frequency of clock
395 */
396 struct clk_fixed_rate
397 {
398 struct clk_hw hw;
399 unsigned long fixed_rate;
400 unsigned long fixed_accuracy;
401 };
402
403 #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
404 /**
405 * struct clk_gate - gating clock
406 *
407 * @hw: handle between common and hardware-specific interfaces
408 * @reg: register controlling gate
409 * @bit_idx: single bit controlling gate
410 * @flags: hardware-specific flags
411 * @lock: register lock
412 *
413 * Clock which can gate its output. Implements .enable & .disable
414 *
415 * Flags:
416 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
417 * enable the clock. Setting this flag does the opposite: setting the bit
418 * disable the clock and clearing it enables the clock
419 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
420 * of this register, and mask of gate bits are in higher 16-bit of this
421 * register. While setting the gate bits, higher 16-bit should also be
422 * updated to indicate changing gate bits.
423 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
424 * the gate register. Setting this flag makes the register accesses big
425 * endian.
426 */
427 struct clk_gate
428 {
429 struct clk_hw hw;
430 u32 reg;
431 u8 bit_idx;
432 u8 flags;
433 };
434
435 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
436
437 struct clk_div_table
438 {
439 unsigned int val;
440 unsigned int div;
441 };
442
443 /**
444 * struct clk_divider - adjustable divider clock
445 *
446 * @hw: handle between common and hardware-specific interfaces
447 * @reg: register containing the divider
448 * @shift: shift to the divider bit field
449 * @width: width of the divider bit field
450 * @table: array of value/divider pairs, last entry should have div = 0
451 * @lock: register lock
452 *
453 * Clock with an adjustable divider affecting its output frequency. Implements
454 * .recalc_rate, .set_rate and .round_rate
455 *
456 * Flags:
457 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
458 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
459 * the raw value read from the register, with the value of zero considered
460 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
461 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
462 * the hardware register
463 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
464 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
465 * Some hardware implementations gracefully handle this case and allow a
466 * zero divisor by not modifying their input clock
467 * (divide by one / bypass).
468 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
469 * of this register, and mask of divider bits are in higher 16-bit of this
470 * register. While setting the divider bits, higher 16-bit should also be
471 * updated to indicate changing divider bits.
472 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
473 * to the closest integer instead of the up one.
474 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
475 * not be changed by the clock framework.
476 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
477 * except when the value read from the register is zero, the divisor is
478 * 2^width of the field.
479 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
480 * for the divider register. Setting this flag makes the register accesses
481 * big endian.
482 */
483 struct clk_divider
484 {
485 struct clk_hw hw;
486 unsigned long reg;
487 u8 shift;
488 u8 width;
489 u8 flags;
490 hal_spinlock_t lock;
491 const struct clk_div_table *table;
492 };
493
494 extern const struct clk_ops clk_divider_ops;
495 extern const struct clk_ops clk_divider_ro_ops;
496
497 #define CLK_DIVIDER_ONE_BASED BIT(0)
498 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
499 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
500 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
501 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
502 #define CLK_DIVIDER_READ_ONLY BIT(5)
503 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
504 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
505
506 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
507 unsigned int val, const struct clk_div_table *table,
508 unsigned long flags, unsigned long width);
509 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
510 unsigned long rate, unsigned long *prate,
511 const struct clk_div_table *table, u8 width,
512 unsigned long flags, unsigned int val);
513 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
514 unsigned long rate, unsigned long *prate,
515 const struct clk_div_table *table,
516 u8 width, unsigned long flags);
517
518 int divider_get_val(unsigned long rate, unsigned long parent_rate,
519 const struct clk_div_table *table, u8 width,
520 unsigned long flags);
521
522 #define clk_div_mask(width) ((1 << (width)) - 1)
523 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
524
525 struct clk_hw *clk_hw_register_divider(const char *name,
526 const char *parent_name, unsigned long flags,
527 u32 reg, u8 shift, u8 width,
528 u8 clk_divider_flags, hal_spinlock_t lock);
529 struct clk_hw *clk_hw_register_divider_table(const char *name,
530 const char *parent_name, unsigned long flags,
531 u32 reg, u8 shift, u8 width,
532 u8 clk_divider_flags, const struct clk_div_table *table,
533 hal_spinlock_t lock);
534 void clk_unregister_divider(struct clk *clk);
535 void clk_hw_unregister_divider(struct clk_hw *hw);
536
537 /**
538 * struct clk_mux - multiplexer clock
539 *
540 * @hw: handle between common and hardware-specific interfaces
541 * @reg: register controlling multiplexer
542 * @table: array of register values corresponding to the parent index
543 * @shift: shift to multiplexer bit field
544 * @mask: mask of mutliplexer bit field
545 * @flags: hardware-specific flags
546 * @lock: register lock
547 *
548 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
549 * and .recalc_rate
550 *
551 * Flags:
552 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
553 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
554 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
555 * register, and mask of mux bits are in higher 16-bit of this register.
556 * While setting the mux bits, higher 16-bit should also be updated to
557 * indicate changing mux bits.
558 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
559 * .get_parent clk_op.
560 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
561 * frequency.
562 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
563 * the mux register. Setting this flag makes the register accesses big
564 * endian.
565 */
566 struct clk_mux
567 {
568 struct clk_hw hw;
569 u32 reg;
570 u32 *table;
571 u32 mask;
572 u8 shift;
573 u8 flags;
574 };
575
576 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
577
578 #define CLK_MUX_INDEX_ONE BIT(0)
579 #define CLK_MUX_INDEX_BIT BIT(1)
580 #define CLK_MUX_HIWORD_MASK BIT(2)
581 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
582 #define CLK_MUX_ROUND_CLOSEST BIT(4)
583 #define CLK_MUX_BIG_ENDIAN BIT(5)
584
585 extern const struct clk_ops clk_mux_ops;
586 extern const struct clk_ops clk_mux_ro_ops;
587
588 /**
589 * struct clk_fixed_factor - fixed multiplier and divider clock
590 *
591 * @hw: handle between common and hardware-specific interfaces
592 * @mult: multiplier
593 * @div: divider
594 *
595 * Clock with a fixed multiplier and divider. The output frequency is the
596 * parent clock rate divided by div and multiplied by mult.
597 * Implements .recalc_rate, .set_rate and .round_rate
598 */
599
600 struct clk_fixed_factor
601 {
602 struct clk_hw hw;
603 unsigned int mult;
604 unsigned int div;
605 };
606
607 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
608
609 extern const struct clk_ops clk_fixed_factor_ops;
610
611 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
612
613 /*
614 * Use this macro when you have a driver that requires two initialization
615 * routines, one at of_clk_init(), and one at platform device probe
616 */
617 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
618 static void __init name##_of_clk_init_driver(struct device_node *np) \
619 { \
620 of_node_clear_flag(np, OF_POPULATED); \
621 fn(np); \
622 } \
623 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
624
625 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
626 (&(struct clk_init_data) { \
627 .flags = _flags, \
628 .name = _name, \
629 .parent_names = (const char *[]) { _parent }, \
630 .num_parents = 1, \
631 .ops = _ops, \
632 })
633
634 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
635 (&(struct clk_init_data) { \
636 .flags = _flags, \
637 .name = _name, \
638 .parent_hws = (const struct clk_hw*[]) { _parent }, \
639 .num_parents = 1, \
640 .ops = _ops, \
641 })
642
643 /*
644 * This macro is intended for drivers to be able to share the otherwise
645 * individual struct clk_hw[] compound literals created by the compiler
646 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
647 */
648 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
649 (&(struct clk_init_data) { \
650 .flags = _flags, \
651 .name = _name, \
652 .parent_hws = _parent, \
653 .num_parents = 1, \
654 .ops = _ops, \
655 })
656
657 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
658 (&(struct clk_init_data) { \
659 .flags = _flags, \
660 .name = _name, \
661 .parent_data = (const struct clk_parent_data[]) { \
662 { .fw_name = _parent }, \
663 }, \
664 .num_parents = 1, \
665 .ops = _ops, \
666 })
667
668 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
669 (&(struct clk_init_data) { \
670 .flags = _flags, \
671 .name = _name, \
672 .parent_names = _parents, \
673 .num_parents = ARRAY_SIZE(_parents), \
674 .ops = _ops, \
675 })
676
677 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
678 (&(struct clk_init_data) { \
679 .flags = _flags, \
680 .name = _name, \
681 .parent_hws = _parents, \
682 .num_parents = ARRAY_SIZE(_parents), \
683 .ops = _ops, \
684 })
685
686 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
687 (&(struct clk_init_data) { \
688 .flags = _flags, \
689 .name = _name, \
690 .parent_data = _parents, \
691 .num_parents = ARRAY_SIZE(_parents), \
692 .ops = _ops, \
693 })
694
695 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
696 (&(struct clk_init_data) { \
697 .flags = _flags, \
698 .name = _name, \
699 .parent_names = NULL, \
700 .num_parents = 0, \
701 .ops = _ops, \
702 })
703
704 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
705 _div, _mult, _flags) \
706 struct clk_fixed_factor _struct = { \
707 .div = _div, \
708 .mult = _mult, \
709 .hw.init = CLK_HW_INIT(_name, \
710 _parent, \
711 &clk_fixed_factor_ops, \
712 _flags), \
713 }
714
715 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
716 _div, _mult, _flags) \
717 struct clk_fixed_factor _struct = { \
718 .div = _div, \
719 .mult = _mult, \
720 .hw.init = CLK_HW_INIT_HW(_name, \
721 _parent, \
722 &clk_fixed_factor_ops, \
723 _flags), \
724 }
725
726 /*
727 * This macro allows the driver to reuse the _parent array for multiple
728 * fixed factor clk declarations.
729 */
730 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
731 _div, _mult, _flags) \
732 struct clk_fixed_factor _struct = { \
733 .div = _div, \
734 .mult = _mult, \
735 .hw.init = CLK_HW_INIT_HWS(_name, \
736 _parent, \
737 &clk_fixed_factor_ops, \
738 _flags), \
739 }
740
741 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
742 _div, _mult, _flags) \
743 struct clk_fixed_factor _struct = { \
744 .div = _div, \
745 .mult = _mult, \
746 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
747 _parent, \
748 &clk_fixed_factor_ops, \
749 _flags), \
750 }
751
752 const char *clk_hw_get_name(const struct clk_hw *hw);
753 u32 clk_hw_get_rate(const struct clk_hw *hw);
754 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
755 struct clk_core *clk_hw_get_core(const struct clk_hw *hw);
756 #define clk_hw_can_set_rate_parent(hw) \
757 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
758
759 /*
760 * FIXME clock api without lock protection
761 */
762 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
763
764 struct clk_hw_onecell_data
765 {
766 unsigned int num;
767 struct clk_hw *hws[];
768 };
769
770 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
771
772 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
773 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
774 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
775 unsigned int index);
776
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)777 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
778 unsigned long *prate,
779 const struct clk_div_table *table,
780 u8 width, unsigned long flags)
781 {
782 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
783 rate, prate, table, width, flags);
784 }
785
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)786 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
787 unsigned long *prate,
788 const struct clk_div_table *table,
789 u8 width, unsigned long flags,
790 unsigned int val)
791 {
792 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
793 rate, prate, table, width, flags,
794 val);
795 }
796
797 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
798 int __clk_mux_determine_rate(struct clk_hw *hw,
799 struct clk_rate_request *req);
800
801 int hw_clks_register(struct clk_hw_onecell_data *hw_clock_clks);
802
803 int hw_clks_init(struct clk_hw *hw);
804
805 int clk_hw_register(struct clk_hw *hw);
806
807 int clk_hw_unregister(struct clk_hw *hw);
808
809 hal_clk_status_t clk_hw_set_rate(struct clk_hw *hw, unsigned long rate);
810
811 struct clk_core *clk_core_get(hal_clk_type_t type, hal_clk_id_t id);
812
813 hal_clk_status_t clk_core_is_enabled(struct clk_core *core);
814
815 hal_clk_status_t clk_core_enable(struct clk_core *core);
816
817 hal_clk_status_t clk_core_disable(struct clk_core *core);
818
819 struct clk_core *clk_core_get_parent(struct clk_core *core);
820
821 hal_clk_status_t clk_core_set_parent(struct clk_core *core, struct clk_core *parent);
822
823 u32 clk_core_get_rate(struct clk_core *core);
824
825 hal_clk_status_t clk_core_set_rate(struct clk_core *core, struct clk_core *p_core, unsigned long rate);
826
827 u32 clk_core_recalc_rate(struct clk_core *core, struct clk_core *p_core);
828
829 u32 clk_core_round_rate(struct clk_core *core, u32 rate);
830
831 #endif /* __HAL_CLOCK_H__ */
832
833