1 /*
2 *******************************************************************************
3 * Copyright(C) NEC Electronics Corporation 2010
4 * All rights reserved by NEC Electronics Corporation.
5 * This program should be used on your own responsibility.
6 * NEC Electronics Corporation assumes no responsibility for any losses
7 * incurred by customers or third parties arising from the use of this file.
8 *
9 * This device driver was created by Applilet3 for V850ES/Jx3
10 * 32-Bit Single-Chip Microcontrollers
11 * Filename: CG_system.c
12 * Abstract: This file implements device driver for System module.
13 * APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
14 * Device: uPD70F3746
15 * Compiler: IAR Systems ICCV850
16 * Creation date: 6/26/2010
17 *******************************************************************************
18 */
19
20 /*
21 *******************************************************************************
22 ** Include files
23 *******************************************************************************
24 */
25 #include "CG_macrodriver.h"
26 #include "CG_system.h"
27 /* Start user code for include. Do not edit comment generated here */
28 /* End user code. Do not edit comment generated here */
29 #include "CG_userdefine.h"
30
31 /*
32 *******************************************************************************
33 ** Global define
34 *******************************************************************************
35 */
36 /* Start user code for global. Do not edit comment generated here */
37 /* End user code. Do not edit comment generated here */
38
clock_pll_mode(void)39 void clock_pll_mode(void)
40 {
41 /* CPU operation clock selection */
42 /* Set PLL mode. */
43 PLLCTL = 0x03; /* bit 1: CPU clock selection (PLL mode/clock-through mode selection) */
44 /* 1: PLL mode, 0: Clock-through mode */
45
46 __asm("_loop: set1 1,0xF82C[r0]"); //__IO_REG8_BIT( PLLCTL, 0xFFFFF82C, __READ_WRITE )
47 __asm(" tst1 1,0xF82C[r0]"); //__IO_REG8_BIT( PLLCTL, 0xFFFFF82C, __READ_WRITE )
48 __asm(" bz _loop");
49
50 return;
51 }
52
clock_pcc_mode(void)53 void clock_pcc_mode(void)
54 {
55 /* DMA is forcibly terminated in this sample since DMA transfer must be terminated
56 before data is set to a special register. */
57
58 if(TC0 == 0 && E00 == 1){ /* DMA0 transfer judgment */
59 INIT0 = 1; /* DMA0 forcible termination */
60 }
61 if(TC1 == 0 && E11 == 1){ /* DMA1 transfer judgment */
62 INIT1 = 1; /* DMA1 forcible termination */
63 }
64 if(TC2 == 0 && E22 == 1){ /* DMA2 transfer judgment */
65 INIT2 = 1; /* DMA2 forcible termination */
66 }
67 if(TC3 == 0 && E33 == 1){ /* DMA3 transfer judgment */
68 INIT3 = 1; /* DMA3 forcible termination */
69 }
70
71 /* The PCC register is a special register. Data can be written to this register only in a combination of specific sequences. */
72 /* bit 1, bit 0: Clock selection, 11: fxx/8, 10: fxx/4, 01: fxx/2, 00: fxx */
73 /* Clock selection: fxx */
74 __asm("mov 0x00, r10"); /* Set general-purpose register data to be set to special register. */
75 __asm("st.b r10, 0xF1FC[r0]"); /* Write to PRCMD register. */ //__IO_REG8(PRCMD, 0xFFFFF1FC, __WRITE)
76 __asm("st.b r10, 0xF828[r0]"); /* Set PCC register. */ //__IO_REG8_BIT(PCC, 0xFFFFF828, __READ_WRITE)
77 __asm("nop"); /* Insert five or more NOP instructions. */
78 __asm("nop");
79 __asm("nop");
80 __asm("nop");
81 __asm("nop");
82
83 return;
84 }
85
86 /*
87 **-----------------------------------------------------------------------------
88 **
89 ** Abstract:
90 ** This function initializes the clock generator module.
91 **
92 ** Parameters:
93 ** None
94 **
95 ** Returns:
96 ** None
97 **
98 **-----------------------------------------------------------------------------
99 */
CLOCK_Init(void)100 void CLOCK_Init(void)
101 {
102 DI(); /* Maskable interrupt disabled */
103
104 do{
105 clock_pll_mode(); /* PLL mode setting function */
106
107 clock_pcc_mode(); /* PCC register setting function */
108
109 }while(PRERR); /* Written in correct sequence? */
110 }
111
112 /* Start user code for adding. Do not edit comment generated here */
113 /* End user code. Do not edit comment generated here */
114