1 /********************************** (C) COPYRIGHT *******************************
2 * File Name : core_riscv.h
3 * Author : WCH
4 * Version : V1.0.0
5 * Date : 2020/04/30
6 * Description : RISC-V Core Peripheral Access Layer Header File
7 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
8 * SPDX-License-Identifier: Apache-2.0
9 *******************************************************************************/
10 #ifndef __CORE_RISCV_H__
11 #define __CORE_RISCV_H__
12
13 /* IO definitions */
14 #ifdef __cplusplus
15 #define __I volatile /*!< defines 'read only' permissions */
16 #else
17 #define __I volatile const /*!< defines 'read only' permissions */
18 #endif
19 #define __O volatile /*!< defines 'write only' permissions */
20 #define __IO volatile /*!< defines 'read / write' permissions */
21
22 /* Standard Peripheral Library old types (maintained for legacy purpose) */
23 typedef __I uint32_t vuc32; /* Read Only */
24 typedef __I uint16_t vuc16; /* Read Only */
25 typedef __I uint8_t vuc8; /* Read Only */
26
27 typedef const uint32_t uc32; /* Read Only */
28 typedef const uint16_t uc16; /* Read Only */
29 typedef const uint8_t uc8; /* Read Only */
30
31 typedef __I int32_t vsc32; /* Read Only */
32 typedef __I int16_t vsc16; /* Read Only */
33 typedef __I int8_t vsc8; /* Read Only */
34
35 typedef const int32_t sc32; /* Read Only */
36 typedef const int16_t sc16; /* Read Only */
37 typedef const int8_t sc8; /* Read Only */
38
39 typedef __IO uint32_t vu32;
40 typedef __IO uint16_t vu16;
41 typedef __IO uint8_t vu8;
42
43 typedef uint32_t u32;
44 typedef uint16_t u16;
45 typedef uint8_t u8;
46
47 typedef __IO int32_t vs32;
48 typedef __IO int16_t vs16;
49 typedef __IO int8_t vs8;
50
51 typedef int32_t s32;
52 typedef int16_t s16;
53 typedef int8_t s8;
54
55 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
56
57 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
58
59 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
60
61 #define RV_STATIC_INLINE static inline
62
63 /* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
64 typedef struct{
65 __I uint32_t ISR[8];
66 __I uint32_t IPR[8];
67 __IO uint32_t ITHRESDR;
68 __IO uint32_t FIBADDRR;
69 __IO uint32_t CFGR;
70 __I uint32_t GISR;
71 uint8_t RESERVED0[0x10];
72 __IO uint32_t FIOFADDRR[4];
73 uint8_t RESERVED1[0x90];
74 __O uint32_t IENR[8];
75 uint8_t RESERVED2[0x60];
76 __O uint32_t IRER[8];
77 uint8_t RESERVED3[0x60];
78 __O uint32_t IPSR[8];
79 uint8_t RESERVED4[0x60];
80 __O uint32_t IPRR[8];
81 uint8_t RESERVED5[0x60];
82 __IO uint32_t IACTR[8];
83 uint8_t RESERVED6[0xE0];
84 __IO uint8_t IPRIOR[256];
85 uint8_t RESERVED7[0x810];
86 __IO uint32_t SCTLR;
87 }PFIC_Type;
88
89 /* memory mapped structure for SysTick */
90 typedef struct
91 {
92 __IO uint32_t CTLR;
93 __IO uint8_t CNTL0;
94 __IO uint8_t CNTL1;
95 __IO uint8_t CNTL2;
96 __IO uint8_t CNTL3;
97 __IO uint8_t CNTH0;
98 __IO uint8_t CNTH1;
99 __IO uint8_t CNTH2;
100 __IO uint8_t CNTH3;
101 __IO uint8_t CMPLR0;
102 __IO uint8_t CMPLR1;
103 __IO uint8_t CMPLR2;
104 __IO uint8_t CMPLR3;
105 __IO uint8_t CMPHR0;
106 __IO uint8_t CMPHR1;
107 __IO uint8_t CMPHR2;
108 __IO uint8_t CMPHR3;
109 }SysTick_Type;
110
111
112 #define PFIC ((PFIC_Type *) 0xE000E000 )
113 #define NVIC PFIC
114 #define NVIC_KEY1 ((uint32_t)0xFA050000)
115 #define NVIC_KEY2 ((uint32_t)0xBCAF0000)
116 #define NVIC_KEY3 ((uint32_t)0xBEEF0000)
117
118 #define SysTick ((SysTick_Type *) 0xE000F000)
119
120
121 /*********************************************************************
122 * @fn __NOP
123 *
124 * @brief nop
125 *
126 * @return none
127 */
__NOP()128 RV_STATIC_INLINE void __NOP()
129 {
130 __asm volatile ("nop");
131 }
132
133 /*********************************************************************
134 * @fn NVIC_EnableIRQ
135 *
136 * @brief Enable Interrupt
137 *
138 * @param IRQn: Interrupt Numbers
139 *
140 * @return none
141 */
NVIC_EnableIRQ(IRQn_Type IRQn)142 RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn){
143 NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
144 }
145
146 /*********************************************************************
147 * @fn NVIC_DisableIRQ
148 *
149 * @brief Disable Interrupt
150 *
151 * @param IRQn: Interrupt Numbers
152 *
153 * @return none
154 */
NVIC_DisableIRQ(IRQn_Type IRQn)155 RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
156 {
157 uint32_t t;
158
159 t = NVIC->ITHRESDR;
160 NVIC->ITHRESDR = 0x10;
161 NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
162 NVIC->ITHRESDR = t;
163 }
164
165 /*********************************************************************
166 * @fn NVIC_GetStatusIRQ
167 *
168 * @brief Get Interrupt Enable State
169 *
170 * @param IRQn: Interrupt Numbers
171 *
172 * @return 1 - Interrupt Enable
173 * 0 - Interrupt Disable
174 */
NVIC_GetStatusIRQ(IRQn_Type IRQn)175 RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
176 {
177 return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
178 }
179
180 /*********************************************************************
181 * @fn NVIC_GetPendingIRQ
182 *
183 * @brief Get Interrupt Pending State
184 *
185 * @param IRQn: Interrupt Numbers
186 *
187 * @return 1 - Interrupt Pending Enable
188 * 0 - Interrupt Pending Disable
189 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)190 RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
191 {
192 return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
193 }
194
195 /*********************************************************************
196 * @fn NVIC_SetPendingIRQ
197 *
198 * @brief Set Interrupt Pending
199 *
200 * @param IRQn: Interrupt Numbers
201 *
202 * @return None
203 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)204 RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
205 {
206 NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
207 }
208
209 /*********************************************************************
210 * @fn NVIC_ClearPendingIRQ
211 *
212 * @brief Clear Interrupt Pending
213 *
214 * @param IRQn: Interrupt Numbers
215 *
216 * @return None
217 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)218 RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
219 {
220 NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
221 }
222
223 /*********************************************************************
224 * @fn NVIC_GetActive
225 *
226 * @brief Get Interrupt Active State
227 *
228 * @param IRQn: Interrupt Numbers
229 *
230 * @return 1 - Interrupt Active
231 * 0 - Interrupt No Active
232 */
NVIC_GetActive(IRQn_Type IRQn)233 RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
234 {
235 return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
236 }
237
238 /*********************************************************************
239 * @fn NVIC_SetPriority
240 *
241 * @brief Set Interrupt Priority
242 *
243 * @param IRQn - Interrupt Numbers
244 * priority -
245 * bit7 - pre-emption priority
246 * bit6~bit4 - subpriority
247 * @return None
248 */
NVIC_SetPriority(IRQn_Type IRQn,uint8_t priority)249 RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
250 {
251 NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
252 }
253
254 /*********************************************************************
255 * @fn __WFI
256 *
257 * @brief Wait for Interrupt
258 *
259 * @return None
260 */
__WFI(void)261 __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
262 {
263 NVIC->SCTLR &= ~(1<<3); // wfi
264 asm volatile ("wfi");
265 }
266
267 /*********************************************************************
268 * @fn __WFE
269 *
270 * @brief Wait for Events
271 *
272 * @return None
273 */
__WFE(void)274 __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
275 {
276 NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev)
277 asm volatile ("wfi");
278 NVIC->SCTLR |= (1<<3);
279 asm volatile ("wfi");
280 }
281
282 /*********************************************************************
283 * @fn NVIC_SetFastIRQ
284 *
285 * @brief Set VTF Interrupt
286 *
287 * @param add - VTF interrupt service function base address.
288 * IRQn -Interrupt Numbers
289 * num - VTF Interrupt Numbers
290 * @return None
291 */
NVIC_SetFastIRQ(uint32_t addr,IRQn_Type IRQn,uint8_t num)292 RV_STATIC_INLINE void NVIC_SetFastIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num)
293 {
294 if(num > 3) return ;
295 NVIC->FIBADDRR = addr;
296 NVIC->FIOFADDRR[num] = ((uint32_t)IRQn<<24)|(addr&0xfffff);
297 }
298
299 /*********************************************************************
300 * @fn NVIC_SystemReset
301 *
302 * @brief Initiate a system reset request
303 *
304 * @return None
305 */
NVIC_SystemReset(void)306 RV_STATIC_INLINE void NVIC_SystemReset(void)
307 {
308 NVIC->CFGR = NVIC_KEY3|(1<<7);
309 }
310
311 /*********************************************************************
312 * @fn NVIC_HaltPushCfg
313 *
314 * @brief Enable Hardware Stack
315 *
316 * @param NewState - DISABLE or ENABLE
317
318 * @return None
319 */
NVIC_HaltPushCfg(FunctionalState NewState)320 RV_STATIC_INLINE void NVIC_HaltPushCfg(FunctionalState NewState)
321 {
322 if (NewState != DISABLE)
323 {
324 NVIC->CFGR = NVIC_KEY1;
325 }
326 else{
327 NVIC->CFGR = NVIC_KEY1|(1<<0);
328 }
329 }
330
331 /*********************************************************************
332 * @fn NVIC_INTNestCfg
333 *
334 * @brief Enable Interrupt Nesting
335 *
336 * @param NewState - DISABLE or ENABLE
337
338 * @return None
339 */
NVIC_INTNestCfg(FunctionalState NewState)340 RV_STATIC_INLINE void NVIC_INTNestCfg(FunctionalState NewState)
341 {
342 if (NewState != DISABLE)
343 {
344 NVIC->CFGR = NVIC_KEY1;
345 }
346 else
347 {
348 NVIC->CFGR = NVIC_KEY1|(1<<1);
349 }
350 }
351
352 /* Core_Exported_Functions */
353 extern uint32_t __get_FFLAGS(void);
354 extern void __set_FFLAGS(uint32_t value);
355 extern uint32_t __get_FRM(void);
356 extern void __set_FRM(uint32_t value);
357 extern uint32_t __get_FCSR(void);
358 extern void __set_FCSR(uint32_t value);
359 extern uint32_t __get_MSTATUS(void);
360 extern void __set_MSTATUS(uint32_t value);
361 extern uint32_t __get_MISA(void);
362 extern void __set_MISA(uint32_t value);
363 extern uint32_t __get_MIE(void);
364 extern void __set_MIE(uint32_t value);
365 extern uint32_t __get_MTVEC(void);
366 extern void __set_MTVEC(uint32_t value);
367 extern uint32_t __get_MSCRATCH(void);
368 extern void __set_MSCRATCH(uint32_t value);
369 extern uint32_t __get_MEPC(void);
370 extern void __set_MEPC(uint32_t value);
371 extern uint32_t __get_MCAUSE(void);
372 extern void __set_MCAUSE(uint32_t value);
373 extern uint32_t __get_MTVAL(void);
374 extern void __set_MTVAL(uint32_t value);
375 extern uint32_t __get_MIP(void);
376 extern void __set_MIP(uint32_t value);
377 extern uint32_t __get_MCYCLE(void);
378 extern void __set_MCYCLE(uint32_t value);
379 extern uint32_t __get_MCYCLEH(void);
380 extern void __set_MCYCLEH(uint32_t value);
381 extern uint32_t __get_MINSTRET(void);
382 extern void __set_MINSTRET(uint32_t value);
383 extern uint32_t __get_MINSTRETH(void);
384 extern void __set_MINSTRETH(uint32_t value);
385 extern uint32_t __get_MVENDORID(void);
386 extern uint32_t __get_MARCHID(void);
387 extern uint32_t __get_MIMPID(void);
388 extern uint32_t __get_MHARTID(void);
389 extern uint32_t __get_SP(void);
390
391
392 #endif/* __CORE_RISCV_H__ */
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