1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_comp.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_COMP_H 22 #define __REG_COMP_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 //////////////////////////////////////////////////////////////////////////////// 44 /// @brief COMP Base Address Definition 45 //////////////////////////////////////////////////////////////////////////////// 46 #define COMP_BASE (APB2PERIPH_BASE + 0x4000) ///< Base Address: 0x40014000 47 48 //////////////////////////////////////////////////////////////////////////////// 49 /// @brief Comparators Register Structure Definition 50 //////////////////////////////////////////////////////////////////////////////// 51 typedef struct { 52 53 54 55 __IO u32 RESERVED1; ///< offset: 0x00 56 __IO u32 RESERVED2; ///< offset: 0x04 57 __IO u32 RESERVED3; ///< offset: 0x08 58 union { 59 __IO u32 CSR1; ///< COMP1 Control Status Register offset: 0x0C 60 __IO u32 COMP1_CSR; 61 }; 62 union { 63 __IO u32 CSR2; ///< COMP2 Control Status Register offset: 0x10 64 __IO u32 COMP2_CSR; 65 }; 66 __IO u32 RESERVED4; ///< offset: 0x14 67 union { 68 __IO u32 CRV; ///< COMP external reference voltage register offset: 0x18 69 __IO u32 COMP_CRV; 70 }; 71 union { 72 __IO u32 POLL1; ///< COMP1 polling register offset: 0x1C 73 __IO u32 COMP1_POLL; 74 }; 75 union { 76 __IO u32 POLL2; ///< COMP2 polling register offset: 0x20 77 __IO u32 COMP2_POLL; 78 }; 79 } COMP_TypeDef; 80 81 82 //////////////////////////////////////////////////////////////////////////////// 83 /// @brief COMP type pointer Definition 84 //////////////////////////////////////////////////////////////////////////////// 85 #define COMP ((COMP_TypeDef*) COMP_BASE) 86 87 88 89 90 91 //////////////////////////////////////////////////////////////////////////////// 92 /// @brief COMP_CSR Register Bit Definition 93 //////////////////////////////////////////////////////////////////////////////// 94 #define COMP_CSR_EN_Pos (0) 95 #define COMP_CSR_EN (0x01U << COMP_CSR_EN_Pos) ///< Comparator enable 96 #define COMP_CSR_MODE_Pos (2) 97 #define COMP_CSR_MODE (0x03U << COMP_CSR_MODE_Pos) ///< Comparator mode 98 #define COMP_CSR_MODE_LOWESTPOWER (0x00U << COMP_CSR_MODE_Pos) ///< Comparator lowest power mode 99 #define COMP_CSR_MODE_LOWPOWER (0x01U << COMP_CSR_MODE_Pos) ///< Comparator low power mode 100 #define COMP_CSR_MODE_MEDIUMRATE (0x02U << COMP_CSR_MODE_Pos) ///< Comparator medium rate mode 101 #define COMP_CSR_MODE_HIGHRATE (0x03U << COMP_CSR_MODE_Pos) ///< Comparator high rate mode 102 103 #define COMP_CSR_INM_Pos (4) 104 #define COMP_CSR_INM (0x03U << COMP_CSR_INM_Pos) ///< Comparator inverting input selection 105 #define COMP_CSR_INM_0 (0x00U << COMP_CSR_INM_Pos) ///< INM0 as COMP inverting input 106 #define COMP_CSR_INM_1 (0x01U << COMP_CSR_INM_Pos) ///< INM1 as COMP inverting input 107 #define COMP_CSR_INM_2 (0x02U << COMP_CSR_INM_Pos) ///< INM2 as COMP inverting input 108 #define COMP_CSR_INM_3 (0x03U << COMP_CSR_INM_Pos) ///< INM3 as COMP inverting input 109 110 #define COMP_CSR_INP_Pos (7) 111 #define COMP_CSR_INP (0x03U << COMP_CSR_INP_Pos) ///< Comparator non-inverting input selection 112 #define COMP_CSR_INP_INP0 (0x00U << COMP_CSR_INP_Pos) ///< INP0 as COMP non-inverting input 113 #define COMP_CSR_INP_INP1 (0x01U << COMP_CSR_INP_Pos) ///< INP1 as COMP non-inverting input 114 #define COMP_CSR_INP_INP2 (0x02U << COMP_CSR_INP_Pos) ///< INP2 as COMP non-inverting input 115 #define COMP_CSR_INP_INP3 (0x03U << COMP_CSR_INP_Pos) ///< INP3 as COMP non-inverting input 116 117 #define COMP_CSR_OUT_Pos (10) 118 #define COMP_CSR_OUT (0x0FU << COMP_CSR_OUT_Pos) ///< Comparator output selection 119 #define COMP_CSR_OUT_TIM1_BRAKE (0x02U << COMP_CSR_OUT_Pos) ///< Timer1 brake input 120 #define COMP_CSR_OUT_TIM8_BRAKE (0x03U << COMP_CSR_OUT_Pos) ///< Timer8 brake input 121 #define COMP_CSR_OUT_TIM1_OCREFCLR (0x06U << COMP_CSR_OUT_Pos) ///< Timer1 ocrefclear input 122 #define COMP_CSR_OUT_TIM1_CAPTURE1 (0x07U << COMP_CSR_OUT_Pos) ///< Timer1 input capture 1 123 #define COMP_CSR_OUT_TIM2_CAPTURE4 (0x08U << COMP_CSR_OUT_Pos) ///< Timer2 input capture 4 124 #define COMP_CSR_OUT_TIM2_OCREFCLR (0x09U << COMP_CSR_OUT_Pos) ///< Timer2 ocrefclear input 125 #define COMP_CSR_OUT_TIM3_CAPTURE1 (0x0AU << COMP_CSR_OUT_Pos) ///< Timer3 input capture 1 126 #define COMP_CSR_OUT_TIM3_OCREFCLR (0x0BU << COMP_CSR_OUT_Pos) ///< Timer3 ocrefclear input 127 #define COMP_CSR_OUT_TIM8_OCREFCLR (0x0FU << COMP_CSR_OUT_Pos) ///< Timer8 ocrefclear input 128 129 #define COMP_CSR_POL_Pos (15) 130 #define COMP_CSR_POL (0x01U << COMP_CSR_POL_Pos) ///< Comparator output polarity 131 #define COMP_CSR_HYST_Pos (16) 132 #define COMP_CSR_HYST (0x03U << COMP_CSR_HYST_Pos) ///< Comparator hysteresis 133 #define COMP_CSR_HYST_0 (0x00U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 0mV 134 #define COMP_CSR_HYST_15 (0x01U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 15mV 135 #define COMP_CSR_HYST_30 (0x02U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 30mV 136 #define COMP_CSR_HYST_90 (0x03U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 90mV 137 138 #define COMP_CSR_OFLT_Pos (18) 139 #define COMP_CSR_OFLT (0x07U << COMP_CSR_OFLT_Pos) ///< Comparator output filter 140 #define COMP_CSR_OFLT_0 (0x00U << COMP_CSR_OFLT_Pos) ///< 0 clock cycle 141 #define COMP_CSR_OFLT_1 (0x01U << COMP_CSR_OFLT_Pos) ///< 2 clock cycle 142 #define COMP_CSR_OFLT_2 (0x02U << COMP_CSR_OFLT_Pos) ///< 4 clock cycle 143 #define COMP_CSR_OFLT_3 (0x03U << COMP_CSR_OFLT_Pos) ///< 8 clock cycle 144 #define COMP_CSR_OFLT_4 (0x04U << COMP_CSR_OFLT_Pos) ///< 16 clock cycle 145 #define COMP_CSR_OFLT_5 (0x05U << COMP_CSR_OFLT_Pos) ///< 32 clock cycle 146 #define COMP_CSR_OFLT_6 (0x06U << COMP_CSR_OFLT_Pos) ///< 64 clock cycle 147 #define COMP_CSR_OFLT_7 (0x07U << COMP_CSR_OFLT_Pos) ///< 128 clock cycle 148 149 #define COMP_CSR_STA_Pos (30) 150 #define COMP_CSR_STA (0x01U << COMP_CSR_STA_Pos) ///< Comparator output status 151 #define COMP_CSR_LOCK_Pos (31) 152 #define COMP_CSR_LOCK (0x01U << COMP_CSR_LOCK_Pos) ///< Comparator lock 153 154 155 //////////////////////////////////////////////////////////////////////////////// 156 /// @brief COMP_CRV Register Bit Definition 157 //////////////////////////////////////////////////////////////////////////////// 158 #define COMP_CRV_Pos (0) 159 #define COMP_CRV_MASK (0x0FU << COMP_CRV_Pos) ///< Comparator external reference voltage select 160 #define COMP_CRV_1_20 (0x00U << COMP_CRV_Pos) ///< Comparator external reference voltage select 161 #define COMP_CRV_2_20 (0x01U << COMP_CRV_Pos) ///< Comparator external reference voltage select 162 #define COMP_CRV_3_20 (0x02U << COMP_CRV_Pos) ///< Comparator external reference voltage select 163 #define COMP_CRV_4_20 (0x03U << COMP_CRV_Pos) ///< Comparator external reference voltage select 164 #define COMP_CRV_5_20 (0x04U << COMP_CRV_Pos) ///< Comparator external reference voltage select 165 #define COMP_CRV_6_20 (0x05U << COMP_CRV_Pos) ///< Comparator external reference voltage select 166 #define COMP_CRV_7_20 (0x06U << COMP_CRV_Pos) ///< Comparator external reference voltage select 167 #define COMP_CRV_8_20 (0x07U << COMP_CRV_Pos) ///< Comparator external reference voltage select 168 #define COMP_CRV_9_20 (0x08U << COMP_CRV_Pos) ///< Comparator external reference voltage select 169 #define COMP_CRV_10_20 (0x09U << COMP_CRV_Pos) ///< Comparator external reference voltage select 170 #define COMP_CRV_11_20 (0x0AU << COMP_CRV_Pos) ///< Comparator external reference voltage select 171 #define COMP_CRV_12_20 (0x0BU << COMP_CRV_Pos) ///< Comparator external reference voltage select 172 #define COMP_CRV_13_20 (0x0CU << COMP_CRV_Pos) ///< Comparator external reference voltage select 173 #define COMP_CRV_14_20 (0x0DU << COMP_CRV_Pos) ///< Comparator external reference voltage select 174 #define COMP_CRV_15_20 (0x0EU << COMP_CRV_Pos) ///< Comparator external reference voltage select 175 #define COMP_CRV_16_20 (0x0FU << COMP_CRV_Pos) ///< Comparator external reference voltage select 176 177 #define COMP_CRV_EN_Pos (4) 178 #define COMP_CRV_EN (0x01U << COMP_CRV_EN_Pos) ///< Comparator external reference voltage enable 179 #define COMP_CRV_EN_DISABLE (0x00U << COMP_CRV_EN_Pos) ///< Disable comparator external reference voltage 180 #define COMP_CRV_EN_ENABLE (0x01U << COMP_CRV_EN_Pos) ///< Enable comparator external reference voltage 181 #define COMP_CRV_SRC_Pos (5) 182 #define COMP_CRV_SRC (0x01U << COMP_CRV_SRC_Pos) ///< Comparator external reference voltage source select 183 #define COMP_CRV_SRC_VREF (0x00U << COMP_CRV_SRC_Pos) ///< Select VREF 184 #define COMP_CRV_SRC_AVDD (0x01U << COMP_CRV_SRC_Pos) ///< Select AVDD 185 186 //////////////////////////////////////////////////////////////////////////////// 187 /// @brief COMP_POL Register Bit Definition 188 //////////////////////////////////////////////////////////////////////////////// 189 #define COMP_POLL_EN_Pos (0) 190 #define COMP_POLL_EN (0x01U << COMP_POLL_EN_Pos) ///< Comparator polling enable 191 #define COMP_POLL_EN_DISABLE (0x00U << COMP_POLL_EN_Pos) ///< Disable comparator polling mode 192 #define COMP_POLL_EN_ENABLE (0x01U << COMP_POLL_EN_Pos) ///< Enable comparator polling mode 193 #define COMP_POLL_CH_Pos (1) 194 #define COMP_POLL_CH (0x01U << COMP_POLL_CH_Pos) ///< Comparator polling channel 195 #define COMP_POLL_CH_1_2 (0x00U << COMP_POLL_CH_Pos) ///< Polling channel 1/2 196 #define COMP_POLL_CH_1_2_3 (0x01U << COMP_POLL_CH_Pos) ///< Polling channel 1/2/3 197 #define COMP_POLL_FIXN_Pos (2) 198 #define COMP_POLL_FIXN (0x01U << COMP_POLL_FIXN_Pos) ///< Polling inverting input fix 199 #define COMP_POLL_FIXN_NOTFIXED (0x00U << COMP_POLL_FIXN_Pos) ///< Polling channel inverting input is not fixed 200 #define COMP_POLL_FIXN_FIXED (0x01U << COMP_POLL_FIXN_Pos) ///< Polling channel inverting input fixed 201 #define COMP_POLL_PERIOD_Pos (4) 202 #define COMP_POLL_PERIOD (0x07U << COMP_POLL_PERIOD_Pos) ///< polling wait cycle 203 #define COMP_POLL_PERIOD_1 (0x00U << COMP_POLL_PERIOD_Pos) ///< 1 clock cycle 204 #define COMP_POLL_PERIOD_2 (0x01U << COMP_POLL_PERIOD_Pos) ///< 2 clock cycle 205 #define COMP_POLL_PERIOD_4 (0x02U << COMP_POLL_PERIOD_Pos) ///< 4 clock cycle 206 #define COMP_POLL_PERIOD_8 (0x03U << COMP_POLL_PERIOD_Pos) ///< 8 clock cycle 207 #define COMP_POLL_PERIOD_16 (0x04U << COMP_POLL_PERIOD_Pos) ///< 16 clock cycle 208 #define COMP_POLL_PERIOD_32 (0x05U << COMP_POLL_PERIOD_Pos) ///< 32 clock cycle 209 #define COMP_POLL_PERIOD_64 (0x06U << COMP_POLL_PERIOD_Pos) ///< 64 clock cycle 210 #define COMP_POLL_PERIOD_128 (0x07U << COMP_POLL_PERIOD_Pos) ///< 128 clock cycle 211 #define COMP_POLL_POUT_Pos (8) 212 #define COMP_POLL_POUT (0x07U << COMP_POLL_POUT_Pos) ///< Polling output 213 #define COMP_POLL_POUT_Low (0x00U << COMP_POLL_POUT_Pos) ///< Non-inverting input is lower than inverting input 214 #define COMP_POLL_POUT_High (0x01U << COMP_POLL_POUT_Pos) ///< Non-inverting input is higher than inverting input 215 216 217 218 219 220 /// @} 221 222 /// @} 223 224 /// @} 225 226 //////////////////////////////////////////////////////////////////////////////// 227 #endif 228 //////////////////////////////////////////////////////////////////////////////// 229