1 #ifndef __IRQ_CTX_H__ 2 #define __IRQ_CTX_H__ 3 4 /**************************************************************************** 5 * Included Files 6 ****************************************************************************/ 7 8 /**************************************************************************** 9 * Pre-processor Definitions 10 ****************************************************************************/ 11 12 /* Configuration ************************************************************/ 13 14 #define CONFIG_ARCH_FPU 15 #define CONFIG_ARCH_DPFPU 16 17 /* Processor PC */ 18 19 #define REG_EPC_NDX 0 20 21 /* General pupose registers 22 * $0: Zero register does not need to be saved 23 * $1: ra (return address) 24 */ 25 26 #define REG_X1_NDX 1 27 28 /* $2: Stack POinter 29 * $3: Global Pointer 30 * $4: Thread Pointer 31 */ 32 33 #define REG_X2_NDX 2 34 #define REG_X3_NDX 3 35 #define REG_X4_NDX 4 36 37 /* $5-$7 = t0-t3: Temporary registers */ 38 39 #define REG_X5_NDX 5 40 #define REG_X6_NDX 6 41 #define REG_X7_NDX 7 42 43 /* $8: s0 / fp Frame pointer */ 44 45 #define REG_X8_NDX 8 46 47 /* $89 s1 Saved register */ 48 49 #define REG_X9_NDX 9 50 51 /* $10-$17 = a0-a7: Argument registers */ 52 53 #define REG_X10_NDX 10 54 #define REG_X11_NDX 11 55 #define REG_X12_NDX 12 56 #define REG_X13_NDX 13 57 #define REG_X14_NDX 14 58 #define REG_X15_NDX 15 59 #define REG_X16_NDX 16 60 #define REG_X17_NDX 17 61 62 /* $18-$27 = s2-s11: Saved registers */ 63 64 #define REG_X18_NDX 18 65 #define REG_X19_NDX 19 66 #define REG_X20_NDX 20 67 #define REG_X21_NDX 21 68 #define REG_X22_NDX 22 69 #define REG_X23_NDX 23 70 #define REG_X24_NDX 24 71 #define REG_X25_NDX 25 72 #define REG_X26_NDX 26 73 #define REG_X27_NDX 27 74 75 /* $28-31 = t3-t6: Temporary (Volatile) registers */ 76 77 #define REG_X28_NDX 28 78 #define REG_X29_NDX 29 79 #define REG_X30_NDX 30 80 #define REG_X31_NDX 31 81 82 /* Interrupt Context register */ 83 84 #define REG_INT_CTX_NDX 32 85 86 #define INT_XCPT_REGS 33 87 88 #define INT_XCPT_SIZE (8 * INT_XCPT_REGS) 89 90 #ifdef CONFIG_ARCH_FPU 91 92 #if defined(CONFIG_ARCH_DPFPU) 93 #define FPU_REG_SIZE 1 /* size in uint64_t */ 94 #elif defined(CONFIG_ARCH_QPFPU) 95 #define FPU_REG_SIZE 2 96 #else 97 #error not supported !!! 98 #endif 99 100 #define REG_F0_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 0) 101 #define REG_F1_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 1) 102 #define REG_F2_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 2) 103 #define REG_F3_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 3) 104 #define REG_F4_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 4) 105 #define REG_F5_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 5) 106 #define REG_F6_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 6) 107 #define REG_F7_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 7) 108 #define REG_F8_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 8) 109 #define REG_F9_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 9) 110 #define REG_F10_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 10) 111 #define REG_F11_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 11) 112 #define REG_F12_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 12) 113 #define REG_F13_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 13) 114 #define REG_F14_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 14) 115 #define REG_F15_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 15) 116 #define REG_F16_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 16) 117 #define REG_F17_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 17) 118 #define REG_F18_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 18) 119 #define REG_F19_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 19) 120 #define REG_F20_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 20) 121 #define REG_F21_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 21) 122 #define REG_F22_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 22) 123 #define REG_F23_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 23) 124 #define REG_F24_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 24) 125 #define REG_F25_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 25) 126 #define REG_F26_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 26) 127 #define REG_F27_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 27) 128 #define REG_F28_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 28) 129 #define REG_F29_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 29) 130 #define REG_F30_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 30) 131 #define REG_F31_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 31) 132 #define REG_FCSR_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 32) 133 134 #define FPU_XCPT_REGS (FPU_REG_SIZE * 33) 135 #else 136 #define FPU_XCPT_REGS 0 137 #endif 138 139 #define XCPTCONTEXT_REGS (INT_XCPT_REGS + FPU_XCPT_REGS) 140 141 #define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS) 142 143 /* In assembly language, values have to be referenced as byte address 144 * offsets. But in C, it is more convenient to reference registers as 145 * register save table offsets. 146 */ 147 148 #ifdef __ASSEMBLY__ 149 #define REG_EPC (8 * REG_EPC_NDX) 150 #define REG_X1 (8 * REG_X1_NDX) 151 #define REG_X2 (8 * REG_X2_NDX) 152 #define REG_X3 (8 * REG_X3_NDX) 153 #define REG_X4 (8 * REG_X4_NDX) 154 #define REG_X5 (8 * REG_X5_NDX) 155 #define REG_X6 (8 * REG_X6_NDX) 156 #define REG_X7 (8 * REG_X7_NDX) 157 #define REG_X8 (8 * REG_X8_NDX) 158 #define REG_X9 (8 * REG_X9_NDX) 159 #define REG_X10 (8 * REG_X10_NDX) 160 #define REG_X11 (8 * REG_X11_NDX) 161 #define REG_X12 (8 * REG_X12_NDX) 162 #define REG_X13 (8 * REG_X13_NDX) 163 #define REG_X14 (8 * REG_X14_NDX) 164 #define REG_X15 (8 * REG_X15_NDX) 165 #define REG_X16 (8 * REG_X16_NDX) 166 #define REG_X17 (8 * REG_X17_NDX) 167 #define REG_X18 (8 * REG_X18_NDX) 168 #define REG_X19 (8 * REG_X19_NDX) 169 #define REG_X20 (8 * REG_X20_NDX) 170 #define REG_X21 (8 * REG_X21_NDX) 171 #define REG_X22 (8 * REG_X22_NDX) 172 #define REG_X23 (8 * REG_X23_NDX) 173 #define REG_X24 (8 * REG_X24_NDX) 174 #define REG_X25 (8 * REG_X25_NDX) 175 #define REG_X26 (8 * REG_X26_NDX) 176 #define REG_X27 (8 * REG_X27_NDX) 177 #define REG_X28 (8 * REG_X28_NDX) 178 #define REG_X29 (8 * REG_X29_NDX) 179 #define REG_X30 (8 * REG_X30_NDX) 180 #define REG_X31 (8 * REG_X31_NDX) 181 #define REG_INT_CTX (8 * REG_INT_CTX_NDX) 182 183 #ifdef CONFIG_ARCH_FPU 184 #define REG_F0 (8 * REG_F0_NDX) 185 #define REG_F1 (8 * REG_F1_NDX) 186 #define REG_F2 (8 * REG_F2_NDX) 187 #define REG_F3 (8 * REG_F3_NDX) 188 #define REG_F4 (8 * REG_F4_NDX) 189 #define REG_F5 (8 * REG_F5_NDX) 190 #define REG_F6 (8 * REG_F6_NDX) 191 #define REG_F7 (8 * REG_F7_NDX) 192 #define REG_F8 (8 * REG_F8_NDX) 193 #define REG_F9 (8 * REG_F9_NDX) 194 #define REG_F10 (8 * REG_F10_NDX) 195 #define REG_F11 (8 * REG_F11_NDX) 196 #define REG_F12 (8 * REG_F12_NDX) 197 #define REG_F13 (8 * REG_F13_NDX) 198 #define REG_F14 (8 * REG_F14_NDX) 199 #define REG_F15 (8 * REG_F15_NDX) 200 #define REG_F16 (8 * REG_F16_NDX) 201 #define REG_F17 (8 * REG_F17_NDX) 202 #define REG_F18 (8 * REG_F18_NDX) 203 #define REG_F19 (8 * REG_F19_NDX) 204 #define REG_F20 (8 * REG_F20_NDX) 205 #define REG_F21 (8 * REG_F21_NDX) 206 #define REG_F22 (8 * REG_F22_NDX) 207 #define REG_F23 (8 * REG_F23_NDX) 208 #define REG_F24 (8 * REG_F24_NDX) 209 #define REG_F25 (8 * REG_F25_NDX) 210 #define REG_F26 (8 * REG_F26_NDX) 211 #define REG_F27 (8 * REG_F27_NDX) 212 #define REG_F28 (8 * REG_F28_NDX) 213 #define REG_F29 (8 * REG_F29_NDX) 214 #define REG_F30 (8 * REG_F30_NDX) 215 #define REG_F31 (8 * REG_F31_NDX) 216 #define REG_FCSR (8 * REG_FCSR_NDX) 217 #endif 218 219 #else 220 #define REG_EPC REG_EPC_NDX 221 #define REG_X1 REG_X1_NDX 222 #define REG_X2 REG_X2_NDX 223 #define REG_X3 REG_X3_NDX 224 #define REG_X4 REG_X4_NDX 225 #define REG_X5 REG_X5_NDX 226 #define REG_X6 REG_X6_NDX 227 #define REG_X7 REG_X7_NDX 228 #define REG_X8 REG_X8_NDX 229 #define REG_X9 REG_X9_NDX 230 #define REG_X10 REG_X10_NDX 231 #define REG_X11 REG_X11_NDX 232 #define REG_X12 REG_X12_NDX 233 #define REG_X13 REG_X13_NDX 234 #define REG_X14 REG_X14_NDX 235 #define REG_X15 REG_X15_NDX 236 #define REG_X16 REG_X16_NDX 237 #define REG_X17 REG_X17_NDX 238 #define REG_X18 REG_X18_NDX 239 #define REG_X19 REG_X19_NDX 240 #define REG_X20 REG_X20_NDX 241 #define REG_X21 REG_X21_NDX 242 #define REG_X22 REG_X22_NDX 243 #define REG_X23 REG_X23_NDX 244 #define REG_X24 REG_X24_NDX 245 #define REG_X25 REG_X25_NDX 246 #define REG_X26 REG_X26_NDX 247 #define REG_X27 REG_X27_NDX 248 #define REG_X28 REG_X28_NDX 249 #define REG_X29 REG_X29_NDX 250 #define REG_X30 REG_X30_NDX 251 #define REG_X31 REG_X31_NDX 252 #define REG_INT_CTX REG_INT_CTX_NDX 253 254 #ifdef CONFIG_ARCH_FPU 255 #define REG_F0 REG_F0_NDX 256 #define REG_F1 REG_F1_NDX 257 #define REG_F2 REG_F2_NDX 258 #define REG_F3 REG_F3_NDX 259 #define REG_F4 REG_F4_NDX 260 #define REG_F5 REG_F5_NDX 261 #define REG_F6 REG_F6_NDX 262 #define REG_F7 REG_F7_NDX 263 #define REG_F8 REG_F8_NDX 264 #define REG_F9 REG_F9_NDX 265 #define REG_F10 REG_F10_NDX 266 #define REG_F11 REG_F11_NDX 267 #define REG_F12 REG_F12_NDX 268 #define REG_F13 REG_F13_NDX 269 #define REG_F14 REG_F14_NDX 270 #define REG_F15 REG_F15_NDX 271 #define REG_F16 REG_F16_NDX 272 #define REG_F17 REG_F17_NDX 273 #define REG_F18 REG_F18_NDX 274 #define REG_F19 REG_F19_NDX 275 #define REG_F20 REG_F20_NDX 276 #define REG_F21 REG_F21_NDX 277 #define REG_F22 REG_F22_NDX 278 #define REG_F23 REG_F23_NDX 279 #define REG_F24 REG_F24_NDX 280 #define REG_F25 REG_F25_NDX 281 #define REG_F26 REG_F26_NDX 282 #define REG_F27 REG_F27_NDX 283 #define REG_F28 REG_F28_NDX 284 #define REG_F29 REG_F29_NDX 285 #define REG_F30 REG_F30_NDX 286 #define REG_F31 REG_F31_NDX 287 #define REG_FCSR REG_FCSR_NDX 288 #endif 289 290 #endif 291 292 /* Now define more user friendly alternative name that can be used either 293 * in assembly or C contexts. 294 */ 295 296 /* $1 = ra: Return address */ 297 298 #define REG_RA REG_X1 299 300 /* $2 = sp: The value of the stack pointer on return from the exception */ 301 302 #define REG_SP REG_X2 303 304 /* $3 = gp: Only needs to be saved under conditions where there are 305 * multiple, per-thread values for the GP. 306 */ 307 308 #define REG_GP REG_X3 309 310 /* $4 = tp: Thread Pointer */ 311 312 #define REG_TP REG_X4 313 314 /* $5-$7 = t0-t2: Caller saved temporary registers */ 315 316 #define REG_T0 REG_X5 317 #define REG_T1 REG_X6 318 #define REG_T2 REG_X7 319 320 /* $8 = either s0 or fp: Depends if a frame pointer is used or not */ 321 322 #define REG_S0 REG_X8 323 #define REG_FP REG_X8 324 325 /* $9 = s1: Caller saved register */ 326 327 #define REG_S1 REG_X9 328 329 /* $10-$17 = a0-a7: Argument registers */ 330 331 #define REG_A0 REG_X10 332 #define REG_A1 REG_X11 333 #define REG_A2 REG_X12 334 #define REG_A3 REG_X13 335 #define REG_A4 REG_X14 336 #define REG_A5 REG_X15 337 #define REG_A6 REG_X16 338 #define REG_A7 REG_X17 339 340 /* $18-$27 = s2-s11: Callee saved registers */ 341 342 #define REG_S2 REG_X18 343 #define REG_S3 REG_X19 344 #define REG_S4 REG_X20 345 #define REG_S5 REG_X21 346 #define REG_S6 REG_X22 347 #define REG_S7 REG_X23 348 #define REG_S8 REG_X24 349 #define REG_S9 REG_X25 350 #define REG_S10 REG_X26 351 #define REG_S11 REG_X27 352 353 /* $28-$31 = t3-t6: Caller saved temporary registers */ 354 355 #define REG_T3 REG_X28 356 #define REG_T4 REG_X29 357 #define REG_T5 REG_X30 358 #define REG_T6 REG_X31 359 360 /**************************************************************************** 361 * Public Types 362 ****************************************************************************/ 363 364 /**************************************************************************** 365 * Public Variables 366 ****************************************************************************/ 367 368 /**************************************************************************** 369 * Public Function Prototypes 370 ****************************************************************************/ 371 372 #endif /* __IRQ_CTX_H__ */ 373