1 /** @file system.h 2 * @brief System Driver Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * . 10 * which are relevant for the System driver. 11 */ 12 13 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 14 15 #ifndef __SYS_SYSTEM_H__ 16 #define __SYS_SYSTEM_H__ 17 18 #include "reg_system.h" 19 #include "reg_flash.h" 20 #include "reg_tcram.h" 21 #include "gio.h" 22 23 24 /* USER CODE BEGIN (0) */ 25 /* USER CODE END */ 26 27 28 /* System General Definitions */ 29 30 /** @enum systemInterrupt 31 * @brief Alias names for clock sources 32 * 33 * This enumeration is used to provide alias names for the clock sources: 34 * - IRQ 35 * - FIQ 36 */ 37 enum systemInterrupt 38 { 39 SYS_IRQ, /**< Alias for IRQ interrupt */ 40 SYS_FIQ /**< Alias for FIQ interrupt */ 41 }; 42 43 /** @enum systemClockSource 44 * @brief Alias names for clock sources 45 * 46 * This enumeration is used to provide alias names for the clock sources: 47 * - Oscillator 48 * - Pll1 49 * - External1 50 * - Low Power Oscillator Low 51 * - Low Power Oscillator High 52 * - PLL2 53 * - External2 54 * - Synchronous VCLK1 55 */ 56 enum systemClockSource 57 { 58 SYS_OSC = 0U, /**< Alias for oscillator clock Source */ 59 SYS_PLL1 = 1U, /**< Alias for Pll1 clock Source */ 60 SYS_EXTERNAL1 = 3U, /**< Alias for external clock Source */ 61 SYS_LPO_LOW = 4U, /**< Alias for low power oscillator low clock Source */ 62 SYS_LPO_HIGH = 5U, /**< Alias for low power oscillator high clock Source */ 63 SYS_PLL2 = 6U, /**< Alias for Pll2 clock Source */ 64 SYS_EXTERNAL2 = 7U, /**< Alias for external 2 clock Source */ 65 SYS_VCLK = 9U /**< Alias for synchronous VCLK1 clock Source */ 66 }; 67 68 #define SYS_DOZE_MODE 0x000F3F02U 69 #define SYS_SNOOZE_MODE 0x000F3F03U 70 #define SYS_SLEEP_MODE 0x000FFFFFU 71 #define LPO_TRIM_VALUE (((*(volatile uint32 *)0xF00801B4U) & 0xFFFF0000U)>>16U) 72 #define SYS_EXCEPTION (*(volatile uint32 *)0xFFFFFFE4U) 73 74 #define POWERON_RESET 0x8000U 75 #define OSC_FAILURE_RESET 0x4000U 76 #define WATCHDOG_RESET 0x2000U 77 #define ICEPICK_RESET 0x2000U 78 #define CPU_RESET 0x0020U 79 #define SW_RESET 0x0010U 80 81 #define WATCHDOG_STATUS (*(volatile uint32 *)0xFFFFFC98U) 82 #define DEVICE_ID_REV (*(volatile uint32 *)0xFFFFFFF0U) 83 84 /** @def OSC_FREQ 85 * @brief Oscillator clock source exported from HALCoGen GUI 86 * 87 * Oscillator clock source exported from HALCoGen GUI 88 */ 89 #define OSC_FREQ 16.0F 90 91 /** @def PLL1_FREQ 92 * @brief PLL 1 clock source exported from HALCoGen GUI 93 * 94 * PLL 1 clock source exported from HALCoGen GUI 95 */ 96 #define PLL1_FREQ 200.00F 97 98 /** @def LPO_LF_FREQ 99 * @brief LPO Low Freq Oscillator source exported from HALCoGen GUI 100 * 101 * LPO Low Freq Oscillator source exported from HALCoGen GUI 102 */ 103 #define LPO_LF_FREQ 0.080F 104 105 /** @def LPO_HF_FREQ 106 * @brief LPO High Freq Oscillator source exported from HALCoGen GUI 107 * 108 * LPO High Freq Oscillator source exported from HALCoGen GUI 109 */ 110 #define LPO_HF_FREQ 10.000F 111 112 /** @def PLL1_FREQ 113 * @brief PLL 2 clock source exported from HALCoGen GUI 114 * 115 * PLL 2 clock source exported from HALCoGen GUI 116 */ 117 #define PLL2_FREQ 200.00F 118 119 /** @def GCLK_FREQ 120 * @brief GCLK domain frequency exported from HALCoGen GUI 121 * 122 * GCLK domain frequency exported from HALCoGen GUI 123 */ 124 #define GCLK_FREQ 200.000F 125 126 /** @def HCLK_FREQ 127 * @brief HCLK domain frequency exported from HALCoGen GUI 128 * 129 * HCLK domain frequency exported from HALCoGen GUI 130 */ 131 #define HCLK_FREQ 200.000F 132 133 /** @def RTI_FREQ 134 * @brief RTI Clock frequency exported from HALCoGen GUI 135 * 136 * RTI Clock frequency exported from HALCoGen GUI 137 */ 138 #define RTI_FREQ 100.000F 139 140 /** @def AVCLK1_FREQ 141 * @brief AVCLK1 Domain frequency exported from HALCoGen GUI 142 * 143 * AVCLK Domain frequency exported from HALCoGen GUI 144 */ 145 #define AVCLK1_FREQ 100.000F 146 147 /** @def AVCLK2_FREQ 148 * @brief AVCLK2 Domain frequency exported from HALCoGen GUI 149 * 150 * AVCLK2 Domain frequency exported from HALCoGen GUI 151 */ 152 #define AVCLK2_FREQ 100.0F 153 154 /** @def AVCLK3_FREQ 155 * @brief AVCLK3 Domain frequency exported from HALCoGen GUI 156 * 157 * AVCLK3 Domain frequency exported from HALCoGen GUI 158 */ 159 #define AVCLK3_FREQ 100.000F 160 161 /** @def VCLK1_FREQ 162 * @brief VCLK1 Domain frequency exported from HALCoGen GUI 163 * 164 * VCLK1 Domain frequency exported from HALCoGen GUI 165 */ 166 #define VCLK1_FREQ 100.000F 167 168 /** @def VCLK2_FREQ 169 * @brief VCLK2 Domain frequency exported from HALCoGen GUI 170 * 171 * VCLK2 Domain frequency exported from HALCoGen GUI 172 */ 173 #define VCLK2_FREQ 100.000F 174 175 176 /** @def SYS_PRE1 177 * @brief Alias name for RTI1CLK PRE clock source 178 * 179 * This is an alias name for the RTI1CLK pre clock source. 180 * This can be either: 181 * - Oscillator 182 * - Pll 183 * - 32 kHz Oscillator 184 * - External 185 * - Low Power Oscillator Low 186 * - Low Power Oscillator High 187 * - Flexray Pll 188 */ 189 /*SAFETYMCUSW 79 S MR:19.4 <REVIEWED> "Macro filled using GUI parameter cannot be avoided" */ 190 #define SYS_PRE1 SYS_PLL1 191 192 /** @def SYS_PRE2 193 * @brief Alias name for RTI2CLK pre clock source 194 * 195 * This is an alias name for the RTI2CLK pre clock source. 196 * This can be either: 197 * - Oscillator 198 * - Pll 199 * - 32 kHz Oscillator 200 * - External 201 * - Low Power Oscillator Low 202 * - Low Power Oscillator High 203 * - Flexray Pll 204 */ 205 /*SAFETYMCUSW 79 S MR:19.4 <REVIEWED> "Macro filled using GUI parameter cannot be avoided" */ 206 #define SYS_PRE2 SYS_PLL1 207 208 /* Configuration registers */ 209 typedef struct system_config_reg 210 { 211 uint32 CONFIG_SYSPC1; 212 uint32 CONFIG_SYSPC2; 213 uint32 CONFIG_SYSPC7; 214 uint32 CONFIG_SYSPC8; 215 uint32 CONFIG_SYSPC9; 216 uint32 CONFIG_CSDIS; 217 uint32 CONFIG_CDDIS; 218 uint32 CONFIG_GHVSRC; 219 uint32 CONFIG_VCLKASRC; 220 uint32 CONFIG_RCLKSRC; 221 uint32 CONFIG_MSTGCR; 222 uint32 CONFIG_MINITGCR; 223 uint32 CONFIG_MSINENA; 224 uint32 CONFIG_PLLCTL1; 225 uint32 CONFIG_PLLCTL2; 226 uint32 CONFIG_UERFLAG; 227 uint32 CONFIG_LPOMONCTL; 228 uint32 CONFIG_CLKTEST; 229 uint32 CONFIG_DFTCTRLREG1; 230 uint32 CONFIG_DFTCTRLREG2; 231 uint32 CONFIG_GPREG1; 232 uint32 CONFIG_RAMGCR; 233 uint32 CONFIG_BMMCR1; 234 uint32 CONFIG_MMUGCR; 235 uint32 CONFIG_CLKCNTL; 236 uint32 CONFIG_ECPCNTL; 237 uint32 CONFIG_DEVCR1; 238 uint32 CONFIG_SYSECR; 239 uint32 CONFIG_PLLCTL3; 240 uint32 CONFIG_STCCLKDIV; 241 uint32 CONFIG_CLK2CNTL; 242 uint32 CONFIG_VCLKACON1; 243 uint32 CONFIG_CLKSLIP; 244 uint32 CONFIG_EFC_CTLEN; 245 } system_config_reg_t; 246 247 /* Configuration registers initial value */ 248 #define SYS_SYSPC1_CONFIGVALUE 0U 249 250 #define SYS_SYSPC2_CONFIGVALUE 1U 251 252 #define SYS_SYSPC7_CONFIGVALUE 0U 253 254 #define SYS_SYSPC8_CONFIGVALUE 0U 255 256 #define SYS_SYSPC9_CONFIGVALUE 1U 257 258 #define SYS_CSDIS_CONFIGVALUE 0x00000000U\ 259 | 0x00000000U \ 260 | 0x00000008U \ 261 | 0x00000080U \ 262 | 0x00000000U \ 263 | 0x00000000U \ 264 | 0x00000000U\ 265 | (1U << 2U) 266 267 #define SYS_CDDIS_CONFIGVALUE (FALSE << 4U )\ 268 |(TRUE << 5U )\ 269 |(FALSE << 8U )\ 270 |(FALSE << 10U)\ 271 |(FALSE << 11U) 272 273 #define SYS_GHVSRC_CONFIGVALUE (SYS_PLL1 << 24U) \ 274 | (SYS_PLL1 << 16U) \ 275 | SYS_PLL1 276 277 #define SYS_VCLKASRC_CONFIGVALUE (SYS_VCLK << 8U)\ 278 | SYS_VCLK 279 280 #define SYS_RCLKSRC_CONFIGVALUE (1U << 24U)\ 281 | (SYS_VCLK << 16U)\ 282 | (1U << 8U)\ 283 | SYS_VCLK 284 285 #define SYS_MSTGCR_CONFIGVALUE 0x00000105U 286 287 #define SYS_MINITGCR_CONFIGVALUE 0x5U 288 289 #define SYS_MSINENA_CONFIGVALUE 0U 290 291 #define SYS_PLLCTL1_CONFIGVALUE_1 0x00000000U \ 292 | 0x20000000U \ 293 | ((0x1FU)<< 24U) \ 294 | 0x00000000U \ 295 | ((6U - 1U)<< 16U)\ 296 | ((150U - 1U)<< 8U) 297 298 #define SYS_PLLCTL1_CONFIGVALUE_2 ( (SYS_PLLCTL1_CONFIGVALUE_1) & 0xE0FFFFFFU)|((1U - 1U)<< 24U) 299 300 #define SYS_PLLCTL2_CONFIGVALUE 0x00000000U\ 301 | (255U << 22U)\ 302 | (7U << 12U)\ 303 | ((2U - 1U)<< 9U)\ 304 | 61U 305 306 #define SYS_UERFLAG_CONFIGVALUE 0U 307 308 #define SYS_LPOMONCTL_CONFIGVALUE_1 (1U << 24U) | LPO_TRIM_VALUE 309 #define SYS_LPOMONCTL_CONFIGVALUE_2 (1U << 24U) | (16U << 8U) | 8U 310 311 #define SYS_CLKTEST_CONFIGVALUE 0x000A0000U 312 313 #define SYS_DFTCTRLREG1_CONFIGVALUE 0x00002205U 314 315 #define SYS_DFTCTRLREG2_CONFIGVALUE 0x5U 316 317 #define SYS_GPREG1_CONFIGVALUE 0x0005FFFFU 318 319 #define SYS_RAMGCR_CONFIGVALUE 0x00050000U 320 321 #define SYS_BMMCR1_CONFIGVALUE 0xAU 322 323 #define SYS_MMUGCR_CONFIGVALUE 0U 324 325 #define SYS_CLKCNTL_CONFIGVALUE (1U << 8U) \ 326 | (1U << 16U) \ 327 | (1U << 24U) 328 329 #define SYS_ECPCNTL_CONFIGVALUE (0U << 24U)\ 330 | (0U << 23U)\ 331 | ((8U - 1U) & 0xFFFFU) 332 333 #define SYS_DEVCR1_CONFIGVALUE 0xAU 334 335 #define SYS_SYSECR_CONFIGVALUE 0x00004000U 336 #define SYS2_PLLCTL3_CONFIGVALUE_1 ((2U - 1U) << 29U)\ 337 | ((0x1FU)<< 24U) \ 338 | ((6U - 1U)<< 16U) \ 339 | ((150U - 1U) << 8U) 340 341 #define SYS2_PLLCTL3_CONFIGVALUE_2 ((SYS2_PLLCTL3_CONFIGVALUE_1) & 0xE0FFFFFFU)|((1U - 1U)<< 24U) 342 #define SYS2_STCCLKDIV_CONFIGVALUE 0U 343 #define SYS2_CLK2CNTL_CONFIGVALUE (1U) \ 344 | (1U << 8U) 345 #define SYS2_VCLKACON1_CONFIGVALUE (1U << 24U) \ 346 | (1U << 20U) \ 347 | (SYS_VCLK << 16U)\ 348 | (1U << 8U)\ 349 | (1U << 4U) \ 350 | SYS_VCLK 351 #define SYS2_CLKSLIP_CONFIGVALUE 0x5U 352 #define SYS2_EFC_CTLEN_CONFIGVALUE 0x5U 353 354 void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type); 355 356 /* USER CODE BEGIN (1) */ 357 /* USER CODE END */ 358 359 /* FlashW General Definitions */ 360 361 362 /** @enum flashWPowerModes 363 * @brief Alias names for flash bank power modes 364 * 365 * This enumeration is used to provide alias names for the flash bank power modes: 366 * - sleep 367 * - standby 368 * - active 369 */ 370 enum flashWPowerModes 371 { 372 SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */ 373 SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */ 374 SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */ 375 }; 376 377 /* USER CODE BEGIN (2) */ 378 /* USER CODE END */ 379 380 381 #define FSM_WR_ENA_HL (*(volatile uint32 *)0xFFF87288U) 382 #define EEPROM_CONFIG_HL (*(volatile uint32 *)0xFFF872B8U) 383 384 /* Configuration registers */ 385 typedef struct tcmflash_config_reg 386 { 387 uint32 CONFIG_FRDCNTL; 388 uint32 CONFIG_FEDACCTRL1; 389 uint32 CONFIG_FEDACCTRL2; 390 uint32 CONFIG_FEDACSDIS; 391 uint32 CONFIG_FBPROT; 392 uint32 CONFIG_FBSE; 393 uint32 CONFIG_FBAC; 394 uint32 CONFIG_FBFALLBACK; 395 uint32 CONFIG_FPAC1; 396 uint32 CONFIG_FPAC2; 397 uint32 CONFIG_FMAC; 398 uint32 CONFIG_FLOCK; 399 uint32 CONFIG_FDIAGCTRL; 400 uint32 CONFIG_FEDACSDIS2; 401 } tcmflash_config_reg_t; 402 403 /* Configuration registers initial value */ 404 #define TCMFLASH_FRDCNTL_CONFIGVALUE 0x00000000U | (3U << 8U) | (1U << 4U) | 1U 405 #define TCMFLASH_FEDACCTRL1_CONFIGVALUE 0x000A0005U 406 #define TCMFLASH_FEDACCTRL2_CONFIGVALUE 0U 407 #define TCMFLASH_FEDACSDIS_CONFIGVALUE 0U 408 #define TCMFLASH_FBPROT_CONFIGVALUE 0U 409 #define TCMFLASH_FBSE_CONFIGVALUE 0U 410 #define TCMFLASH_FBAC_CONFIGVALUE 0xFU 411 #define TCMFLASH_FBFALLBACK_CONFIGVALUE 0x00000000U\ 412 | (SYS_ACTIVE << 14U) \ 413 | (SYS_SLEEP << 12U) \ 414 | (SYS_SLEEP << 10U) \ 415 | (SYS_SLEEP << 8U) \ 416 | (SYS_SLEEP << 6U) \ 417 | (SYS_SLEEP << 4U) \ 418 | (SYS_ACTIVE << 2U) \ 419 | SYS_ACTIVE \ 420 421 #define TCMFLASH_FPAC1_CONFIGVALUE 0x00C80001U 422 #define TCMFLASH_FPAC2_CONFIGVALUE 0U 423 #define TCMFLASH_FMAC_CONFIGVALUE 0U 424 #define TCMFLASH_FLOCK_CONFIGVALUE 0x55AAU 425 #define TCMFLASH_FDIAGCTRL_CONFIGVALUE 0x000A0000U 426 #define TCMFLASH_FEDACSDIS2_CONFIGVALUE 0U 427 428 void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type); 429 430 /* USER CODE BEGIN (3) */ 431 /* USER CODE END */ 432 433 434 /* System Interface Functions */ 435 void setupPLL(void); 436 void trimLPO(void); 437 void setupFlash(void); 438 void periphInit(void); 439 void mapClocks(void); 440 void systemInit(void); 441 void systemPowerDown(uint32 mode); 442 443 444 /*Configuration registers 445 * index 0: Even RAM 446 * index 1: Odd RAM 447 */ 448 typedef struct sram_config_reg 449 { 450 uint32 CONFIG_RAMCTRL[2U]; 451 uint32 CONFIG_RAMTHRESHOLD[2U]; 452 uint32 CONFIG_RAMINTCTRL[2U]; 453 uint32 CONFIG_RAMTEST[2U]; 454 uint32 CONFIG_RAMADDRDECVECT[2U]; 455 } sram_config_reg_t; 456 457 /* Configuration registers initial value */ 458 #define SRAM_RAMCTRL_CONFIGVALUE 0x0005000AU 459 #define SRAM_RAMTHRESHOLD_CONFIGVALUE 1U 460 #define SRAM_RAMINTCTRL_CONFIGVALUE 1U 461 #define SRAM_RAMTEST_CONFIGVALUE 0x5U 462 #define SRAM_RAMADDRDECVECT_CONFIGVALUE 0U 463 464 void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type); 465 #endif 466