1 /* 2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /**************************************************************************//** 18 * @file soc.h 19 * @brief CSI Core Peripheral Access Layer Header File for 20 * CSKYSOC Device Series 21 * @version V1.0 22 * @date 02. June 2017 23 ******************************************************************************/ 24 25 #ifndef SOC_H 26 #define SOC_H 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 #define SYSTEM_CLOCK (20000000) 33 34 /* ------------------------- Interrupt Number Definition ------------------------ */ 35 36 typedef enum IRQn 37 { 38 /* ---------------------- CSKYCK801 Specific Interrupt Numbers --------------------- */ 39 GPIOA_IRQn = 0, 40 CORET_IRQn = 1, /* core Timer Interrupt */ 41 TIMA0_IRQn = 2, /* timerA0 Interrupt */ 42 TIMA1_IRQn = 3, /* timerA1 Interrupt */ 43 WDT_IRQn = 5, /* wdt Interrupt */ 44 UART0_IRQn = 6, /* uart0 Interrupt */ 45 UART1_IRQn = 7, /* uart1 Interrupt */ 46 UART2_IRQn = 8, /* uart2 Interrupt */ 47 I2C0_IRQn = 9, /* i2c0 Interrupt */ 48 I2C1_IRQn = 10, /* i2c1 Interrupt */ 49 SPI1_IRQn = 11, /* spi0 Interrupt */ 50 SPI0_IRQn = 12, /* spi1 Interrupt */ 51 RTC_IRQn = 13, /* rtc Interrupt */ 52 EXTWAK_IRQn = 14, /* extwakeup Interrupt */ 53 DMAC_IRQn = 17, /* dmac Interrupt */ 54 PMU_IRQn = 18, /* pmu Interrupt */ 55 PWM_IRQn = 19, /* pwm Interrupt */ 56 UART3_IRQn = 21, /* uart3 Interrupt */ 57 TIMB0_IRQn = 23, /* timerB0 Interrupt */ 58 TIMB1_IRQn = 24, /* timerB1 Interrupt */ 59 GPIOB_IRQn = 27, /* GPIOB Interrupt */ 60 AES_IRQn = 26, /* aes Interrupt */ 61 RSA_IRQn = 28, /* rsa Interrupt */ 62 SHA_IRQn = 29, /* sha Interrupt */ 63 64 } 65 IRQn_Type; 66 67 /* ================================================================================ */ 68 /* ================ Processor and Core Peripheral Section ================ */ 69 /* ================================================================================ */ 70 71 /* -------- Configuration of the CK801 Processor and Core Peripherals ------- */ 72 #define __CK802_REV 0x0000U /* Core revision r0p0 */ 73 #define __MGU_PRESENT 0 /* MGU present or not */ 74 #define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */ 75 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ 76 77 #include "core_ck802.h" /* Processor and core peripherals */ 78 #include "stdint.h" 79 80 typedef enum 81 { 82 CKENUM_DMA_UART0_RX, 83 CKENUM_DMA_UART0_TX, 84 CKENUM_DMA_UART1_RX, 85 CKENUM_DMA_UART1_TX, 86 CKENUM_DMA_ADC_RX, 87 CKENUM_DMA_ADC_TX, 88 CKENUM_DMA_SPI1_RX, 89 CKENUM_DMA_SPI1_TX, 90 CKENUM_DMA_SPI0_RX, 91 CKENUM_DMA_SPI0_TX, 92 CKENUM_DMA_IIC_RX, 93 CKENUM_DMA_IIC_TX, 94 CKENUM_DMA_IIC1_RX, 95 CKENUM_DMA_IIC1_TX, 96 CKENUM_DMA_IIS_RX, 97 CKENUM_DMA_IIS_TX, 98 CKENUM_DMA_MEMORY 99 } ckenum_dma_device_e; 100 101 /* ================================================================================ */ 102 /* ================ Device Specific Peripheral Section ================ */ 103 /* ================================================================================ */ 104 #if 0 105 106 /* ================================================================================ */ 107 /* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */ 108 /* ================================================================================ */ 109 typedef struct 110 { 111 union 112 { 113 __IM uint32_t RBR; /* Offset: 0x000 (R/ ) Receive buffer register */ 114 __OM uint32_t THR; /* Offset: 0x000 ( /W) Transmission hold register */ 115 __IOM uint32_t DLL; /* Offset: 0x000 (R/W) Clock frequency division low section register */ 116 }; 117 union 118 { 119 __IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section register */ 120 __IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt enable register */ 121 }; 122 __IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt indicia register */ 123 __IOM uint32_t LCR; /* Offset: 0x00C (R/W) Transmission control register */ 124 __IOM uint32_t MCR; /* Offset: 0x010 (R/W) Modem control register */ 125 __IM uint32_t LSR; /* Offset: 0x014 (R/ ) Transmission state register */ 126 __IM uint32_t MSR; /* Offset: 0x018 (R/ ) Modem state register */ 127 uint32_t RESERVED1[24]; 128 __IM uint32_t USR; /* Offset: 0x07c (R/ ) UART state register */ 129 } CSKY_UART_TypeDef; 130 131 /* ================================================================================ */ 132 /* ============== Inter-Integrated Circuit (IIC) ============= */ 133 /* ================================================================================ */ 134 typedef struct 135 { 136 __IOM uint32_t IC_CON; /* Offset: 0x000 (R/W) Receive buffer register */ 137 __IOM uint32_t IC_TAR; /* Offset: 0x004 (R/W) Transmission hold register */ 138 __IOM uint32_t IC_SAR; /* Offset: 0x008 (R/W) Clock frequency division low section register */ 139 __IOM uint32_t IC_HS_MADDR; /* Offset: 0x00c (R/W) Clock frequency division high section register */ 140 __IOM uint32_t IC_DATA_CMD; /* Offset: 0x010 (R/W) Interrupt enable register */ 141 __IOM uint32_t IC_SS_SCL_HCNT; /* Offset: 0x014 (R/W) Interrupt indicia register */ 142 __IOM uint32_t IC_SS_SCL_LCNT; /* Offset: 0x018 (R/W) Transmission control register */ 143 __IOM uint32_t IC_FS_SCL_HCNT; /* Offset: 0x01c (R/W) Modem control register */ 144 __IOM uint32_t IC_FS_SCL_LCNT; /* Offset: 0x020 (R/W) Transmission state register */ 145 __IOM uint32_t IC_HS_SCL_HCNT; /* Offset: 0x024 (R/W) Transmission state register */ 146 __IOM uint32_t IC_HS_SCL_LCNT; /* Offset: 0x028 (R/W) Transmission state register */ 147 __IOM uint32_t IC_INTR_STAT; /* Offset: 0x02c (R) Transmission state register */ 148 __IOM uint32_t IC_INTR_MASK; /* Offset: 0x030 (R/W) Transmission state register */ 149 __IOM uint32_t IC_RAW_INTR_STAT; /* Offset: 0x034 (R) Transmission state register */ 150 __IOM uint32_t IC_RX_TL; /* Offset: 0x038 (R/W) Transmission state register */ 151 __IOM uint32_t IC_TX_TL; /* Offset: 0x03c (R/W) Transmission state register */ 152 __IOM uint32_t IC_CLR_INTR; /* Offset: 0x040 (R) Transmission state register */ 153 __IOM uint32_t IC_CLR_RX_UNDER; /* Offset: 0x044 (R) Transmission state register */ 154 __IOM uint32_t IC_CLR_RX_OVER; /* Offset: 0x048 (R) Transmission state register */ 155 __IOM uint32_t IC_CLR_TX_OVER; /* Offset: 0x04c (R) Transmission state register */ 156 __IOM uint32_t IC_CLR_RD_REQ; /* Offset: 0x050 (R) Transmission state register */ 157 __IOM uint32_t IC_CLR_TX_ABRT; /* Offset: 0x054 (R) Transmission state register */ 158 __IOM uint32_t IC_CLR_RX_DONE; /* Offset: 0x058 (R) Transmission state register */ 159 __IOM uint32_t IC_CLR_ACTIVITY; /* Offset: 0x05c (R) Transmission state register */ 160 __IOM uint32_t IC_CLR_STOP_DET; /* Offset: 0x060 (R) Transmission state register */ 161 __IOM uint32_t IC_CLR_START_DET; /* Offset: 0x064 (R) Transmission state register */ 162 __IOM uint32_t IC_CLR_GEN_CALL; /* Offset: 0x068 (R) Transmission state register */ 163 __IOM uint32_t IC_ENABLE; /* Offset: 0x06c (R/W) Transmission state register */ 164 __IOM uint32_t IC_STATUS; /* Offset: 0x070 (R) Transmission state register */ 165 __IOM uint32_t IC_TXFLR; /* Offset: 0x074 (R) Transmission state register */ 166 __IOM uint32_t IC_RXFLR; /* Offset: 0x078 (R) Transmission state register */ 167 uint32_t RESERVED; /* Offset: 0x014 (R/ ) Transmission state register */ 168 __IOM uint32_t IC_TX_ABRT_SOURCE; /* Offset: 0x080 (R/W) Transmission state register */ 169 __IOM uint32_t IC_SAR1; /* Offset: 0x084 (R/W) Transmission state register */ 170 __IOM uint32_t IC_DMA_CR; /* Offset: 0x088 (R/W) Transmission state register */ 171 __IOM uint32_t IC_DMA_TDLR; /* Offset: 0x08c (R/W) Transmission state register */ 172 __IOM uint32_t IC_DMA_RDLR; /* Offset: 0x090 (R/W) Transmission state register */ 173 __IOM uint32_t IC_SAR2; /* Offset: 0x094 (R/W) Transmission state register */ 174 __IOM uint32_t IC_SAR3; /* Offset: 0x098 (R/W) Transmission state register */ 175 __IOM uint32_t IC_MULTI_SLAVE; /* Offset: 0x09c (R/W) Transmission state register */ 176 __IOM uint32_t IC_GEN_CALL_EN; /* Offset: 0x0a0 (R/W) Transmission state register */ 177 178 } CSKY_IIC_TypeDef; 179 180 /* ================================================================================ */ 181 /* ============== TIMER ============= */ 182 /* ================================================================================ */ 183 typedef struct 184 { 185 __IOM uint32_t TxLoadCount; /* Offset: 0x000 (R/W) Receive buffer register */ 186 __IOM uint32_t TxCurrentValue; /* Offset: 0x004 (R) Transmission hold register */ 187 __IOM uint32_t TxControl; /* Offset: 0x008 (R/W) Clock frequency division low section register */ 188 __IOM uint32_t TxEOI; /* Offset: 0x00c (R) Clock frequency division high section register */ 189 __IOM uint32_t TxIntStatus; /* Offset: 0x010 (R) Interrupt enable register */ 190 191 } CSKY_TIMER_TypeDef; 192 193 /* ================================================================================ */ 194 /* ============== TIMER Control ============= */ 195 /* ================================================================================ */ 196 typedef struct 197 { 198 __IOM uint32_t TimersIntStatus; /* Offset: 0x000 (R) Interrupt indicia register */ 199 __IOM uint32_t TimerEOI; /* Offset: 0x004 (R) Transmission control register */ 200 __IOM uint32_t TimerRawIntStatus; /* Offset: 0x008 (R) Modem control register */ 201 202 } CSKY_TIMER_Control_TypeDef; 203 204 /* ================================================================================ */ 205 /* ============== GPIO ============= */ 206 /* ================================================================================ */ 207 typedef struct 208 { 209 __IOM uint32_t SWPORT_DR; /* Offset: 0x000 (R/W) Interrupt indicia register */ 210 __IOM uint32_t SWPORT_DDR; /* Offset: 0x004 (R/W) Interrupt indicia register */ 211 __IOM uint32_t PORT_CTL; /* Offset: 0x008 (R/W) Interrupt indicia register */ 212 } CKStruct_GPIO, *PCKStruct_GPIO; 213 214 typedef struct 215 { 216 __IOM uint32_t SHA_CON; /* Offset: 0x000 (R/W) Control register */ 217 __IOM uint32_t SHA_INTSTATE; /* Offset: 0x004 (R/W) Instatus register */ 218 __IOM uint32_t SHA_H0L; /* Offset: 0x008 (R/W) H0L register */ 219 __IOM uint32_t SHA_H1L; /* Offset: 0x00c (R/W) H1L register */ 220 __IOM uint32_t SHA_H2L; /* Offset: 0x010 (R/W) H2L register */ 221 __IOM uint32_t SHA_H3L; /* Offset: 0x014 (R/W) H3L register */ 222 __IOM uint32_t SHA_H4L; /* Offset: 0x018 (R/W) H4L register */ 223 __IOM uint32_t SHA_H5L; /* Offset: 0x01c (R/W) H5L register */ 224 __IOM uint32_t SHA_H6L; /* Offset: 0x020 (R/W) H6L register */ 225 __IOM uint32_t SHA_H7L; /* Offset: 0x024 (R/W) H7L register */ 226 __IOM uint32_t SHA_H0H; /* Offset: 0x028 (R/W) H0H register */ 227 __IOM uint32_t SHA_H1H; /* Offset: 0x02c (R/W) H1H register */ 228 __IOM uint32_t SHA_H2H; /* Offset: 0x030 (R/W) H2H register */ 229 __IOM uint32_t SHA_H3H; /* Offset: 0x034 (R/W) H3H register */ 230 __IOM uint32_t SHA_H4H; /* Offset: 0x038 (R/W) H4H register */ 231 __IOM uint32_t SHA_H5H; /* Offset: 0x03c (R/W) H5H register */ 232 __IOM uint32_t SHA_H6H; /* Offset: 0x040 (R/W) H6H register */ 233 __IOM uint32_t SHA_H7H; /* Offset: 0x044 (R/W) H7H register */ 234 __IOM uint32_t SHA_DATA1; /* Offset: 0x048 (R/W) DATA1 register */ 235 uint32_t REV[15]; 236 __IOM uint32_t SHA_DATA2; /* Offset: 0x088 (R/W) DATA2 register */ 237 } CSKY_SHA_TypeDef; 238 239 #endif 240 241 #define CONFIG_CRC_NUM 1 242 #define CONFIG_IIC_NUM 2 243 #define CONFIG_TRNG_NUM 1 244 #define CONFIG_EFLASH_NUM 1 245 #define CONFIG_AES_NUM 1 246 #define CONFIG_RSA_NUM 1 247 #define CONFIG_SHA_NUM 1 248 #define CONFIG_SPI_NUM 2 249 #define CONFIG_PWM_NUM 1 250 #define CONFIG_TIMER_NUM 4 251 #define CONFIG_RTC_NUM 1 252 #define CONFIG_WDT_NUM 1 253 #define CONFIG_DMAC_NUM 1 254 #define CONFIG_ETH_NUM 2 255 256 #define CSKY_I2C0_BASE (0x50014000UL) 257 #define CSKY_I2C1_BASE (0x60014000UL) 258 259 #define CONFIG_USART_NUM 4 260 #define CSKY_UART0_BASE (0x50010000UL) 261 #define CSKY_UART1_BASE (0x50010400UL) 262 #define CSKY_UART2_BASE (0x60010000UL) 263 #define CSKY_UART3_BASE (0x60010400UL) 264 265 /* ================================================================================ */ 266 /* ================ Peripheral memory map ================ */ 267 /* ================================================================================ */ 268 /* -------------------------- CPU FPGA memory map ------------------------------- */ 269 #define CSKY_EFLASH_BASE (0x10000000UL) 270 #define CSKY_SRAM_BASE (0x20000000UL) 271 272 #define CSKY_PMU_BASE (0x40000000UL) 273 #define CSKY_DMA_BASE (0x40001000UL) 274 #define CSKY_EFLASH_CONTROL_BASE (0x40005000UL) 275 #define CSKY_OTP_BASE (0x40006000UL) 276 #define CSKY_SRAM_CONTROL_BASE (0x40009000UL) 277 #define CSKY_AES_BASE (0x4000d000UL) 278 #define CSKY_SHA_BASE (0x4000e000UL) 279 #define CSKY_RSA_BASE (0x4000f000UL) 280 #define CSKY_CRC_BASE (0x40010000UL) 281 #define CSKY_TRNG_BASE (0x40015000UL) 282 #define CSKY_TIMERA0_BASE (0x50000000UL) 283 #define CSKY_TIMERA1_BASE (0x50000014UL) 284 #define CSKY_TIMERA_CONTROL_BASE (0x500000a0UL) 285 #define CSKY_RTC_BASE (0x50004000UL) 286 #define CSKY_WDT_BASE (0x50008000UL) 287 #define CSKY_SPI0_BASE (0x5000c000UL) 288 289 #define CONFIG_GPIO_NUM 2 290 #define CONFIG_GPIO_PIN_NUM 43 291 #define CSKY_GPIOA_BASE (0x50018000UL) 292 #define CSKY_GPIOA_CONTROL_BASE (0x50018030UL) 293 #define CSKY_PWM_BASE (0x5001c000UL) 294 #define CSKY_ADC_BASE (0x50020000UL) 295 #define CSKY_I2S0_BASE (0x50030000UL) 296 #define CSKY_TIMERB0_BASE (0x60000000UL) 297 #define CSKY_TIMERB1_BASE (0x60000014UL) 298 #define CSKY_SPI1_BASE (0x6000c000UL) 299 300 #define CSKY_GPIOB_BASE (0x60018000UL) 301 #define CSKY_GPIOB_CONTROL_BASE (0x60018030UL) 302 #define CSKY_TIMERB_CONTROL_BASE (0x600000a0UL) 303 #define CSKY_SIPC_BASE (0x6001c000UL) 304 #define CSKY_I2S1_BASE (0x60020000UL) 305 #define CSKY_ETB_BASE (0x60024000UL) 306 #define CSKY_USI_BASE (0x60028000UL) 307 308 /* ================================================================================ */ 309 /* ================ Peripheral declaration ================ */ 310 /* ================================================================================ */ 311 #define CSKY_UART1 (( CSKY_UART_TypeDef *) CSKY_UART1_BASE) 312 #define CSKY_SHA (( CSKY_SHA_TypeDef *) CSKY_SHA_BASE) 313 314 #ifdef __cplusplus 315 } 316 #endif 317 318 #endif /* SOC_H */ 319